change wifi driver to cypress

hc

2024-01-05 071106ecf68c401173c58808b1cf5f68cc50d390

 kernel/drivers/gpu/drm/radeon/radeon_object.c
..
..
@@ -29,14 +29,17 @@
29
29
  *    Thomas Hellstrom <thomas-at-tungstengraphics-dot-com>
30
30
  *    Dave Airlie
31
31
  */
32
+
33
+#include <linux/io.h>
32
34
 #include <linux/list.h>
33
35
 #include <linux/slab.h>
34
-#include <drm/drmP.h>
35
-#include <drm/radeon_drm.h>
36
+
36
37
 #include <drm/drm_cache.h>
38
+#include <drm/drm_prime.h>
39
+#include <drm/radeon_drm.h>
40
+
37
41
 #include "radeon.h"
38
42
 #include "radeon_trace.h"
39
-
40
43
 
41
44
 int radeon_ttm_init(struct radeon_device *rdev);
42
45
 void radeon_ttm_fini(struct radeon_device *rdev);
..
..
@@ -82,9 +85,9 @@
82
85
 	mutex_unlock(&bo->rdev->gem.mutex);
83
86
 	radeon_bo_clear_surface_reg(bo);
84
87
 	WARN_ON_ONCE(!list_empty(&bo->va));
85
-	if (bo->gem_base.import_attach)
86
-		drm_prime_gem_destroy(&bo->gem_base, bo->tbo.sg);
87
-	drm_gem_object_release(&bo->gem_base);
88
+	if (bo->tbo.base.import_attach)
89
+		drm_prime_gem_destroy(&bo->tbo.base, bo->tbo.sg);
90
+	drm_gem_object_release(&bo->tbo.base);
88
91
 	kfree(bo);
89
92
 }
90
93
 
..
..
@@ -109,58 +112,58 @@
109
112
 		    rbo->rdev->mc.visible_vram_size < rbo->rdev->mc.real_vram_size) {
110
113
 			rbo->placements[c].fpfn =
111
114
 				rbo->rdev->mc.visible_vram_size >> PAGE_SHIFT;
115
+			rbo->placements[c].mem_type = TTM_PL_VRAM;
112
116
 			rbo->placements[c++].flags = TTM_PL_FLAG_WC |
113
-						     TTM_PL_FLAG_UNCACHED |
114
-						     TTM_PL_FLAG_VRAM;
117
+						     TTM_PL_FLAG_UNCACHED;
115
118
 		}
116
119
 
117
120
 		rbo->placements[c].fpfn = 0;
121
+		rbo->placements[c].mem_type = TTM_PL_VRAM;
118
122
 		rbo->placements[c++].flags = TTM_PL_FLAG_WC |
119
-					     TTM_PL_FLAG_UNCACHED |
120
-					     TTM_PL_FLAG_VRAM;
123
+					     TTM_PL_FLAG_UNCACHED;
121
124
 	}
122
125
 
123
126
 	if (domain & RADEON_GEM_DOMAIN_GTT) {
124
127
 		if (rbo->flags & RADEON_GEM_GTT_UC) {
125
128
 			rbo->placements[c].fpfn = 0;
126
-			rbo->placements[c++].flags = TTM_PL_FLAG_UNCACHED |
127
-				TTM_PL_FLAG_TT;
129
+			rbo->placements[c].mem_type = TTM_PL_TT;
130
+			rbo->placements[c++].flags = TTM_PL_FLAG_UNCACHED;
128
131
 
129
132
 		} else if ((rbo->flags & RADEON_GEM_GTT_WC) ||
130
133
 			   (rbo->rdev->flags & RADEON_IS_AGP)) {
131
134
 			rbo->placements[c].fpfn = 0;
135
+			rbo->placements[c].mem_type = TTM_PL_TT;
132
136
 			rbo->placements[c++].flags = TTM_PL_FLAG_WC |
133
-				TTM_PL_FLAG_UNCACHED |
134
-				TTM_PL_FLAG_TT;
137
+				TTM_PL_FLAG_UNCACHED;
135
138
 		} else {
136
139
 			rbo->placements[c].fpfn = 0;
137
-			rbo->placements[c++].flags = TTM_PL_FLAG_CACHED |
138
-						     TTM_PL_FLAG_TT;
140
+			rbo->placements[c].mem_type = TTM_PL_TT;
141
+			rbo->placements[c++].flags = TTM_PL_FLAG_CACHED;
139
142
 		}
140
143
 	}
141
144
 
142
145
 	if (domain & RADEON_GEM_DOMAIN_CPU) {
143
146
 		if (rbo->flags & RADEON_GEM_GTT_UC) {
144
147
 			rbo->placements[c].fpfn = 0;
145
-			rbo->placements[c++].flags = TTM_PL_FLAG_UNCACHED |
146
-				TTM_PL_FLAG_SYSTEM;
148
+			rbo->placements[c].mem_type = TTM_PL_SYSTEM;
149
+			rbo->placements[c++].flags = TTM_PL_FLAG_UNCACHED;
147
150
 
148
151
 		} else if ((rbo->flags & RADEON_GEM_GTT_WC) ||
149
152
 		    rbo->rdev->flags & RADEON_IS_AGP) {
150
153
 			rbo->placements[c].fpfn = 0;
154
+			rbo->placements[c].mem_type = TTM_PL_SYSTEM;
151
155
 			rbo->placements[c++].flags = TTM_PL_FLAG_WC |
152
-				TTM_PL_FLAG_UNCACHED |
153
-				TTM_PL_FLAG_SYSTEM;
156
+				TTM_PL_FLAG_UNCACHED;
154
157
 		} else {
155
158
 			rbo->placements[c].fpfn = 0;
156
-			rbo->placements[c++].flags = TTM_PL_FLAG_CACHED |
157
-						     TTM_PL_FLAG_SYSTEM;
159
+			rbo->placements[c].mem_type = TTM_PL_SYSTEM;
160
+			rbo->placements[c++].flags = TTM_PL_FLAG_CACHED;
158
161
 		}
159
162
 	}
160
163
 	if (!c) {
161
164
 		rbo->placements[c].fpfn = 0;
162
-		rbo->placements[c++].flags = TTM_PL_MASK_CACHING |
163
-					     TTM_PL_FLAG_SYSTEM;
165
+		rbo->placements[c].mem_type = TTM_PL_SYSTEM;
166
+		rbo->placements[c++].flags = TTM_PL_MASK_CACHING;
164
167
 	}
165
168
 
166
169
 	rbo->placement.num_placement = c;
..
..
@@ -168,7 +171,7 @@
168
171
 
169
172
 	for (i = 0; i < c; ++i) {
170
173
 		if ((rbo->flags & RADEON_GEM_CPU_ACCESS) &&
171
-		    (rbo->placements[i].flags & TTM_PL_FLAG_VRAM) &&
174
+		    (rbo->placements[i].mem_type == TTM_PL_VRAM) &&
172
175
 		    !rbo->placements[i].fpfn)
173
176
 			rbo->placements[i].lpfn =
174
177
 				rbo->rdev->mc.visible_vram_size >> PAGE_SHIFT;
..
..
@@ -180,7 +183,7 @@
180
183
 int radeon_bo_create(struct radeon_device *rdev,
181
184
 		     unsigned long size, int byte_align, bool kernel,
182
185
 		     u32 domain, u32 flags, struct sg_table *sg,
183
-		     struct reservation_object *resv,
186
+		     struct dma_resv *resv,
184
187
 		     struct radeon_bo **bo_ptr)
185
188
 {
186
189
 	struct radeon_bo *bo;
..
..
@@ -206,7 +209,7 @@
206
209
 	bo = kzalloc(sizeof(struct radeon_bo), GFP_KERNEL);
207
210
 	if (bo == NULL)
208
211
 		return -ENOMEM;
209
-	drm_gem_private_object_init(rdev->ddev, &bo->gem_base, size);
212
+	drm_gem_private_object_init(rdev->ddev, &bo->tbo.base, size);
210
213
 	bo->rdev = rdev;
211
214
 	bo->surface_reg = -1;
212
215
 	INIT_LIST_HEAD(&bo->list);
..
..
@@ -314,11 +317,9 @@
314
317
 void radeon_bo_unref(struct radeon_bo **bo)
315
318
 {
316
319
 	struct ttm_buffer_object *tbo;
317
-	struct radeon_device *rdev;
318
320
 
319
321
 	if ((*bo) == NULL)
320
322
 		return;
321
-	rdev = (*bo)->rdev;
322
323
 	tbo = &((*bo)->tbo);
323
324
 	ttm_bo_put(tbo);
324
325
 	*bo = NULL;
..
..
@@ -330,7 +331,7 @@
330
331
 	struct ttm_operation_ctx ctx = { false, false };
331
332
 	int r, i;
332
333
 
333
-	if (radeon_ttm_tt_has_userptr(bo->tbo.ttm))
334
+	if (radeon_ttm_tt_has_userptr(bo->rdev, bo->tbo.ttm))
334
335
 		return -EPERM;
335
336
 
336
337
 	if (bo->pin_count) {
..
..
@@ -359,7 +360,7 @@
359
360
 	radeon_ttm_placement_from_domain(bo, domain);
360
361
 	for (i = 0; i < bo->placement.num_placement; i++) {
361
362
 		/* force to pin into visible video ram */
362
-		if ((bo->placements[i].flags & TTM_PL_FLAG_VRAM) &&
363
+		if ((bo->placements[i].mem_type == TTM_PL_VRAM) &&
363
364
 		    !(bo->flags & RADEON_GEM_NO_CPU_ACCESS) &&
364
365
 		    (!max_offset || max_offset > bo->rdev->mc.visible_vram_size))
365
366
 			bo->placements[i].lpfn =
..
..
@@ -421,11 +422,13 @@
421
422
 int radeon_bo_evict_vram(struct radeon_device *rdev)
422
423
 {
423
424
 	/* late 2.6.33 fix IGP hibernate - we need pm ops to do this correct */
424
-	if (0 && (rdev->flags & RADEON_IS_IGP)) {
425
+#ifndef CONFIG_HIBERNATION
426
+	if (rdev->flags & RADEON_IS_IGP) {
425
427
 		if (rdev->mc.igp_sideport_enabled == false)
426
428
 			/* Useless to evict on IGP chips */
427
429
 			return 0;
428
430
 	}
431
+#endif
429
432
 	return ttm_bo_evict_mm(&rdev->mman.bdev, TTM_PL_VRAM);
430
433
 }
431
434
 
..
..
@@ -439,13 +442,13 @@
439
442
 	dev_err(rdev->dev, "Userspace still has active objects !\n");
440
443
 	list_for_each_entry_safe(bo, n, &rdev->gem.objects, list) {
441
444
 		dev_err(rdev->dev, "%p %p %lu %lu force free\n",
442
-			&bo->gem_base, bo, (unsigned long)bo->gem_base.size,
443
-			*((unsigned long *)&bo->gem_base.refcount));
445
+			&bo->tbo.base, bo, (unsigned long)bo->tbo.base.size,
446
+			*((unsigned long *)&bo->tbo.base.refcount));
444
447
 		mutex_lock(&bo->rdev->gem.mutex);
445
448
 		list_del_init(&bo->list);
446
449
 		mutex_unlock(&bo->rdev->gem.mutex);
447
450
 		/* this should unref the ttm bo */
448
-		drm_gem_object_put_unlocked(&bo->gem_base);
451
+		drm_gem_object_put(&bo->tbo.base);
449
452
 	}
450
453
 }
451
454
 
..
..
@@ -607,7 +610,7 @@
607
610
 	int steal;
608
611
 	int i;
609
612
 
610
-	lockdep_assert_held(&bo->tbo.resv->lock.base);
613
+	dma_resv_assert_held(bo->tbo.base.resv);
611
614
 
612
615
 	if (!bo->tiling_flags)
613
616
 		return 0;
..
..
@@ -733,7 +736,7 @@
733
736
 				uint32_t *tiling_flags,
734
737
 				uint32_t *pitch)
735
738
 {
736
-	lockdep_assert_held(&bo->tbo.resv->lock.base);
739
+	dma_resv_assert_held(bo->tbo.base.resv);
737
740
 
738
741
 	if (tiling_flags)
739
742
 		*tiling_flags = bo->tiling_flags;
..
..
@@ -745,7 +748,7 @@
745
748
 				bool force_drop)
746
749
 {
747
750
 	if (!force_drop)
748
-		lockdep_assert_held(&bo->tbo.resv->lock.base);
751
+		dma_resv_assert_held(bo->tbo.base.resv);
749
752
 
750
753
 	if (!(bo->tiling_flags & RADEON_TILING_SURFACE))
751
754
 		return 0;
..
..
@@ -772,7 +775,7 @@
772
775
 
773
776
 void radeon_bo_move_notify(struct ttm_buffer_object *bo,
774
777
 			   bool evict,
775
-			   struct ttm_mem_reg *new_mem)
778
+			   struct ttm_resource *new_mem)
776
779
 {
777
780
 	struct radeon_bo *rbo;
778
781
 
..
..
@@ -821,7 +824,7 @@
821
824
 	lpfn =	rdev->mc.visible_vram_size >> PAGE_SHIFT;
822
825
 	for (i = 0; i < rbo->placement.num_placement; i++) {
823
826
 		/* Force into visible VRAM */
824
-		if ((rbo->placements[i].flags & TTM_PL_FLAG_VRAM) &&
827
+		if ((rbo->placements[i].mem_type == TTM_PL_VRAM) &&
825
828
 		    (!rbo->placements[i].lpfn || rbo->placements[i].lpfn > lpfn))
826
829
 			rbo->placements[i].lpfn = lpfn;
827
830
 	}
..
..
@@ -867,10 +870,10 @@
867
870
 void radeon_bo_fence(struct radeon_bo *bo, struct radeon_fence *fence,
868
871
 		     bool shared)
869
872
 {
870
-	struct reservation_object *resv = bo->tbo.resv;
873
+	struct dma_resv *resv = bo->tbo.base.resv;
871
874
 
872
875
 	if (shared)
873
-		reservation_object_add_shared_fence(resv, &fence->base);
876
+		dma_resv_add_shared_fence(resv, &fence->base);
874
877
 	else
875
-		reservation_object_add_excl_fence(resv, &fence->base);
878
+		dma_resv_add_excl_fence(resv, &fence->base);
876
879
 }