~hc/RK356X_SDK_RELEASE.git

..	..	@@ -21,25 +21,32 @@
21	21	* DEALINGS IN THE SOFTWARE.
22	22	*/
23	23
24		-#include <linux/backlight.h>
	24	+#include <linux/delay.h>
25	25	#include <linux/gpio/consumer.h>
	26	+#include <linux/iopoll.h>
26	27	#include <linux/module.h>
27	28	#include <linux/of_platform.h>
28	29	#include <linux/platform_device.h>
29	30	#include <linux/regulator/consumer.h>
30		-
31		-#include <drm/drmP.h>
32		-#include <drm/drm_crtc.h>
33		-#include <drm/drm_mipi_dsi.h>
34		-#include <drm/drm_panel.h>
	31	+#include <linux/spi/spi.h>
35	32
36	33	#include <video/display_timing.h>
37	34	#include <video/mipi_display.h>
38	35	#include <video/of_display_timing.h>
39		-#include <linux/of_graph.h>
40	36	#include <video/videomode.h>
41	37
42		-#include "../rockchip/rockchip_drm_drv.h"
	38	+#include <drm/drm_crtc.h>
	39	+#include <drm/drm_device.h>
	40	+#include <drm/drm_mipi_dsi.h>
	41	+#include <drm/drm_panel.h>
	42	+#include <drm/drm_dsc.h>
	43	+
	44	+#include "panel-simple.h"
	45	+
	46	+enum panel_simple_cmd_type {
	47	+ CMD_TYPE_DEFAULT,
	48	+ CMD_TYPE_SPI
	49	+};
43	50
44	51	struct panel_cmd_header {
45	52	u8 data_type;
..	..	@@ -57,6 +64,22 @@
57	64	unsigned int cmd_cnt;
58	65	};
59	66
	67	+/**
	68	+ * @modes: Pointer to array of fixed modes appropriate for this panel. If
	69	+ * only one mode then this can just be the address of this the mode.
	70	+ * NOTE: cannot be used with "timings" and also if this is specified
	71	+ * then you cannot override the mode in the device tree.
	72	+ * @num_modes: Number of elements in modes array.
	73	+ * @timings: Pointer to array of display timings. NOTE: cannot be used with
	74	+ * "modes" and also these will be used to validate a device tree
	75	+ * override if one is present.
	76	+ * @num_timings: Number of elements in timings array.
	77	+ * @bpc: Bits per color.
	78	+ * @size: Structure containing the physical size of this panel.
	79	+ * @delay: Structure containing various delay values for this panel.
	80	+ * @bus_format: See MEDIA_BUS_FMT_... defines.
	81	+ * @bus_flags: See DRM_BUS_FLAG_... defines.
	82	+ */
60	83	struct panel_desc {
61	84	const struct drm_display_mode *modes;
62	85	unsigned int num_modes;
..	..	@@ -77,6 +100,8 @@
77	100	/**
78	101	* @prepare: the time (in milliseconds) that it takes for the panel to
79	102	* become ready and start receiving video data
	103	+ * @hpd_absent_delay: Add this to the prepare delay if we know Hot
	104	+ * Plug Detect isn't used.
80	105	* @enable: the time (in milliseconds) that it takes for the panel to
81	106	* display the first valid frame after starting to receive
82	107	* video data
..	..	@@ -91,6 +116,7 @@
91	116	*/
92	117	struct {
93	118	unsigned int prepare;
	119	+ unsigned int hpd_absent_delay;
94	120	unsigned int enable;
95	121	unsigned int disable;
96	122	unsigned int unprepare;
..	..	@@ -100,9 +126,15 @@
100	126
101	127	u32 bus_format;
102	128	u32 bus_flags;
	129	+ int connector_type;
103	130
104	131	struct panel_cmd_seq *init_seq;
105	132	struct panel_cmd_seq *exit_seq;
	133	+
	134	+ enum panel_simple_cmd_type cmd_type;
	135	+
	136	+ int (spi_read)(struct device dev, const u8 cmd, u8 *val);
	137	+ int (spi_write)(struct device dev, const u8 *data, size_t len, u8 type);
106	138	};
107	139
108	140	struct panel_simple {
..	..	@@ -111,61 +143,26 @@
111	143	bool prepared;
112	144	bool enabled;
113	145	bool power_invert;
	146	+ bool no_hpd;
114	147
115	148	const struct panel_desc *desc;
116	149
117		- struct backlight_device *backlight;
118	150	struct regulator *supply;
119		- struct regulator_bulk_data supplies[2];
120	151	struct i2c_adapter *ddc;
121	152
122	153	struct gpio_desc *enable_gpio;
123	154	struct gpio_desc *reset_gpio;
124		- int cmd_type;
	155	+ struct gpio_desc *hpd_gpio;
125	156
126		- struct gpio_desc *spi_sdi_gpio;
127		- struct gpio_desc *spi_scl_gpio;
128		- struct gpio_desc *spi_cs_gpio;
129		- struct device_node *np_crtc;
	157	+ struct drm_display_mode override_mode;
	158	+
	159	+ struct drm_dsc_picture_parameter_set *pps;
	160	+ enum drm_panel_orientation orientation;
130	161	};
131	162
132		-enum rockchip_cmd_type {
133		- CMD_TYPE_DEFAULT,
134		- CMD_TYPE_SPI,
135		- CMD_TYPE_MCU
136		-};
137		-
138		-enum MCU_IOCTL {
139		- MCU_WRCMD = 0,
140		- MCU_WRDATA,
141		- MCU_SETBYPASS,
142		-};
143		-
144		-enum rockchip_spi_cmd_type {
145		- SPI_3LINE_9BIT_MODE_CMD = 0,
146		- SPI_3LINE_9BIT_MODE_DATA,
147		- SPI_4LINE_8BIT_MODE,
148		-};
149		-
150		-static void panel_simple_sleep(unsigned int msec)
	163	+static inline void panel_simple_msleep(unsigned int msecs)
151	164	{
152		- if (msec > 20)
153		- msleep(msec);
154		- else
155		- usleep_range(msec * 1000, (msec + 1) * 1000);
156		-}
157		-
158		-static inline int get_panel_cmd_type(const char *s)
159		-{
160		- if (!s)
161		- return -EINVAL;
162		-
163		- if (strncmp(s, "spi", 3) == 0)
164		- return CMD_TYPE_SPI;
165		- else if (strncmp(s, "mcu", 3) == 0)
166		- return CMD_TYPE_MCU;
167		-
168		- return CMD_TYPE_DEFAULT;
	165	+ usleep_range(msecs * 1000, msecs * 1000 + 100);
169	166	}
170	167
171	168	static inline struct panel_simple to_panel_simple(struct drm_panel panel)
..	..	@@ -232,109 +229,16 @@
232	229	return 0;
233	230	}
234	231
235		-static void panel_simple_spi_write_cmd(struct panel_simple *panel,
236		- u8 type, int value)
237		-{
238		- int i;
239		-
240		- gpiod_direction_output(panel->spi_cs_gpio, 0);
241		-
242		- /**
243		- * send cmd or data flag for 3line 9bit serial data
244		- */
245		- if (type == SPI_3LINE_9BIT_MODE_CMD) {
246		- gpiod_direction_output(panel->spi_sdi_gpio, 0);
247		- gpiod_direction_output(panel->spi_scl_gpio, 0);
248		- udelay(10);
249		- gpiod_direction_output(panel->spi_scl_gpio, 1);
250		- udelay(10);
251		- } else if (type == SPI_3LINE_9BIT_MODE_DATA) {
252		- gpiod_direction_output(panel->spi_sdi_gpio, 1);
253		- gpiod_direction_output(panel->spi_scl_gpio, 0);
254		- udelay(10);
255		- gpiod_direction_output(panel->spi_scl_gpio, 1);
256		- udelay(10);
257		- }
258		-
259		- /**
260		- * send the 8bit value from the MSB
261		- */
262		- for (i = 0; i < 8; i++) {
263		- if (value & 0x80)
264		- gpiod_direction_output(panel->spi_sdi_gpio, 1);
265		- else
266		- gpiod_direction_output(panel->spi_sdi_gpio, 0);
267		-
268		- gpiod_direction_output(panel->spi_scl_gpio, 0);
269		- udelay(10);
270		- gpiod_direction_output(panel->spi_scl_gpio, 1);
271		- value <<= 1;
272		- udelay(10);
273		- }
274		-
275		- gpiod_direction_output(panel->spi_cs_gpio, 1);
276		-}
277		-
278		-static int panel_simple_xfer_mcu_cmd_seq(struct panel_simple *panel,
279		- struct panel_cmd_seq *cmds)
280		-{
281		- int i;
282		-
283		- if (!cmds)
284		- return -EINVAL;
285		-
286		- rockchip_drm_crtc_send_mcu_cmd(panel->base.drm,
287		- panel->np_crtc, MCU_SETBYPASS, 1);
288		- for (i = 0; i < cmds->cmd_cnt; i++) {
289		- struct panel_cmd_desc *cmd = &cmds->cmds[i];
290		- u32 value = 0;
291		-
292		- value = cmd->payload[0];
293		- rockchip_drm_crtc_send_mcu_cmd(panel->base.drm, panel->np_crtc,
294		- cmd->header.data_type, value);
295		- if (cmd->header.delay)
296		- panel_simple_sleep(cmd->header.delay);
297		- }
298		- rockchip_drm_crtc_send_mcu_cmd(panel->base.drm,
299		- panel->np_crtc, MCU_SETBYPASS, 0);
300		-
301		- return 0;
302		-}
303		-
304		-static int panel_simple_xfer_spi_cmd_seq(struct panel_simple *panel,
305		- struct panel_cmd_seq *cmds)
306		-{
307		- int i;
308		-
309		- if (!cmds)
310		- return -EINVAL;
311		-
312		- for (i = 0; i < cmds->cmd_cnt; i++) {
313		- struct panel_cmd_desc *cmd = &cmds->cmds[i];
314		- int value = 0;
315		-
316		- if (cmd->header.payload_length == 2)
317		- value = (cmd->payload[0] << 8) \| cmd->payload[1];
318		- else
319		- value = cmd->payload[0];
320		- panel_simple_spi_write_cmd(panel, cmd->header.data_type, value);
321		-
322		- if (cmd->header.delay)
323		- panel_simple_sleep(cmd->header.delay);
324		- }
325		-
326		- return 0;
327		-}
328		-
329		-#if IS_ENABLED(CONFIG_DRM_MIPI_DSI)
330	232	static int panel_simple_xfer_dsi_cmd_seq(struct panel_simple *panel,
331		- struct panel_cmd_seq *seq)
	233	+ struct panel_cmd_seq *seq)
332	234	{
333	235	struct device *dev = panel->base.dev;
334	236	struct mipi_dsi_device *dsi = panel->dsi;
335	237	unsigned int i;
336	238	int err;
337	239
	240	+ if (!IS_ENABLED(CONFIG_DRM_MIPI_DSI))
	241	+ return -EINVAL;
338	242	if (!seq)
339	243	return -EINVAL;
340	244
..	..	@@ -342,6 +246,9 @@
342	246	struct panel_cmd_desc *cmd = &seq->cmds[i];
343	247
344	248	switch (cmd->header.data_type) {
	249	+ case MIPI_DSI_COMPRESSION_MODE:
	250	+ err = mipi_dsi_compression_mode(dsi, cmd->payload[0]);
	251	+ break;
345	252	case MIPI_DSI_GENERIC_SHORT_WRITE_0_PARAM:
346	253	case MIPI_DSI_GENERIC_SHORT_WRITE_1_PARAM:
347	254	case MIPI_DSI_GENERIC_SHORT_WRITE_2_PARAM:
..	..	@@ -355,6 +262,18 @@
355	262	err = mipi_dsi_dcs_write_buffer(dsi, cmd->payload,
356	263	cmd->header.payload_length);
357	264	break;
	265	+ case MIPI_DSI_PICTURE_PARAMETER_SET:
	266	+ if (!panel->pps) {
	267	+ panel->pps = devm_kzalloc(dev, sizeof(*panel->pps),
	268	+ GFP_KERNEL);
	269	+ if (!panel->pps)
	270	+ return -ENOMEM;
	271	+
	272	+ memcpy(panel->pps, cmd->payload, cmd->header.payload_length);
	273	+ }
	274	+
	275	+ err = mipi_dsi_picture_parameter_set(dsi, panel->pps);
	276	+ break;
358	277	default:
359	278	return -EINVAL;
360	279	}
..	..	@@ -363,37 +282,49 @@
363	282	dev_err(dev, "failed to write dcs cmd: %d\n", err);
364	283
365	284	if (cmd->header.delay)
366		- panel_simple_sleep(cmd->header.delay);
	285	+ panel_simple_msleep(cmd->header.delay);
367	286	}
368	287
369	288	return 0;
370	289	}
371		-#else
372		-static inline int panel_simple_xfer_dsi_cmd_seq(struct panel_simple *panel,
373		- struct panel_cmd_seq *seq)
374		-{
375		- return -EINVAL;
376		-}
377		-#endif
378	290
379		-static int panel_simple_get_fixed_modes(struct panel_simple *panel)
	291	+static int panel_simple_xfer_spi_cmd_seq(struct panel_simple panel, struct panel_cmd_seq cmds)
380	292	{
381		- struct drm_connector *connector = panel->base.connector;
382		- struct drm_device *drm = panel->base.drm;
	293	+ int i;
	294	+ int ret;
	295	+
	296	+ if (!cmds)
	297	+ return -EINVAL;
	298	+
	299	+ for (i = 0; i < cmds->cmd_cnt; i++) {
	300	+ struct panel_cmd_desc *cmd = &cmds->cmds[i];
	301	+
	302	+ ret = panel->desc->spi_write(panel->base.dev, cmd->payload,
	303	+ cmd->header.payload_length, cmd->header.data_type);
	304	+ if (ret)
	305	+ return ret;
	306	+
	307	+ if (cmd->header.delay)
	308	+ panel_simple_msleep(cmd->header.delay);
	309	+ }
	310	+
	311	+ return 0;
	312	+}
	313	+
	314	+static unsigned int panel_simple_get_timings_modes(struct panel_simple *panel,
	315	+ struct drm_connector *connector)
	316	+{
383	317	struct drm_display_mode *mode;
384	318	unsigned int i, num = 0;
385		-
386		- if (!panel->desc)
387		- return 0;
388	319
389	320	for (i = 0; i < panel->desc->num_timings; i++) {
390	321	const struct display_timing *dt = &panel->desc->timings[i];
391	322	struct videomode vm;
392	323
393	324	videomode_from_timing(dt, &vm);
394		- mode = drm_mode_create(drm);
	325	+ mode = drm_mode_create(connector->dev);
395	326	if (!mode) {
396		- dev_err(drm->dev, "failed to add mode %ux%u\n",
	327	+ dev_err(panel->base.dev, "failed to add mode %ux%u\n",
397	328	dt->hactive.typ, dt->vactive.typ);
398	329	continue;
399	330	}
..	..	@@ -409,13 +340,23 @@
409	340	num++;
410	341	}
411	342
	343	+ return num;
	344	+}
	345	+
	346	+static unsigned int panel_simple_get_display_modes(struct panel_simple *panel,
	347	+ struct drm_connector *connector)
	348	+{
	349	+ struct drm_display_mode *mode;
	350	+ unsigned int i, num = 0;
	351	+
412	352	for (i = 0; i < panel->desc->num_modes; i++) {
413	353	const struct drm_display_mode *m = &panel->desc->modes[i];
414	354
415		- mode = drm_mode_duplicate(drm, m);
	355	+ mode = drm_mode_duplicate(connector->dev, m);
416	356	if (!mode) {
417		- dev_err(drm->dev, "failed to add mode %ux%u@%u\n",
418		- m->hdisplay, m->vdisplay, m->vrefresh);
	357	+ dev_err(panel->base.dev, "failed to add mode %ux%u@%u\n",
	358	+ m->hdisplay, m->vdisplay,
	359	+ drm_mode_vrefresh(m));
419	360	continue;
420	361	}
421	362
..	..	@@ -429,6 +370,44 @@
429	370	drm_mode_probed_add(connector, mode);
430	371	num++;
431	372	}
	373	+
	374	+ return num;
	375	+}
	376	+
	377	+static int panel_simple_get_non_edid_modes(struct panel_simple *panel,
	378	+ struct drm_connector *connector)
	379	+{
	380	+ struct drm_display_mode *mode;
	381	+ bool has_override = panel->override_mode.type;
	382	+ unsigned int num = 0;
	383	+
	384	+ if (!panel->desc)
	385	+ return 0;
	386	+
	387	+ if (has_override) {
	388	+ mode = drm_mode_duplicate(connector->dev,
	389	+ &panel->override_mode);
	390	+ if (mode) {
	391	+ drm_mode_probed_add(connector, mode);
	392	+ num = 1;
	393	+ } else {
	394	+ dev_err(panel->base.dev, "failed to add override mode\n");
	395	+ }
	396	+ }
	397	+
	398	+ /* Only add timings if override was not there or failed to validate */
	399	+ if (num == 0 && panel->desc->num_timings)
	400	+ num = panel_simple_get_timings_modes(panel, connector);
	401	+
	402	+ /*
	403	+ * Only add fixed modes if timings/override added no mode.
	404	+ *
	405	+ * We should only ever have either the display timings specified
	406	+ * or a fixed mode. Anything else is rather bogus.
	407	+ */
	408	+ WARN_ON(panel->desc->num_timings && panel->desc->num_modes);
	409	+ if (num == 0)
	410	+ num = panel_simple_get_display_modes(panel, connector);
432	411
433	412	if (panel->desc->bpc)
434	413	connector->display_info.bpc = panel->desc->bpc;
..	..	@@ -448,10 +427,6 @@
448	427	static int panel_simple_regulator_enable(struct panel_simple *p)
449	428	{
450	429	int err;
451		-
452		- err = regulator_bulk_enable(ARRAY_SIZE(p->supplies), p->supplies);
453		- if (err < 0)
454		- return err;
455	430
456	431	if (p->power_invert) {
457	432	if (regulator_is_enabled(p->supply) > 0)
..	..	@@ -479,55 +454,37 @@
479	454	regulator_disable(p->supply);
480	455	}
481	456
482		- regulator_bulk_disable(ARRAY_SIZE(p->supplies), p->supplies);
483		-
484	457	return 0;
485	458	}
486	459
487		-static int panel_simple_loader_protect(struct drm_panel *panel, bool on)
	460	+int panel_simple_loader_protect(struct drm_panel *panel)
488	461	{
489	462	struct panel_simple *p = to_panel_simple(panel);
490	463	int err;
491	464
492		- if (on) {
493		- err = panel_simple_regulator_enable(p);
494		- if (err < 0) {
495		- dev_err(panel->dev, "failed to enable supply: %d\n",
496		- err);
497		- return err;
498		- }
499		-
500		- p->prepared = true;
501		- p->enabled = true;
502		- } else {
503		- /* do nothing */
	465	+ err = panel_simple_regulator_enable(p);
	466	+ if (err < 0) {
	467	+ dev_err(panel->dev, "failed to enable supply: %d\n", err);
	468	+ return err;
504	469	}
	470	+
	471	+ p->prepared = true;
	472	+ p->enabled = true;
505	473
506	474	return 0;
507	475	}
	476	+EXPORT_SYMBOL(panel_simple_loader_protect);
508	477
509	478	static int panel_simple_disable(struct drm_panel *panel)
510	479	{
511	480	struct panel_simple *p = to_panel_simple(panel);
512		- int err = 0;
513	481
514	482	if (!p->enabled)
515	483	return 0;
516	484
517		- if (p->backlight) {
518		- p->backlight->props.power = FB_BLANK_POWERDOWN;
519		- p->backlight->props.state \|= BL_CORE_FBBLANK;
520		- backlight_update_status(p->backlight);
521		- }
522		-
523	485	if (p->desc->delay.disable)
524		- panel_simple_sleep(p->desc->delay.disable);
	486	+ panel_simple_msleep(p->desc->delay.disable);
525	487
526		- if (p->cmd_type == CMD_TYPE_MCU) {
527		- err = panel_simple_xfer_mcu_cmd_seq(p, p->desc->exit_seq);
528		- if (err)
529		- dev_err(panel->dev, "failed to send exit cmds seq\n");
530		- }
531	488	p->enabled = false;
532	489
533	490	return 0;
..	..	@@ -536,30 +493,56 @@
536	493	static int panel_simple_unprepare(struct drm_panel *panel)
537	494	{
538	495	struct panel_simple *p = to_panel_simple(panel);
539		- int err = 0;
540	496
541	497	if (!p->prepared)
542	498	return 0;
543	499
544	500	if (p->desc->exit_seq) {
545		- if (p->dsi)
546		- panel_simple_xfer_dsi_cmd_seq(p, p->desc->exit_seq);
547		- else if (p->cmd_type == CMD_TYPE_SPI)
548		- err = panel_simple_xfer_spi_cmd_seq(p, p->desc->exit_seq);
549		- if (err)
550		- dev_err(panel->dev, "failed to send exit cmds seq\n");
	501	+ if (p->desc->cmd_type == CMD_TYPE_SPI) {
	502	+ if (panel_simple_xfer_spi_cmd_seq(p, p->desc->exit_seq)) {
	503	+ dev_err(panel->dev, "failed to send exit spi cmds seq\n");
	504	+ return -EINVAL;
	505	+ }
	506	+ } else {
	507	+ if (p->dsi)
	508	+ panel_simple_xfer_dsi_cmd_seq(p, p->desc->exit_seq);
	509	+ }
551	510	}
552	511
553	512	gpiod_direction_output(p->reset_gpio, 1);
554		-
555	513	gpiod_direction_output(p->enable_gpio, 0);
556	514
557	515	panel_simple_regulator_disable(p);
558	516
559	517	if (p->desc->delay.unprepare)
560		- panel_simple_sleep(p->desc->delay.unprepare);
	518	+ panel_simple_msleep(p->desc->delay.unprepare);
561	519
562	520	p->prepared = false;
	521	+
	522	+ return 0;
	523	+}
	524	+
	525	+static int panel_simple_get_hpd_gpio(struct device *dev,
	526	+ struct panel_simple *p, bool from_probe)
	527	+{
	528	+ int err;
	529	+
	530	+ p->hpd_gpio = devm_gpiod_get_optional(dev, "hpd", GPIOD_IN);
	531	+ if (IS_ERR(p->hpd_gpio)) {
	532	+ err = PTR_ERR(p->hpd_gpio);
	533	+
	534	+ /*
	535	+ * If we're called from probe we won't consider '-EPROBE_DEFER'
	536	+ * to be an error--we'll leave the error code in "hpd_gpio".
	537	+ * When we try to use it we'll try again. This allows for
	538	+ * circular dependencies where the component providing the
	539	+ * hpd gpio needs the panel to init before probing.
	540	+ */
	541	+ if (err != -EPROBE_DEFER \|\| !from_probe) {
	542	+ dev_err(dev, "failed to get 'hpd' GPIO: %d\n", err);
	543	+ return err;
	544	+ }
	545	+ }
563	546
564	547	return 0;
565	548	}
..	..	@@ -567,7 +550,9 @@
567	550	static int panel_simple_prepare(struct drm_panel *panel)
568	551	{
569	552	struct panel_simple *p = to_panel_simple(panel);
	553	+ unsigned int delay;
570	554	int err;
	555	+ int hpd_asserted;
571	556
572	557	if (p->prepared)
573	558	return 0;
..	..	@@ -580,26 +565,52 @@
580	565
581	566	gpiod_direction_output(p->enable_gpio, 1);
582	567
583		- if (p->desc->delay.prepare)
584		- panel_simple_sleep(p->desc->delay.prepare);
	568	+ delay = p->desc->delay.prepare;
	569	+ if (p->no_hpd)
	570	+ delay += p->desc->delay.hpd_absent_delay;
	571	+ if (delay)
	572	+ panel_simple_msleep(delay);
	573	+
	574	+ if (p->hpd_gpio) {
	575	+ if (IS_ERR(p->hpd_gpio)) {
	576	+ err = panel_simple_get_hpd_gpio(panel->dev, p, false);
	577	+ if (err)
	578	+ return err;
	579	+ }
	580	+
	581	+ err = readx_poll_timeout(gpiod_get_value_cansleep, p->hpd_gpio,
	582	+ hpd_asserted, hpd_asserted,
	583	+ 1000, 2000000);
	584	+ if (hpd_asserted < 0)
	585	+ err = hpd_asserted;
	586	+
	587	+ if (err) {
	588	+ dev_err(panel->dev,
	589	+ "error waiting for hpd GPIO: %d\n", err);
	590	+ return err;
	591	+ }
	592	+ }
585	593
586	594	gpiod_direction_output(p->reset_gpio, 1);
587	595
588	596	if (p->desc->delay.reset)
589		- panel_simple_sleep(p->desc->delay.reset);
	597	+ panel_simple_msleep(p->desc->delay.reset);
590	598
591	599	gpiod_direction_output(p->reset_gpio, 0);
592	600
593	601	if (p->desc->delay.init)
594		- panel_simple_sleep(p->desc->delay.init);
	602	+ panel_simple_msleep(p->desc->delay.init);
595	603
596	604	if (p->desc->init_seq) {
597		- if (p->dsi)
598		- panel_simple_xfer_dsi_cmd_seq(p, p->desc->init_seq);
599		- else if (p->cmd_type == CMD_TYPE_SPI)
600		- err = panel_simple_xfer_spi_cmd_seq(p, p->desc->init_seq);
601		- if (err)
602		- dev_err(panel->dev, "failed to send init cmds seq\n");
	605	+ if (p->desc->cmd_type == CMD_TYPE_SPI) {
	606	+ if (panel_simple_xfer_spi_cmd_seq(p, p->desc->init_seq)) {
	607	+ dev_err(panel->dev, "failed to send init spi cmds seq\n");
	608	+ return -EINVAL;
	609	+ }
	610	+ } else {
	611	+ if (p->dsi)
	612	+ panel_simple_xfer_dsi_cmd_seq(p, p->desc->init_seq);
	613	+ }
603	614	}
604	615
605	616	p->prepared = true;
..	..	@@ -610,47 +621,40 @@
610	621	static int panel_simple_enable(struct drm_panel *panel)
611	622	{
612	623	struct panel_simple *p = to_panel_simple(panel);
613		- int err = 0;
614	624
615	625	if (p->enabled)
616	626	return 0;
617	627
618		- if (p->cmd_type == CMD_TYPE_MCU) {
619		- err = panel_simple_xfer_mcu_cmd_seq(p, p->desc->init_seq);
620		- if (err)
621		- dev_err(panel->dev, "failed to send init cmds seq\n");
622		- }
623	628	if (p->desc->delay.enable)
624		- panel_simple_sleep(p->desc->delay.enable);
625		-
626		- if (p->backlight) {
627		- p->backlight->props.state &= ~BL_CORE_FBBLANK;
628		- p->backlight->props.power = FB_BLANK_UNBLANK;
629		- backlight_update_status(p->backlight);
630		- }
	629	+ panel_simple_msleep(p->desc->delay.enable);
631	630
632	631	p->enabled = true;
633	632
634	633	return 0;
635	634	}
636	635
637		-static int panel_simple_get_modes(struct drm_panel *panel)
	636	+static int panel_simple_get_modes(struct drm_panel *panel,
	637	+ struct drm_connector *connector)
638	638	{
639	639	struct panel_simple *p = to_panel_simple(panel);
640	640	int num = 0;
641	641
642	642	/* probe EDID if a DDC bus is available */
643	643	if (p->ddc) {
644		- struct edid *edid = drm_get_edid(panel->connector, p->ddc);
645		- drm_connector_update_edid_property(panel->connector, edid);
	644	+ struct edid *edid = drm_get_edid(connector, p->ddc);
	645	+
	646	+ drm_connector_update_edid_property(connector, edid);
646	647	if (edid) {
647		- num += drm_add_edid_modes(panel->connector, edid);
	648	+ num += drm_add_edid_modes(connector, edid);
648	649	kfree(edid);
649	650	}
650	651	}
651	652
652	653	/* add hard-coded panel modes */
653		- num += panel_simple_get_fixed_modes(p);
	654	+ num += panel_simple_get_non_edid_modes(p, connector);
	655	+
	656	+ /* set up connector's "panel orientation" property */
	657	+ drm_connector_set_panel_orientation(connector, p->orientation);
654	658
655	659	return num;
656	660	}
..	..	@@ -673,7 +677,6 @@
673	677	}
674	678
675	679	static const struct drm_panel_funcs panel_simple_funcs = {
676		- .loader_protect = panel_simple_loader_protect,
677	680	.disable = panel_simple_disable,
678	681	.unprepare = panel_simple_unprepare,
679	682	.prepare = panel_simple_prepare,
..	..	@@ -682,11 +685,154 @@
682	685	.get_timings = panel_simple_get_timings,
683	686	};
684	687
	688	+static struct panel_desc panel_dpi;
	689	+
	690	+static int panel_dpi_probe(struct device *dev,
	691	+ struct panel_simple *panel)
	692	+{
	693	+ struct display_timing *timing;
	694	+ const struct device_node *np;
	695	+ struct panel_desc *desc;
	696	+ unsigned int bus_flags;
	697	+ struct videomode vm;
	698	+ int ret;
	699	+
	700	+ np = dev->of_node;
	701	+ desc = devm_kzalloc(dev, sizeof(*desc), GFP_KERNEL);
	702	+ if (!desc)
	703	+ return -ENOMEM;
	704	+
	705	+ timing = devm_kzalloc(dev, sizeof(*timing), GFP_KERNEL);
	706	+ if (!timing)
	707	+ return -ENOMEM;
	708	+
	709	+ ret = of_get_display_timing(np, "panel-timing", timing);
	710	+ if (ret < 0) {
	711	+ dev_err(dev, "%pOF: no panel-timing node found for \"panel-dpi\" binding\n",
	712	+ np);
	713	+ return ret;
	714	+ }
	715	+
	716	+ desc->timings = timing;
	717	+ desc->num_timings = 1;
	718	+
	719	+ of_property_read_u32(np, "width-mm", &desc->size.width);
	720	+ of_property_read_u32(np, "height-mm", &desc->size.height);
	721	+
	722	+ /* Extract bus_flags from display_timing */
	723	+ bus_flags = 0;
	724	+ vm.flags = timing->flags;
	725	+ drm_bus_flags_from_videomode(&vm, &bus_flags);
	726	+ desc->bus_flags = bus_flags;
	727	+
	728	+ /* We do not know the connector for the DT node, so guess it */
	729	+ desc->connector_type = DRM_MODE_CONNECTOR_DPI;
	730	+
	731	+ panel->desc = desc;
	732	+
	733	+ return 0;
	734	+}
	735	+
	736	+#define PANEL_SIMPLE_BOUNDS_CHECK(to_check, bounds, field) \
	737	+ (to_check->field.typ >= bounds->field.min && \
	738	+ to_check->field.typ <= bounds->field.max)
	739	+static void panel_simple_parse_panel_timing_node(struct device *dev,
	740	+ struct panel_simple *panel,
	741	+ const struct display_timing *ot)
	742	+{
	743	+ const struct panel_desc *desc = panel->desc;
	744	+ struct videomode vm;
	745	+ unsigned int i;
	746	+
	747	+ if (WARN_ON(desc->num_modes)) {
	748	+ dev_err(dev, "Reject override mode: panel has a fixed mode\n");
	749	+ return;
	750	+ }
	751	+ if (WARN_ON(!desc->num_timings)) {
	752	+ dev_err(dev, "Reject override mode: no timings specified\n");
	753	+ return;
	754	+ }
	755	+
	756	+ for (i = 0; i < panel->desc->num_timings; i++) {
	757	+ const struct display_timing *dt = &panel->desc->timings[i];
	758	+
	759	+ if (!PANEL_SIMPLE_BOUNDS_CHECK(ot, dt, hactive) \|\|
	760	+ !PANEL_SIMPLE_BOUNDS_CHECK(ot, dt, hfront_porch) \|\|
	761	+ !PANEL_SIMPLE_BOUNDS_CHECK(ot, dt, hback_porch) \|\|
	762	+ !PANEL_SIMPLE_BOUNDS_CHECK(ot, dt, hsync_len) \|\|
	763	+ !PANEL_SIMPLE_BOUNDS_CHECK(ot, dt, vactive) \|\|
	764	+ !PANEL_SIMPLE_BOUNDS_CHECK(ot, dt, vfront_porch) \|\|
	765	+ !PANEL_SIMPLE_BOUNDS_CHECK(ot, dt, vback_porch) \|\|
	766	+ !PANEL_SIMPLE_BOUNDS_CHECK(ot, dt, vsync_len))
	767	+ continue;
	768	+
	769	+ if (ot->flags != dt->flags)
	770	+ continue;
	771	+
	772	+ videomode_from_timing(ot, &vm);
	773	+ drm_display_mode_from_videomode(&vm, &panel->override_mode);
	774	+ panel->override_mode.type \|= DRM_MODE_TYPE_DRIVER \|
	775	+ DRM_MODE_TYPE_PREFERRED;
	776	+ break;
	777	+ }
	778	+
	779	+ if (WARN_ON(!panel->override_mode.type))
	780	+ dev_err(dev, "Reject override mode: No display_timing found\n");
	781	+}
	782	+
	783	+static int dcs_bl_update_status(struct backlight_device *bl)
	784	+{
	785	+ struct panel_simple *p = bl_get_data(bl);
	786	+ struct mipi_dsi_device *dsi = p->dsi;
	787	+ int ret;
	788	+
	789	+ if (!p->prepared)
	790	+ return 0;
	791	+
	792	+ dsi->mode_flags &= ~MIPI_DSI_MODE_LPM;
	793	+
	794	+ ret = mipi_dsi_dcs_set_display_brightness(dsi, bl->props.brightness);
	795	+ if (ret < 0)
	796	+ return ret;
	797	+
	798	+ dsi->mode_flags \|= MIPI_DSI_MODE_LPM;
	799	+
	800	+ return 0;
	801	+}
	802	+
	803	+static int dcs_bl_get_brightness(struct backlight_device *bl)
	804	+{
	805	+ struct panel_simple *p = bl_get_data(bl);
	806	+ struct mipi_dsi_device *dsi = p->dsi;
	807	+ u16 brightness = bl->props.brightness;
	808	+ int ret;
	809	+
	810	+ if (!p->prepared)
	811	+ return 0;
	812	+
	813	+ dsi->mode_flags &= ~MIPI_DSI_MODE_LPM;
	814	+
	815	+ ret = mipi_dsi_dcs_get_display_brightness(dsi, &brightness);
	816	+ if (ret < 0)
	817	+ return ret;
	818	+
	819	+ dsi->mode_flags \|= MIPI_DSI_MODE_LPM;
	820	+
	821	+ return brightness & 0xff;
	822	+}
	823	+
	824	+static const struct backlight_ops dcs_bl_ops = {
	825	+ .update_status = dcs_bl_update_status,
	826	+ .get_brightness = dcs_bl_get_brightness,
	827	+};
	828	+
685	829	static int panel_simple_probe(struct device dev, const struct panel_desc desc)
686	830	{
687		- struct device_node backlight, ddc;
688	831	struct panel_simple *panel;
689		- const char *cmd_type;
	832	+ struct display_timing dt;
	833	+ struct device_node *ddc;
	834	+ int connector_type;
	835	+ u32 bus_flags;
690	836	int err;
691	837
692	838	panel = devm_kzalloc(dev, sizeof(*panel), GFP_KERNEL);
..	..	@@ -697,20 +843,21 @@
697	843	panel->prepared = false;
698	844	panel->desc = desc;
699	845
	846	+ panel->no_hpd = of_property_read_bool(dev->of_node, "no-hpd");
	847	+ if (!panel->no_hpd) {
	848	+ err = panel_simple_get_hpd_gpio(dev, panel, true);
	849	+ if (err)
	850	+ return err;
	851	+ }
	852	+
700	853	panel->supply = devm_regulator_get(dev, "power");
701		- if (IS_ERR(panel->supply))
702		- return PTR_ERR(panel->supply);
703		-
704		- panel->supplies[0].supply = "vsp";
705		- panel->supplies[1].supply = "vsn";
706		-
707		- err = devm_regulator_bulk_get(dev, ARRAY_SIZE(panel->supplies),
708		- panel->supplies);
709		- if (err)
	854	+ if (IS_ERR(panel->supply)) {
	855	+ err = PTR_ERR(panel->supply);
	856	+ dev_err(dev, "failed to get power regulator: %d\n", err);
710	857	return err;
	858	+ }
711	859
712		- panel->enable_gpio = devm_gpiod_get_optional(dev, "enable",
713		- GPIOD_ASIS);
	860	+ panel->enable_gpio = devm_gpiod_get_optional(dev, "enable", GPIOD_ASIS);
714	861	if (IS_ERR(panel->enable_gpio)) {
715	862	err = PTR_ERR(panel->enable_gpio);
716	863	if (err != -EPROBE_DEFER)
..	..	@@ -726,68 +873,13 @@
726	873	return err;
727	874	}
728	875
729		- if (of_property_read_string(dev->of_node, "rockchip,cmd-type",
730		- &cmd_type))
731		- panel->cmd_type = CMD_TYPE_DEFAULT;
732		- else
733		- panel->cmd_type = get_panel_cmd_type(cmd_type);
734		-
735		- if (panel->cmd_type == CMD_TYPE_SPI) {
736		- panel->spi_sdi_gpio =
737		- devm_gpiod_get_optional(dev, "spi-sdi", 0);
738		- if (IS_ERR(panel->spi_sdi_gpio)) {
739		- err = PTR_ERR(panel->spi_sdi_gpio);
740		- dev_err(dev, "failed to request spi_sdi: %d\n", err);
741		- return err;
742		- }
743		-
744		- panel->spi_scl_gpio =
745		- devm_gpiod_get_optional(dev, "spi-scl", 0);
746		- if (IS_ERR(panel->spi_scl_gpio)) {
747		- err = PTR_ERR(panel->spi_scl_gpio);
748		- dev_err(dev, "failed to request spi_scl: %d\n", err);
749		- return err;
750		- }
751		-
752		- panel->spi_cs_gpio = devm_gpiod_get_optional(dev, "spi-cs", 0);
753		- if (IS_ERR(panel->spi_cs_gpio)) {
754		- err = PTR_ERR(panel->spi_cs_gpio);
755		- dev_err(dev, "failed to request spi_cs: %d\n", err);
756		- return err;
757		- }
758		- gpiod_direction_output(panel->spi_cs_gpio, 1);
759		- gpiod_direction_output(panel->spi_sdi_gpio, 1);
760		- gpiod_direction_output(panel->spi_scl_gpio, 1);
761		- } else if (panel->cmd_type == CMD_TYPE_MCU) {
762		- struct device_node port, endpoint;
763		- struct device_node *np;
764		-
765		- port = of_graph_get_port_by_id(dev->of_node, 0);
766		- if (port) {
767		- endpoint = of_get_next_child(port, NULL);
768		- /* get connect device node */
769		- np = of_graph_get_remote_port_parent(endpoint);
770		-
771		- port = of_graph_get_port_by_id(np, 0);
772		- if (port) {
773		- endpoint = of_get_next_child(port, NULL);
774		- /* get crtc device node */
775		- np = of_graph_get_remote_port_parent(endpoint);
776		- panel->np_crtc = np;
777		- }
778		- }
	876	+ err = of_drm_get_panel_orientation(dev->of_node, &panel->orientation);
	877	+ if (err) {
	878	+ dev_err(dev, "%pOF: failed to get orientation %d\n", dev->of_node, err);
	879	+ return err;
779	880	}
780		- panel->power_invert =
781		- of_property_read_bool(dev->of_node, "power-invert");
782	881
783		- backlight = of_parse_phandle(dev->of_node, "backlight", 0);
784		- if (backlight) {
785		- panel->backlight = of_find_backlight_by_node(backlight);
786		- of_node_put(backlight);
787		-
788		- if (!panel->backlight)
789		- return -EPROBE_DEFER;
790		- }
	882	+ panel->power_invert = of_property_read_bool(dev->of_node, "power-invert");
791	883
792	884	ddc = of_parse_phandle(dev->of_node, "ddc-i2c-bus", 0);
793	885	if (ddc) {
..	..	@@ -796,17 +888,87 @@
796	888
797	889	if (!panel->ddc) {
798	890	err = -EPROBE_DEFER;
799		- goto free_backlight;
	891	+ dev_err(dev, "failed to find ddc-i2c-bus: %d\n", err);
	892	+ return err;
800	893	}
801	894	}
802	895
803		- drm_panel_init(&panel->base);
804		- panel->base.dev = dev;
805		- panel->base.funcs = &panel_simple_funcs;
	896	+ if (desc == &panel_dpi) {
	897	+ /* Handle the generic panel-dpi binding */
	898	+ err = panel_dpi_probe(dev, panel);
	899	+ if (err)
	900	+ goto free_ddc;
	901	+ desc = panel->desc;
	902	+ } else {
	903	+ if (!of_get_display_timing(dev->of_node, "panel-timing", &dt))
	904	+ panel_simple_parse_panel_timing_node(dev, panel, &dt);
	905	+ }
806	906
807		- err = drm_panel_add(&panel->base);
808		- if (err < 0)
	907	+ connector_type = desc->connector_type;
	908	+ /* Catch common mistakes for panels. */
	909	+ switch (connector_type) {
	910	+ case 0:
	911	+ dev_dbg(dev, "Specify missing connector_type\n");
	912	+ connector_type = DRM_MODE_CONNECTOR_DPI;
	913	+ break;
	914	+ case DRM_MODE_CONNECTOR_LVDS:
	915	+ WARN_ON(desc->bus_flags &
	916	+ ~(DRM_BUS_FLAG_DE_LOW \|
	917	+ DRM_BUS_FLAG_DE_HIGH \|
	918	+ DRM_BUS_FLAG_DATA_MSB_TO_LSB \|
	919	+ DRM_BUS_FLAG_DATA_LSB_TO_MSB));
	920	+ WARN_ON(desc->bus_format != MEDIA_BUS_FMT_RGB666_1X7X3_SPWG &&
	921	+ desc->bus_format != MEDIA_BUS_FMT_RGB888_1X7X4_SPWG &&
	922	+ desc->bus_format != MEDIA_BUS_FMT_RGB888_1X7X4_JEIDA);
	923	+ WARN_ON(desc->bus_format == MEDIA_BUS_FMT_RGB666_1X7X3_SPWG &&
	924	+ desc->bpc != 6);
	925	+ WARN_ON((desc->bus_format == MEDIA_BUS_FMT_RGB888_1X7X4_SPWG \|\|
	926	+ desc->bus_format == MEDIA_BUS_FMT_RGB888_1X7X4_JEIDA) &&
	927	+ desc->bpc != 8);
	928	+ break;
	929	+ case DRM_MODE_CONNECTOR_eDP:
	930	+ if (desc->bus_format == 0)
	931	+ dev_warn(dev, "Specify missing bus_format\n");
	932	+ if (desc->bpc != 6 && desc->bpc != 8)
	933	+ dev_warn(dev, "Expected bpc in {6,8} but got: %u\n", desc->bpc);
	934	+ break;
	935	+ case DRM_MODE_CONNECTOR_DSI:
	936	+ if (desc->bpc != 6 && desc->bpc != 8)
	937	+ dev_warn(dev, "Expected bpc in {6,8} but got: %u\n", desc->bpc);
	938	+ break;
	939	+ case DRM_MODE_CONNECTOR_DPI:
	940	+ bus_flags = DRM_BUS_FLAG_DE_LOW \|
	941	+ DRM_BUS_FLAG_DE_HIGH \|
	942	+ DRM_BUS_FLAG_PIXDATA_SAMPLE_POSEDGE \|
	943	+ DRM_BUS_FLAG_PIXDATA_SAMPLE_NEGEDGE \|
	944	+ DRM_BUS_FLAG_DATA_MSB_TO_LSB \|
	945	+ DRM_BUS_FLAG_DATA_LSB_TO_MSB \|
	946	+ DRM_BUS_FLAG_SYNC_SAMPLE_POSEDGE \|
	947	+ DRM_BUS_FLAG_SYNC_SAMPLE_NEGEDGE;
	948	+ if (desc->bus_flags & ~bus_flags)
	949	+ dev_warn(dev, "Unexpected bus_flags(%d)\n", desc->bus_flags & ~bus_flags);
	950	+ if (!(desc->bus_flags & bus_flags))
	951	+ dev_warn(dev, "Specify missing bus_flags\n");
	952	+ if (desc->bus_format == 0)
	953	+ dev_warn(dev, "Specify missing bus_format\n");
	954	+ if (desc->bpc != 6 && desc->bpc != 8)
	955	+ dev_warn(dev, "Expected bpc in {6,8} but got: %u\n", desc->bpc);
	956	+ break;
	957	+ default:
	958	+ dev_warn(dev, "Specify a valid connector_type: %d\n", desc->connector_type);
	959	+ connector_type = DRM_MODE_CONNECTOR_DPI;
	960	+ break;
	961	+ }
	962	+
	963	+ drm_panel_init(&panel->base, dev, &panel_simple_funcs, connector_type);
	964	+
	965	+ err = drm_panel_of_backlight(&panel->base);
	966	+ if (err) {
	967	+ dev_err(dev, "failed to find backlight: %d\n", err);
809	968	goto free_ddc;
	969	+ }
	970	+
	971	+ drm_panel_add(&panel->base);
810	972
811	973	dev_set_drvdata(dev, panel);
812	974
..	..	@@ -815,9 +977,6 @@
815	977	free_ddc:
816	978	if (panel->ddc)
817	979	put_device(&panel->ddc->dev);
818		-free_backlight:
819		- if (panel->backlight)
820		- put_device(&panel->backlight->dev);
821	980
822	981	return err;
823	982	}
..	..	@@ -827,15 +986,11 @@
827	986	struct panel_simple *panel = dev_get_drvdata(dev);
828	987
829	988	drm_panel_remove(&panel->base);
830		-
831		- panel_simple_disable(&panel->base);
832		- panel_simple_unprepare(&panel->base);
	989	+ drm_panel_disable(&panel->base);
	990	+ drm_panel_unprepare(&panel->base);
833	991
834	992	if (panel->ddc)
835	993	put_device(&panel->ddc->dev);
836		-
837		- if (panel->backlight)
838		- put_device(&panel->backlight->dev);
839	994
840	995	return 0;
841	996	}
..	..	@@ -844,14 +999,35 @@
844	999	{
845	1000	struct panel_simple *panel = dev_get_drvdata(dev);
846	1001
847		- panel_simple_disable(&panel->base);
848		-
849		- if (panel->prepared) {
850		- gpiod_direction_output(panel->reset_gpio, 1);
851		- gpiod_direction_output(panel->enable_gpio, 0);
852		- panel_simple_regulator_disable(panel);
853		- }
	1002	+ drm_panel_disable(&panel->base);
	1003	+ drm_panel_unprepare(&panel->base);
854	1004	}
	1005	+
	1006	+static const struct drm_display_mode ampire_am_1280800n3tzqw_t00h_mode = {
	1007	+ .clock = 71100,
	1008	+ .hdisplay = 1280,
	1009	+ .hsync_start = 1280 + 40,
	1010	+ .hsync_end = 1280 + 40 + 80,
	1011	+ .htotal = 1280 + 40 + 80 + 40,
	1012	+ .vdisplay = 800,
	1013	+ .vsync_start = 800 + 3,
	1014	+ .vsync_end = 800 + 3 + 10,
	1015	+ .vtotal = 800 + 3 + 10 + 10,
	1016	+ .flags = DRM_MODE_FLAG_PHSYNC \| DRM_MODE_FLAG_PVSYNC,
	1017	+};
	1018	+
	1019	+static const struct panel_desc ampire_am_1280800n3tzqw_t00h = {
	1020	+ .modes = &ampire_am_1280800n3tzqw_t00h_mode,
	1021	+ .num_modes = 1,
	1022	+ .bpc = 8,
	1023	+ .size = {
	1024	+ .width = 217,
	1025	+ .height = 136,
	1026	+ },
	1027	+ .bus_flags = DRM_BUS_FLAG_DE_HIGH,
	1028	+ .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG,
	1029	+ .connector_type = DRM_MODE_CONNECTOR_LVDS,
	1030	+};
855	1031
856	1032	static const struct drm_display_mode ampire_am_480272h3tmqw_t01h_mode = {
857	1033	.clock = 9000,
..	..	@@ -863,7 +1039,6 @@
863	1039	.vsync_start = 272 + 2,
864	1040	.vsync_end = 272 + 2 + 10,
865	1041	.vtotal = 272 + 2 + 10 + 2,
866		- .vrefresh = 60,
867	1042	.flags = DRM_MODE_FLAG_PHSYNC \| DRM_MODE_FLAG_PVSYNC,
868	1043	};
869	1044
..	..	@@ -872,8 +1047,8 @@
872	1047	.num_modes = 1,
873	1048	.bpc = 8,
874	1049	.size = {
875		- .width = 105,
876		- .height = 67,
	1050	+ .width = 99,
	1051	+ .height = 58,
877	1052	},
878	1053	.bus_format = MEDIA_BUS_FMT_RGB888_1X24,
879	1054	};
..	..	@@ -888,7 +1063,6 @@
888	1063	.vsync_start = 480 + 2,
889	1064	.vsync_end = 480 + 2 + 45,
890	1065	.vtotal = 480 + 2 + 45 + 0,
891		- .vrefresh = 60,
892	1066	.flags = DRM_MODE_FLAG_PHSYNC \| DRM_MODE_FLAG_PVSYNC,
893	1067	};
894	1068
..	..	@@ -926,7 +1100,7 @@
926	1100	.height = 86,
927	1101	},
928	1102	.bus_format = MEDIA_BUS_FMT_RGB666_1X18,
929		- .bus_flags = DRM_BUS_FLAG_DE_HIGH \| DRM_BUS_FLAG_PIXDATA_POSEDGE,
	1103	+ .bus_flags = DRM_BUS_FLAG_DE_HIGH \| DRM_BUS_FLAG_PIXDATA_SAMPLE_NEGEDGE,
930	1104	};
931	1105
932	1106	static const struct drm_display_mode auo_b101aw03_mode = {
..	..	@@ -939,7 +1113,6 @@
939	1113	.vsync_start = 600 + 16,
940	1114	.vsync_end = 600 + 16 + 6,
941	1115	.vtotal = 600 + 16 + 6 + 16,
942		- .vrefresh = 60,
943	1116	};
944	1117
945	1118	static const struct panel_desc auo_b101aw03 = {
..	..	@@ -950,24 +1123,26 @@
950	1123	.width = 223,
951	1124	.height = 125,
952	1125	},
	1126	+ .bus_format = MEDIA_BUS_FMT_RGB666_1X7X3_SPWG,
	1127	+ .bus_flags = DRM_BUS_FLAG_DE_HIGH,
	1128	+ .connector_type = DRM_MODE_CONNECTOR_LVDS,
953	1129	};
954	1130
955		-static const struct drm_display_mode auo_b101ean01_mode = {
956		- .clock = 72500,
957		- .hdisplay = 1280,
958		- .hsync_start = 1280 + 119,
959		- .hsync_end = 1280 + 119 + 32,
960		- .htotal = 1280 + 119 + 32 + 21,
961		- .vdisplay = 800,
962		- .vsync_start = 800 + 4,
963		- .vsync_end = 800 + 4 + 20,
964		- .vtotal = 800 + 4 + 20 + 8,
965		- .vrefresh = 60,
	1131	+static const struct display_timing auo_b101ean01_timing = {
	1132	+ .pixelclock = { 65300000, 72500000, 75000000 },
	1133	+ .hactive = { 1280, 1280, 1280 },
	1134	+ .hfront_porch = { 18, 119, 119 },
	1135	+ .hback_porch = { 21, 21, 21 },
	1136	+ .hsync_len = { 32, 32, 32 },
	1137	+ .vactive = { 800, 800, 800 },
	1138	+ .vfront_porch = { 4, 4, 4 },
	1139	+ .vback_porch = { 8, 8, 8 },
	1140	+ .vsync_len = { 18, 20, 20 },
966	1141	};
967	1142
968	1143	static const struct panel_desc auo_b101ean01 = {
969		- .modes = &auo_b101ean01_mode,
970		- .num_modes = 1,
	1144	+ .timings = &auo_b101ean01_timing,
	1145	+ .num_timings = 1,
971	1146	.bpc = 6,
972	1147	.size = {
973	1148	.width = 217,
..	..	@@ -985,7 +1160,6 @@
985	1160	.vsync_start = 768 + 14,
986	1161	.vsync_end = 768 + 14 + 42,
987	1162	.vtotal = 768 + 14 + 42,
988		- .vrefresh = 60,
989	1163	.flags = DRM_MODE_FLAG_NVSYNC \| DRM_MODE_FLAG_NHSYNC,
990	1164	};
991	1165
..	..	@@ -999,6 +1173,34 @@
999	1173	},
1000	1174	};
1001	1175
	1176	+static const struct drm_display_mode auo_b116xak01_mode = {
	1177	+ .clock = 69300,
	1178	+ .hdisplay = 1366,
	1179	+ .hsync_start = 1366 + 48,
	1180	+ .hsync_end = 1366 + 48 + 32,
	1181	+ .htotal = 1366 + 48 + 32 + 10,
	1182	+ .vdisplay = 768,
	1183	+ .vsync_start = 768 + 4,
	1184	+ .vsync_end = 768 + 4 + 6,
	1185	+ .vtotal = 768 + 4 + 6 + 15,
	1186	+ .flags = DRM_MODE_FLAG_NVSYNC \| DRM_MODE_FLAG_NHSYNC,
	1187	+};
	1188	+
	1189	+static const struct panel_desc auo_b116xak01 = {
	1190	+ .modes = &auo_b116xak01_mode,
	1191	+ .num_modes = 1,
	1192	+ .bpc = 6,
	1193	+ .size = {
	1194	+ .width = 256,
	1195	+ .height = 144,
	1196	+ },
	1197	+ .delay = {
	1198	+ .hpd_absent_delay = 200,
	1199	+ },
	1200	+ .bus_format = MEDIA_BUS_FMT_RGB666_1X18,
	1201	+ .connector_type = DRM_MODE_CONNECTOR_eDP,
	1202	+};
	1203	+
1002	1204	static const struct drm_display_mode auo_b116xw03_mode = {
1003	1205	.clock = 70589,
1004	1206	.hdisplay = 1366,
..	..	@@ -1009,7 +1211,7 @@
1009	1211	.vsync_start = 768 + 10,
1010	1212	.vsync_end = 768 + 10 + 12,
1011	1213	.vtotal = 768 + 10 + 12 + 6,
1012		- .vrefresh = 60,
	1214	+ .flags = DRM_MODE_FLAG_NVSYNC \| DRM_MODE_FLAG_NHSYNC,
1013	1215	};
1014	1216
1015	1217	static const struct panel_desc auo_b116xw03 = {
..	..	@@ -1020,6 +1222,12 @@
1020	1222	.width = 256,
1021	1223	.height = 144,
1022	1224	},
	1225	+ .delay = {
	1226	+ .enable = 400,
	1227	+ },
	1228	+ .bus_flags = DRM_BUS_FLAG_SYNC_DRIVE_NEGEDGE,
	1229	+ .bus_format = MEDIA_BUS_FMT_RGB666_1X18,
	1230	+ .connector_type = DRM_MODE_CONNECTOR_eDP,
1023	1231	};
1024	1232
1025	1233	static const struct drm_display_mode auo_b133xtn01_mode = {
..	..	@@ -1032,7 +1240,6 @@
1032	1240	.vsync_start = 768 + 3,
1033	1241	.vsync_end = 768 + 3 + 6,
1034	1242	.vtotal = 768 + 3 + 6 + 13,
1035		- .vrefresh = 60,
1036	1243	};
1037	1244
1038	1245	static const struct panel_desc auo_b133xtn01 = {
..	..	@@ -1055,7 +1262,6 @@
1055	1262	.vsync_start = 1080 + 25,
1056	1263	.vsync_end = 1080 + 25 + 10,
1057	1264	.vtotal = 1080 + 25 + 10 + 10,
1058		- .vrefresh = 60,
1059	1265	};
1060	1266
1061	1267	static const struct panel_desc auo_b133htn01 = {
..	..	@@ -1101,6 +1307,30 @@
1101	1307	},
1102	1308	};
1103	1309
	1310	+static const struct drm_display_mode auo_g101evn010_mode = {
	1311	+ .clock = 68930,
	1312	+ .hdisplay = 1280,
	1313	+ .hsync_start = 1280 + 82,
	1314	+ .hsync_end = 1280 + 82 + 2,
	1315	+ .htotal = 1280 + 82 + 2 + 84,
	1316	+ .vdisplay = 800,
	1317	+ .vsync_start = 800 + 8,
	1318	+ .vsync_end = 800 + 8 + 2,
	1319	+ .vtotal = 800 + 8 + 2 + 6,
	1320	+};
	1321	+
	1322	+static const struct panel_desc auo_g101evn010 = {
	1323	+ .modes = &auo_g101evn010_mode,
	1324	+ .num_modes = 1,
	1325	+ .bpc = 6,
	1326	+ .size = {
	1327	+ .width = 216,
	1328	+ .height = 135,
	1329	+ },
	1330	+ .bus_format = MEDIA_BUS_FMT_RGB666_1X7X3_SPWG,
	1331	+ .connector_type = DRM_MODE_CONNECTOR_LVDS,
	1332	+};
	1333	+
1104	1334	static const struct drm_display_mode auo_g104sn02_mode = {
1105	1335	.clock = 40000,
1106	1336	.hdisplay = 800,
..	..	@@ -1111,7 +1341,6 @@
1111	1341	.vsync_start = 600 + 10,
1112	1342	.vsync_end = 600 + 10 + 35,
1113	1343	.vtotal = 600 + 10 + 35 + 2,
1114		- .vrefresh = 60,
1115	1344	};
1116	1345
1117	1346	static const struct panel_desc auo_g104sn02 = {
..	..	@@ -1122,6 +1351,30 @@
1122	1351	.width = 211,
1123	1352	.height = 158,
1124	1353	},
	1354	+};
	1355	+
	1356	+static const struct display_timing auo_g121ean01_timing = {
	1357	+ .pixelclock = { 60000000, 74400000, 90000000 },
	1358	+ .hactive = { 1280, 1280, 1280 },
	1359	+ .hfront_porch = { 20, 50, 100 },
	1360	+ .hback_porch = { 20, 50, 100 },
	1361	+ .hsync_len = { 30, 100, 200 },
	1362	+ .vactive = { 800, 800, 800 },
	1363	+ .vfront_porch = { 2, 10, 25 },
	1364	+ .vback_porch = { 2, 10, 25 },
	1365	+ .vsync_len = { 4, 18, 50 },
	1366	+};
	1367	+
	1368	+static const struct panel_desc auo_g121ean01 = {
	1369	+ .timings = &auo_g121ean01_timing,
	1370	+ .num_timings = 1,
	1371	+ .bpc = 8,
	1372	+ .size = {
	1373	+ .width = 261,
	1374	+ .height = 163,
	1375	+ },
	1376	+ .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG,
	1377	+ .connector_type = DRM_MODE_CONNECTOR_LVDS,
1125	1378	};
1126	1379
1127	1380	static const struct display_timing auo_g133han01_timings = {
..	..	@@ -1151,6 +1404,31 @@
1151	1404	.unprepare = 1000,
1152	1405	},
1153	1406	.bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_JEIDA,
	1407	+ .connector_type = DRM_MODE_CONNECTOR_LVDS,
	1408	+};
	1409	+
	1410	+static const struct drm_display_mode auo_g156xtn01_mode = {
	1411	+ .clock = 76000,
	1412	+ .hdisplay = 1366,
	1413	+ .hsync_start = 1366 + 33,
	1414	+ .hsync_end = 1366 + 33 + 67,
	1415	+ .htotal = 1560,
	1416	+ .vdisplay = 768,
	1417	+ .vsync_start = 768 + 4,
	1418	+ .vsync_end = 768 + 4 + 4,
	1419	+ .vtotal = 806,
	1420	+};
	1421	+
	1422	+static const struct panel_desc auo_g156xtn01 = {
	1423	+ .modes = &auo_g156xtn01_mode,
	1424	+ .num_modes = 1,
	1425	+ .bpc = 8,
	1426	+ .size = {
	1427	+ .width = 344,
	1428	+ .height = 194,
	1429	+ },
	1430	+ .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG,
	1431	+ .connector_type = DRM_MODE_CONNECTOR_LVDS,
1154	1432	};
1155	1433
1156	1434	static const struct display_timing auo_g185han01_timings = {
..	..	@@ -1180,6 +1458,37 @@
1180	1458	.unprepare = 1000,
1181	1459	},
1182	1460	.bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG,
	1461	+ .connector_type = DRM_MODE_CONNECTOR_LVDS,
	1462	+};
	1463	+
	1464	+static const struct display_timing auo_g190ean01_timings = {
	1465	+ .pixelclock = { 90000000, 108000000, 135000000 },
	1466	+ .hactive = { 1280, 1280, 1280 },
	1467	+ .hfront_porch = { 126, 184, 1266 },
	1468	+ .hback_porch = { 84, 122, 844 },
	1469	+ .hsync_len = { 70, 102, 704 },
	1470	+ .vactive = { 1024, 1024, 1024 },
	1471	+ .vfront_porch = { 4, 26, 76 },
	1472	+ .vback_porch = { 2, 8, 25 },
	1473	+ .vsync_len = { 2, 8, 25 },
	1474	+};
	1475	+
	1476	+static const struct panel_desc auo_g190ean01 = {
	1477	+ .timings = &auo_g190ean01_timings,
	1478	+ .num_timings = 1,
	1479	+ .bpc = 8,
	1480	+ .size = {
	1481	+ .width = 376,
	1482	+ .height = 301,
	1483	+ },
	1484	+ .delay = {
	1485	+ .prepare = 50,
	1486	+ .enable = 200,
	1487	+ .disable = 110,
	1488	+ .unprepare = 1000,
	1489	+ },
	1490	+ .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG,
	1491	+ .connector_type = DRM_MODE_CONNECTOR_LVDS,
1183	1492	};
1184	1493
1185	1494	static const struct display_timing auo_p320hvn03_timings = {
..	..	@@ -1208,6 +1517,7 @@
1208	1517	.unprepare = 500,
1209	1518	},
1210	1519	.bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG,
	1520	+ .connector_type = DRM_MODE_CONNECTOR_LVDS,
1211	1521	};
1212	1522
1213	1523	static const struct drm_display_mode auo_t215hvn01_mode = {
..	..	@@ -1220,7 +1530,6 @@
1220	1530	.vsync_start = 1080 + 4,
1221	1531	.vsync_end = 1080 + 4 + 5,
1222	1532	.vtotal = 1080 + 4 + 5 + 36,
1223		- .vrefresh = 60,
1224	1533	};
1225	1534
1226	1535	static const struct panel_desc auo_t215hvn01 = {
..	..	@@ -1234,7 +1543,9 @@
1234	1543	.delay = {
1235	1544	.disable = 5,
1236	1545	.unprepare = 1000,
1237		- }
	1546	+ },
	1547	+ .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG,
	1548	+ .connector_type = DRM_MODE_CONNECTOR_LVDS,
1238	1549	};
1239	1550
1240	1551	static const struct drm_display_mode avic_tm070ddh03_mode = {
..	..	@@ -1247,7 +1558,6 @@
1247	1558	.vsync_start = 600 + 17,
1248	1559	.vsync_end = 600 + 17 + 1,
1249	1560	.vtotal = 600 + 17 + 1 + 17,
1250		- .vrefresh = 60,
1251	1561	};
1252	1562
1253	1563	static const struct panel_desc avic_tm070ddh03 = {
..	..	@@ -1265,26 +1575,51 @@
1265	1575	},
1266	1576	};
1267	1577
	1578	+static const struct drm_display_mode bananapi_s070wv20_ct16_mode = {
	1579	+ .clock = 30000,
	1580	+ .hdisplay = 800,
	1581	+ .hsync_start = 800 + 40,
	1582	+ .hsync_end = 800 + 40 + 48,
	1583	+ .htotal = 800 + 40 + 48 + 40,
	1584	+ .vdisplay = 480,
	1585	+ .vsync_start = 480 + 13,
	1586	+ .vsync_end = 480 + 13 + 3,
	1587	+ .vtotal = 480 + 13 + 3 + 29,
	1588	+};
	1589	+
	1590	+static const struct panel_desc bananapi_s070wv20_ct16 = {
	1591	+ .modes = &bananapi_s070wv20_ct16_mode,
	1592	+ .num_modes = 1,
	1593	+ .bpc = 6,
	1594	+ .size = {
	1595	+ .width = 154,
	1596	+ .height = 86,
	1597	+ },
	1598	+};
	1599	+
1268	1600	static const struct drm_display_mode boe_hv070wsa_mode = {
1269		- .clock = 40800,
	1601	+ .clock = 42105,
1270	1602	.hdisplay = 1024,
1271		- .hsync_start = 1024 + 90,
1272		- .hsync_end = 1024 + 90 + 90,
1273		- .htotal = 1024 + 90 + 90 + 90,
	1603	+ .hsync_start = 1024 + 30,
	1604	+ .hsync_end = 1024 + 30 + 30,
	1605	+ .htotal = 1024 + 30 + 30 + 30,
1274	1606	.vdisplay = 600,
1275		- .vsync_start = 600 + 3,
1276		- .vsync_end = 600 + 3 + 4,
1277		- .vtotal = 600 + 3 + 4 + 3,
1278		- .vrefresh = 60,
	1607	+ .vsync_start = 600 + 10,
	1608	+ .vsync_end = 600 + 10 + 10,
	1609	+ .vtotal = 600 + 10 + 10 + 10,
1279	1610	};
1280	1611
1281	1612	static const struct panel_desc boe_hv070wsa = {
1282	1613	.modes = &boe_hv070wsa_mode,
1283	1614	.num_modes = 1,
	1615	+ .bpc = 8,
1284	1616	.size = {
1285	1617	.width = 154,
1286	1618	.height = 90,
1287	1619	},
	1620	+ .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG,
	1621	+ .bus_flags = DRM_BUS_FLAG_DE_HIGH,
	1622	+ .connector_type = DRM_MODE_CONNECTOR_LVDS,
1288	1623	};
1289	1624
1290	1625	static const struct drm_display_mode boe_nv101wxmn51_modes[] = {
..	..	@@ -1298,7 +1633,6 @@
1298	1633	.vsync_start = 800 + 3,
1299	1634	.vsync_end = 800 + 3 + 5,
1300	1635	.vtotal = 800 + 3 + 5 + 24,
1301		- .vrefresh = 60,
1302	1636	},
1303	1637	{
1304	1638	.clock = 57500,
..	..	@@ -1310,7 +1644,6 @@
1310	1644	.vsync_start = 800 + 3,
1311	1645	.vsync_end = 800 + 3 + 5,
1312	1646	.vtotal = 800 + 3 + 5 + 24,
1313		- .vrefresh = 48,
1314	1647	},
1315	1648	};
1316	1649
..	..	@@ -1329,6 +1662,214 @@
1329	1662	},
1330	1663	};
1331	1664
	1665	+/* Also used for boe_nv133fhm_n62 */
	1666	+static const struct drm_display_mode boe_nv133fhm_n61_modes = {
	1667	+ .clock = 147840,
	1668	+ .hdisplay = 1920,
	1669	+ .hsync_start = 1920 + 48,
	1670	+ .hsync_end = 1920 + 48 + 32,
	1671	+ .htotal = 1920 + 48 + 32 + 200,
	1672	+ .vdisplay = 1080,
	1673	+ .vsync_start = 1080 + 3,
	1674	+ .vsync_end = 1080 + 3 + 6,
	1675	+ .vtotal = 1080 + 3 + 6 + 31,
	1676	+ .flags = DRM_MODE_FLAG_PHSYNC \| DRM_MODE_FLAG_NVSYNC,
	1677	+};
	1678	+
	1679	+/* Also used for boe_nv133fhm_n62 */
	1680	+static const struct panel_desc boe_nv133fhm_n61 = {
	1681	+ .modes = &boe_nv133fhm_n61_modes,
	1682	+ .num_modes = 1,
	1683	+ .bpc = 6,
	1684	+ .size = {
	1685	+ .width = 294,
	1686	+ .height = 165,
	1687	+ },
	1688	+ .delay = {
	1689	+ /*
	1690	+ * When power is first given to the panel there's a short
	1691	+ * spike on the HPD line. It was explained that this spike
	1692	+ * was until the TCON data download was complete. On
	1693	+ * one system this was measured at 8 ms. We'll put 15 ms
	1694	+ * in the prepare delay just to be safe and take it away
	1695	+ * from the hpd_absent_delay (which would otherwise be 200 ms)
	1696	+ * to handle this. That means:
	1697	+ * - If HPD isn't hooked up you still have 200 ms delay.
	1698	+ * - If HPD is hooked up we won't try to look at it for the
	1699	+ * first 15 ms.
	1700	+ */
	1701	+ .prepare = 15,
	1702	+ .hpd_absent_delay = 185,
	1703	+
	1704	+ .unprepare = 500,
	1705	+ },
	1706	+ .bus_format = MEDIA_BUS_FMT_RGB888_1X24,
	1707	+ .bus_flags = DRM_BUS_FLAG_DATA_MSB_TO_LSB,
	1708	+ .connector_type = DRM_MODE_CONNECTOR_eDP,
	1709	+};
	1710	+
	1711	+static const struct drm_display_mode boe_nv140fhmn49_modes[] = {
	1712	+ {
	1713	+ .clock = 148500,
	1714	+ .hdisplay = 1920,
	1715	+ .hsync_start = 1920 + 48,
	1716	+ .hsync_end = 1920 + 48 + 32,
	1717	+ .htotal = 2200,
	1718	+ .vdisplay = 1080,
	1719	+ .vsync_start = 1080 + 3,
	1720	+ .vsync_end = 1080 + 3 + 5,
	1721	+ .vtotal = 1125,
	1722	+ },
	1723	+};
	1724	+
	1725	+static const struct panel_desc boe_nv140fhmn49 = {
	1726	+ .modes = boe_nv140fhmn49_modes,
	1727	+ .num_modes = ARRAY_SIZE(boe_nv140fhmn49_modes),
	1728	+ .bpc = 6,
	1729	+ .size = {
	1730	+ .width = 309,
	1731	+ .height = 174,
	1732	+ },
	1733	+ .delay = {
	1734	+ .prepare = 210,
	1735	+ .enable = 50,
	1736	+ .unprepare = 160,
	1737	+ },
	1738	+ .bus_format = MEDIA_BUS_FMT_RGB666_1X18,
	1739	+ .connector_type = DRM_MODE_CONNECTOR_eDP,
	1740	+};
	1741	+
	1742	+static const struct drm_display_mode cdtech_s043wq26h_ct7_mode = {
	1743	+ .clock = 9000,
	1744	+ .hdisplay = 480,
	1745	+ .hsync_start = 480 + 5,
	1746	+ .hsync_end = 480 + 5 + 5,
	1747	+ .htotal = 480 + 5 + 5 + 40,
	1748	+ .vdisplay = 272,
	1749	+ .vsync_start = 272 + 8,
	1750	+ .vsync_end = 272 + 8 + 8,
	1751	+ .vtotal = 272 + 8 + 8 + 8,
	1752	+ .flags = DRM_MODE_FLAG_NHSYNC \| DRM_MODE_FLAG_NVSYNC,
	1753	+};
	1754	+
	1755	+static const struct panel_desc cdtech_s043wq26h_ct7 = {
	1756	+ .modes = &cdtech_s043wq26h_ct7_mode,
	1757	+ .num_modes = 1,
	1758	+ .bpc = 8,
	1759	+ .size = {
	1760	+ .width = 95,
	1761	+ .height = 54,
	1762	+ },
	1763	+ .bus_flags = DRM_BUS_FLAG_PIXDATA_DRIVE_POSEDGE,
	1764	+};
	1765	+
	1766	+/* S070PWS19HP-FC21 2017/04/22 */
	1767	+static const struct drm_display_mode cdtech_s070pws19hp_fc21_mode = {
	1768	+ .clock = 51200,
	1769	+ .hdisplay = 1024,
	1770	+ .hsync_start = 1024 + 160,
	1771	+ .hsync_end = 1024 + 160 + 20,
	1772	+ .htotal = 1024 + 160 + 20 + 140,
	1773	+ .vdisplay = 600,
	1774	+ .vsync_start = 600 + 12,
	1775	+ .vsync_end = 600 + 12 + 3,
	1776	+ .vtotal = 600 + 12 + 3 + 20,
	1777	+ .flags = DRM_MODE_FLAG_NHSYNC \| DRM_MODE_FLAG_NVSYNC,
	1778	+};
	1779	+
	1780	+static const struct panel_desc cdtech_s070pws19hp_fc21 = {
	1781	+ .modes = &cdtech_s070pws19hp_fc21_mode,
	1782	+ .num_modes = 1,
	1783	+ .bpc = 6,
	1784	+ .size = {
	1785	+ .width = 154,
	1786	+ .height = 86,
	1787	+ },
	1788	+ .bus_format = MEDIA_BUS_FMT_RGB666_1X18,
	1789	+ .bus_flags = DRM_BUS_FLAG_DE_HIGH \| DRM_BUS_FLAG_PIXDATA_SAMPLE_NEGEDGE,
	1790	+ .connector_type = DRM_MODE_CONNECTOR_DPI,
	1791	+};
	1792	+
	1793	+/* S070SWV29HG-DC44 2017/09/21 */
	1794	+static const struct drm_display_mode cdtech_s070swv29hg_dc44_mode = {
	1795	+ .clock = 33300,
	1796	+ .hdisplay = 800,
	1797	+ .hsync_start = 800 + 210,
	1798	+ .hsync_end = 800 + 210 + 2,
	1799	+ .htotal = 800 + 210 + 2 + 44,
	1800	+ .vdisplay = 480,
	1801	+ .vsync_start = 480 + 22,
	1802	+ .vsync_end = 480 + 22 + 2,
	1803	+ .vtotal = 480 + 22 + 2 + 21,
	1804	+ .flags = DRM_MODE_FLAG_NHSYNC \| DRM_MODE_FLAG_NVSYNC,
	1805	+};
	1806	+
	1807	+static const struct panel_desc cdtech_s070swv29hg_dc44 = {
	1808	+ .modes = &cdtech_s070swv29hg_dc44_mode,
	1809	+ .num_modes = 1,
	1810	+ .bpc = 6,
	1811	+ .size = {
	1812	+ .width = 154,
	1813	+ .height = 86,
	1814	+ },
	1815	+ .bus_format = MEDIA_BUS_FMT_RGB666_1X18,
	1816	+ .bus_flags = DRM_BUS_FLAG_DE_HIGH \| DRM_BUS_FLAG_PIXDATA_SAMPLE_NEGEDGE,
	1817	+ .connector_type = DRM_MODE_CONNECTOR_DPI,
	1818	+};
	1819	+
	1820	+static const struct drm_display_mode cdtech_s070wv95_ct16_mode = {
	1821	+ .clock = 35000,
	1822	+ .hdisplay = 800,
	1823	+ .hsync_start = 800 + 40,
	1824	+ .hsync_end = 800 + 40 + 40,
	1825	+ .htotal = 800 + 40 + 40 + 48,
	1826	+ .vdisplay = 480,
	1827	+ .vsync_start = 480 + 29,
	1828	+ .vsync_end = 480 + 29 + 13,
	1829	+ .vtotal = 480 + 29 + 13 + 3,
	1830	+ .flags = DRM_MODE_FLAG_NHSYNC \| DRM_MODE_FLAG_NVSYNC,
	1831	+};
	1832	+
	1833	+static const struct panel_desc cdtech_s070wv95_ct16 = {
	1834	+ .modes = &cdtech_s070wv95_ct16_mode,
	1835	+ .num_modes = 1,
	1836	+ .bpc = 8,
	1837	+ .size = {
	1838	+ .width = 154,
	1839	+ .height = 85,
	1840	+ },
	1841	+};
	1842	+
	1843	+static const struct display_timing chefree_ch101olhlwh_002_timing = {
	1844	+ .pixelclock = { 68900000, 71100000, 73400000 },
	1845	+ .hactive = { 1280, 1280, 1280 },
	1846	+ .hfront_porch = { 65, 80, 95 },
	1847	+ .hback_porch = { 64, 79, 94 },
	1848	+ .hsync_len = { 1, 1, 1 },
	1849	+ .vactive = { 800, 800, 800 },
	1850	+ .vfront_porch = { 7, 11, 14 },
	1851	+ .vback_porch = { 7, 11, 14 },
	1852	+ .vsync_len = { 1, 1, 1 },
	1853	+ .flags = DISPLAY_FLAGS_DE_HIGH,
	1854	+};
	1855	+
	1856	+static const struct panel_desc chefree_ch101olhlwh_002 = {
	1857	+ .timings = &chefree_ch101olhlwh_002_timing,
	1858	+ .num_timings = 1,
	1859	+ .bpc = 8,
	1860	+ .size = {
	1861	+ .width = 217,
	1862	+ .height = 135,
	1863	+ },
	1864	+ .delay = {
	1865	+ .enable = 200,
	1866	+ .disable = 200,
	1867	+ },
	1868	+ .bus_flags = DRM_BUS_FLAG_DE_HIGH,
	1869	+ .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG,
	1870	+ .connector_type = DRM_MODE_CONNECTOR_LVDS,
	1871	+};
	1872	+
1332	1873	static const struct drm_display_mode chunghwa_claa070wp03xg_mode = {
1333	1874	.clock = 66770,
1334	1875	.hdisplay = 800,
..	..	@@ -1339,7 +1880,6 @@
1339	1880	.vsync_start = 1280 + 1,
1340	1881	.vsync_end = 1280 + 1 + 7,
1341	1882	.vtotal = 1280 + 1 + 7 + 15,
1342		- .vrefresh = 60,
1343	1883	.flags = DRM_MODE_FLAG_NVSYNC \| DRM_MODE_FLAG_NHSYNC,
1344	1884	};
1345	1885
..	..	@@ -1351,6 +1891,9 @@
1351	1891	.width = 94,
1352	1892	.height = 150,
1353	1893	},
	1894	+ .bus_format = MEDIA_BUS_FMT_RGB666_1X7X3_SPWG,
	1895	+ .bus_flags = DRM_BUS_FLAG_DE_HIGH,
	1896	+ .connector_type = DRM_MODE_CONNECTOR_LVDS,
1354	1897	};
1355	1898
1356	1899	static const struct drm_display_mode chunghwa_claa101wa01a_mode = {
..	..	@@ -1363,7 +1906,6 @@
1363	1906	.vsync_start = 768 + 4,
1364	1907	.vsync_end = 768 + 4 + 4,
1365	1908	.vtotal = 768 + 4 + 4 + 4,
1366		- .vrefresh = 60,
1367	1909	};
1368	1910
1369	1911	static const struct panel_desc chunghwa_claa101wa01a = {
..	..	@@ -1374,6 +1916,9 @@
1374	1916	.width = 220,
1375	1917	.height = 120,
1376	1918	},
	1919	+ .bus_format = MEDIA_BUS_FMT_RGB666_1X7X3_SPWG,
	1920	+ .bus_flags = DRM_BUS_FLAG_DE_HIGH,
	1921	+ .connector_type = DRM_MODE_CONNECTOR_LVDS,
1377	1922	};
1378	1923
1379	1924	static const struct drm_display_mode chunghwa_claa101wb01_mode = {
..	..	@@ -1386,7 +1931,6 @@
1386	1931	.vsync_start = 768 + 16,
1387	1932	.vsync_end = 768 + 16 + 8,
1388	1933	.vtotal = 768 + 16 + 8 + 16,
1389		- .vrefresh = 60,
1390	1934	};
1391	1935
1392	1936	static const struct panel_desc chunghwa_claa101wb01 = {
..	..	@@ -1397,6 +1941,9 @@
1397	1941	.width = 223,
1398	1942	.height = 125,
1399	1943	},
	1944	+ .bus_format = MEDIA_BUS_FMT_RGB666_1X7X3_SPWG,
	1945	+ .bus_flags = DRM_BUS_FLAG_DE_HIGH,
	1946	+ .connector_type = DRM_MODE_CONNECTOR_LVDS,
1400	1947	};
1401	1948
1402	1949	static const struct drm_display_mode dataimage_scf0700c48ggu18_mode = {
..	..	@@ -1409,7 +1956,6 @@
1409	1956	.vsync_start = 480 + 10,
1410	1957	.vsync_end = 480 + 10 + 2,
1411	1958	.vtotal = 480 + 10 + 2 + 33,
1412		- .vrefresh = 60,
1413	1959	.flags = DRM_MODE_FLAG_NVSYNC \| DRM_MODE_FLAG_NHSYNC,
1414	1960	};
1415	1961
..	..	@@ -1422,7 +1968,7 @@
1422	1968	.height = 91,
1423	1969	},
1424	1970	.bus_format = MEDIA_BUS_FMT_RGB888_1X24,
1425		- .bus_flags = DRM_BUS_FLAG_DE_HIGH \| DRM_BUS_FLAG_PIXDATA_POSEDGE,
	1971	+ .bus_flags = DRM_BUS_FLAG_DE_HIGH \| DRM_BUS_FLAG_PIXDATA_DRIVE_POSEDGE,
1426	1972	};
1427	1973
1428	1974	static const struct display_timing dlc_dlc0700yzg_1_timing = {
..	..	@@ -1452,6 +1998,116 @@
1452	1998	.disable = 200,
1453	1999	},
1454	2000	.bus_format = MEDIA_BUS_FMT_RGB666_1X7X3_SPWG,
	2001	+ .connector_type = DRM_MODE_CONNECTOR_LVDS,
	2002	+};
	2003	+
	2004	+static const struct display_timing dlc_dlc1010gig_timing = {
	2005	+ .pixelclock = { 68900000, 71100000, 73400000 },
	2006	+ .hactive = { 1280, 1280, 1280 },
	2007	+ .hfront_porch = { 43, 53, 63 },
	2008	+ .hback_porch = { 43, 53, 63 },
	2009	+ .hsync_len = { 44, 54, 64 },
	2010	+ .vactive = { 800, 800, 800 },
	2011	+ .vfront_porch = { 5, 8, 11 },
	2012	+ .vback_porch = { 5, 8, 11 },
	2013	+ .vsync_len = { 5, 7, 11 },
	2014	+ .flags = DISPLAY_FLAGS_DE_HIGH,
	2015	+};
	2016	+
	2017	+static const struct panel_desc dlc_dlc1010gig = {
	2018	+ .timings = &dlc_dlc1010gig_timing,
	2019	+ .num_timings = 1,
	2020	+ .bpc = 8,
	2021	+ .size = {
	2022	+ .width = 216,
	2023	+ .height = 135,
	2024	+ },
	2025	+ .delay = {
	2026	+ .prepare = 60,
	2027	+ .enable = 150,
	2028	+ .disable = 100,
	2029	+ .unprepare = 60,
	2030	+ },
	2031	+ .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG,
	2032	+ .connector_type = DRM_MODE_CONNECTOR_LVDS,
	2033	+};
	2034	+
	2035	+static const struct drm_display_mode edt_et035012dm6_mode = {
	2036	+ .clock = 6500,
	2037	+ .hdisplay = 320,
	2038	+ .hsync_start = 320 + 20,
	2039	+ .hsync_end = 320 + 20 + 30,
	2040	+ .htotal = 320 + 20 + 68,
	2041	+ .vdisplay = 240,
	2042	+ .vsync_start = 240 + 4,
	2043	+ .vsync_end = 240 + 4 + 4,
	2044	+ .vtotal = 240 + 4 + 4 + 14,
	2045	+ .flags = DRM_MODE_FLAG_NVSYNC \| DRM_MODE_FLAG_NHSYNC,
	2046	+};
	2047	+
	2048	+static const struct panel_desc edt_et035012dm6 = {
	2049	+ .modes = &edt_et035012dm6_mode,
	2050	+ .num_modes = 1,
	2051	+ .bpc = 8,
	2052	+ .size = {
	2053	+ .width = 70,
	2054	+ .height = 52,
	2055	+ },
	2056	+ .bus_format = MEDIA_BUS_FMT_RGB888_1X24,
	2057	+ .bus_flags = DRM_BUS_FLAG_DE_LOW \| DRM_BUS_FLAG_PIXDATA_SAMPLE_POSEDGE,
	2058	+};
	2059	+
	2060	+static const struct drm_display_mode edt_etm043080dh6gp_mode = {
	2061	+ .clock = 10870,
	2062	+ .hdisplay = 480,
	2063	+ .hsync_start = 480 + 8,
	2064	+ .hsync_end = 480 + 8 + 4,
	2065	+ .htotal = 480 + 8 + 4 + 41,
	2066	+
	2067	+ /*
	2068	+ * IWG22M: Y resolution changed for "dc_linuxfb" module crashing while
	2069	+ * fb_align
	2070	+ */
	2071	+
	2072	+ .vdisplay = 288,
	2073	+ .vsync_start = 288 + 2,
	2074	+ .vsync_end = 288 + 2 + 4,
	2075	+ .vtotal = 288 + 2 + 4 + 10,
	2076	+};
	2077	+
	2078	+static const struct panel_desc edt_etm043080dh6gp = {
	2079	+ .modes = &edt_etm043080dh6gp_mode,
	2080	+ .num_modes = 1,
	2081	+ .bpc = 8,
	2082	+ .size = {
	2083	+ .width = 100,
	2084	+ .height = 65,
	2085	+ },
	2086	+ .bus_format = MEDIA_BUS_FMT_RGB666_1X18,
	2087	+ .connector_type = DRM_MODE_CONNECTOR_DPI,
	2088	+};
	2089	+
	2090	+static const struct drm_display_mode edt_etm0430g0dh6_mode = {
	2091	+ .clock = 9000,
	2092	+ .hdisplay = 480,
	2093	+ .hsync_start = 480 + 2,
	2094	+ .hsync_end = 480 + 2 + 41,
	2095	+ .htotal = 480 + 2 + 41 + 2,
	2096	+ .vdisplay = 272,
	2097	+ .vsync_start = 272 + 2,
	2098	+ .vsync_end = 272 + 2 + 10,
	2099	+ .vtotal = 272 + 2 + 10 + 2,
	2100	+ .flags = DRM_MODE_FLAG_NHSYNC \| DRM_MODE_FLAG_NVSYNC,
	2101	+};
	2102	+
	2103	+static const struct panel_desc edt_etm0430g0dh6 = {
	2104	+ .modes = &edt_etm0430g0dh6_mode,
	2105	+ .num_modes = 1,
	2106	+ .bpc = 6,
	2107	+ .size = {
	2108	+ .width = 95,
	2109	+ .height = 54,
	2110	+ },
1455	2111	};
1456	2112
1457	2113	static const struct drm_display_mode edt_et057090dhu_mode = {
..	..	@@ -1464,7 +2120,6 @@
1464	2120	.vsync_start = 480 + 10,
1465	2121	.vsync_end = 480 + 10 + 3,
1466	2122	.vtotal = 480 + 10 + 3 + 32,
1467		- .vrefresh = 60,
1468	2123	.flags = DRM_MODE_FLAG_NVSYNC \| DRM_MODE_FLAG_NHSYNC,
1469	2124	};
1470	2125
..	..	@@ -1477,7 +2132,8 @@
1477	2132	.height = 86,
1478	2133	},
1479	2134	.bus_format = MEDIA_BUS_FMT_RGB666_1X18,
1480		- .bus_flags = DRM_BUS_FLAG_DE_HIGH \| DRM_BUS_FLAG_PIXDATA_NEGEDGE,
	2135	+ .bus_flags = DRM_BUS_FLAG_DE_HIGH \| DRM_BUS_FLAG_PIXDATA_DRIVE_NEGEDGE,
	2136	+ .connector_type = DRM_MODE_CONNECTOR_DPI,
1481	2137	};
1482	2138
1483	2139	static const struct drm_display_mode edt_etm0700g0dh6_mode = {
..	..	@@ -1490,7 +2146,6 @@
1490	2146	.vsync_start = 480 + 10,
1491	2147	.vsync_end = 480 + 10 + 2,
1492	2148	.vtotal = 480 + 10 + 2 + 33,
1493		- .vrefresh = 60,
1494	2149	.flags = DRM_MODE_FLAG_NHSYNC \| DRM_MODE_FLAG_NVSYNC,
1495	2150	};
1496	2151
..	..	@@ -1503,7 +2158,7 @@
1503	2158	.height = 91,
1504	2159	},
1505	2160	.bus_format = MEDIA_BUS_FMT_RGB666_1X18,
1506		- .bus_flags = DRM_BUS_FLAG_DE_HIGH \| DRM_BUS_FLAG_PIXDATA_NEGEDGE,
	2161	+ .bus_flags = DRM_BUS_FLAG_DE_HIGH \| DRM_BUS_FLAG_PIXDATA_DRIVE_NEGEDGE,
1507	2162	};
1508	2163
1509	2164	static const struct panel_desc edt_etm0700g0bdh6 = {
..	..	@@ -1515,7 +2170,34 @@
1515	2170	.height = 91,
1516	2171	},
1517	2172	.bus_format = MEDIA_BUS_FMT_RGB666_1X18,
1518		- .bus_flags = DRM_BUS_FLAG_DE_HIGH \| DRM_BUS_FLAG_PIXDATA_POSEDGE,
	2173	+ .bus_flags = DRM_BUS_FLAG_DE_HIGH \| DRM_BUS_FLAG_PIXDATA_DRIVE_POSEDGE,
	2174	+};
	2175	+
	2176	+static const struct display_timing evervision_vgg804821_timing = {
	2177	+ .pixelclock = { 27600000, 33300000, 50000000 },
	2178	+ .hactive = { 800, 800, 800 },
	2179	+ .hfront_porch = { 40, 66, 70 },
	2180	+ .hback_porch = { 40, 67, 70 },
	2181	+ .hsync_len = { 40, 67, 70 },
	2182	+ .vactive = { 480, 480, 480 },
	2183	+ .vfront_porch = { 6, 10, 10 },
	2184	+ .vback_porch = { 7, 11, 11 },
	2185	+ .vsync_len = { 7, 11, 11 },
	2186	+ .flags = DISPLAY_FLAGS_HSYNC_HIGH \| DISPLAY_FLAGS_VSYNC_HIGH \|
	2187	+ DISPLAY_FLAGS_DE_HIGH \| DISPLAY_FLAGS_PIXDATA_NEGEDGE \|
	2188	+ DISPLAY_FLAGS_SYNC_NEGEDGE,
	2189	+};
	2190	+
	2191	+static const struct panel_desc evervision_vgg804821 = {
	2192	+ .timings = &evervision_vgg804821_timing,
	2193	+ .num_timings = 1,
	2194	+ .bpc = 8,
	2195	+ .size = {
	2196	+ .width = 108,
	2197	+ .height = 64,
	2198	+ },
	2199	+ .bus_format = MEDIA_BUS_FMT_RGB888_1X24,
	2200	+ .bus_flags = DRM_BUS_FLAG_DE_HIGH \| DRM_BUS_FLAG_PIXDATA_SAMPLE_POSEDGE,
1519	2201	};
1520	2202
1521	2203	static const struct drm_display_mode foxlink_fl500wvr00_a0t_mode = {
..	..	@@ -1528,7 +2210,6 @@
1528	2210	.vsync_start = 480 + 37,
1529	2211	.vsync_end = 480 + 37 + 2,
1530	2212	.vtotal = 480 + 37 + 2 + 8,
1531		- .vrefresh = 60,
1532	2213	};
1533	2214
1534	2215	static const struct panel_desc foxlink_fl500wvr00_a0t = {
..	..	@@ -1542,6 +2223,68 @@
1542	2223	.bus_format = MEDIA_BUS_FMT_RGB888_1X24,
1543	2224	};
1544	2225
	2226	+static const struct drm_display_mode frida_frd350h54004_modes[] = {
	2227	+ { /* 60 Hz */
	2228	+ .clock = 6000,
	2229	+ .hdisplay = 320,
	2230	+ .hsync_start = 320 + 44,
	2231	+ .hsync_end = 320 + 44 + 16,
	2232	+ .htotal = 320 + 44 + 16 + 20,
	2233	+ .vdisplay = 240,
	2234	+ .vsync_start = 240 + 2,
	2235	+ .vsync_end = 240 + 2 + 6,
	2236	+ .vtotal = 240 + 2 + 6 + 2,
	2237	+ .flags = DRM_MODE_FLAG_NHSYNC \| DRM_MODE_FLAG_NVSYNC,
	2238	+ },
	2239	+ { /* 50 Hz */
	2240	+ .clock = 5400,
	2241	+ .hdisplay = 320,
	2242	+ .hsync_start = 320 + 56,
	2243	+ .hsync_end = 320 + 56 + 16,
	2244	+ .htotal = 320 + 56 + 16 + 40,
	2245	+ .vdisplay = 240,
	2246	+ .vsync_start = 240 + 2,
	2247	+ .vsync_end = 240 + 2 + 6,
	2248	+ .vtotal = 240 + 2 + 6 + 2,
	2249	+ .flags = DRM_MODE_FLAG_NHSYNC \| DRM_MODE_FLAG_NVSYNC,
	2250	+ },
	2251	+};
	2252	+
	2253	+static const struct panel_desc frida_frd350h54004 = {
	2254	+ .modes = frida_frd350h54004_modes,
	2255	+ .num_modes = ARRAY_SIZE(frida_frd350h54004_modes),
	2256	+ .bpc = 8,
	2257	+ .size = {
	2258	+ .width = 77,
	2259	+ .height = 64,
	2260	+ },
	2261	+ .bus_format = MEDIA_BUS_FMT_RGB888_1X24,
	2262	+ .bus_flags = DRM_BUS_FLAG_DE_HIGH \| DRM_BUS_FLAG_PIXDATA_SAMPLE_NEGEDGE,
	2263	+ .connector_type = DRM_MODE_CONNECTOR_DPI,
	2264	+};
	2265	+
	2266	+static const struct drm_display_mode friendlyarm_hd702e_mode = {
	2267	+ .clock = 67185,
	2268	+ .hdisplay = 800,
	2269	+ .hsync_start = 800 + 20,
	2270	+ .hsync_end = 800 + 20 + 24,
	2271	+ .htotal = 800 + 20 + 24 + 20,
	2272	+ .vdisplay = 1280,
	2273	+ .vsync_start = 1280 + 4,
	2274	+ .vsync_end = 1280 + 4 + 8,
	2275	+ .vtotal = 1280 + 4 + 8 + 4,
	2276	+ .flags = DRM_MODE_FLAG_NVSYNC \| DRM_MODE_FLAG_NHSYNC,
	2277	+};
	2278	+
	2279	+static const struct panel_desc friendlyarm_hd702e = {
	2280	+ .modes = &friendlyarm_hd702e_mode,
	2281	+ .num_modes = 1,
	2282	+ .size = {
	2283	+ .width = 94,
	2284	+ .height = 151,
	2285	+ },
	2286	+};
	2287	+
1545	2288	static const struct drm_display_mode giantplus_gpg482739qs5_mode = {
1546	2289	.clock = 9000,
1547	2290	.hdisplay = 480,
..	..	@@ -1552,7 +2295,6 @@
1552	2295	.vsync_start = 272 + 8,
1553	2296	.vsync_end = 272 + 8 + 1,
1554	2297	.vtotal = 272 + 8 + 1 + 8,
1555		- .vrefresh = 60,
1556	2298	};
1557	2299
1558	2300	static const struct panel_desc giantplus_gpg482739qs5 = {
..	..	@@ -1564,6 +2306,31 @@
1564	2306	.height = 54,
1565	2307	},
1566	2308	.bus_format = MEDIA_BUS_FMT_RGB888_1X24,
	2309	+};
	2310	+
	2311	+static const struct display_timing giantplus_gpm940b0_timing = {
	2312	+ .pixelclock = { 13500000, 27000000, 27500000 },
	2313	+ .hactive = { 320, 320, 320 },
	2314	+ .hfront_porch = { 14, 686, 718 },
	2315	+ .hback_porch = { 50, 70, 255 },
	2316	+ .hsync_len = { 1, 1, 1 },
	2317	+ .vactive = { 240, 240, 240 },
	2318	+ .vfront_porch = { 1, 1, 179 },
	2319	+ .vback_porch = { 1, 21, 31 },
	2320	+ .vsync_len = { 1, 1, 6 },
	2321	+ .flags = DISPLAY_FLAGS_HSYNC_LOW \| DISPLAY_FLAGS_VSYNC_LOW,
	2322	+};
	2323	+
	2324	+static const struct panel_desc giantplus_gpm940b0 = {
	2325	+ .timings = &giantplus_gpm940b0_timing,
	2326	+ .num_timings = 1,
	2327	+ .bpc = 8,
	2328	+ .size = {
	2329	+ .width = 60,
	2330	+ .height = 45,
	2331	+ },
	2332	+ .bus_format = MEDIA_BUS_FMT_RGB888_3X8,
	2333	+ .bus_flags = DRM_BUS_FLAG_DE_HIGH \| DRM_BUS_FLAG_PIXDATA_SAMPLE_POSEDGE,
1567	2334	};
1568	2335
1569	2336	static const struct display_timing hannstar_hsd070pww1_timing = {
..	..	@@ -1593,6 +2360,7 @@
1593	2360	.height = 94,
1594	2361	},
1595	2362	.bus_format = MEDIA_BUS_FMT_RGB666_1X7X3_SPWG,
	2363	+ .connector_type = DRM_MODE_CONNECTOR_LVDS,
1596	2364	};
1597	2365
1598	2366	static const struct display_timing hannstar_hsd100pxn1_timing = {
..	..	@@ -1617,6 +2385,7 @@
1617	2385	.height = 152,
1618	2386	},
1619	2387	.bus_format = MEDIA_BUS_FMT_RGB666_1X7X3_SPWG,
	2388	+ .connector_type = DRM_MODE_CONNECTOR_LVDS,
1620	2389	};
1621	2390
1622	2391	static const struct drm_display_mode hitachi_tx23d38vm0caa_mode = {
..	..	@@ -1629,7 +2398,6 @@
1629	2398	.vsync_start = 480 + 16,
1630	2399	.vsync_end = 480 + 16 + 13,
1631	2400	.vtotal = 480 + 16 + 13 + 16,
1632		- .vrefresh = 60,
1633	2401	};
1634	2402
1635	2403	static const struct panel_desc hitachi_tx23d38vm0caa = {
..	..	@@ -1656,7 +2424,6 @@
1656	2424	.vsync_start = 272 + 2,
1657	2425	.vsync_end = 272 + 2 + 10,
1658	2426	.vtotal = 272 + 2 + 10 + 2,
1659		- .vrefresh = 60,
1660	2427	.flags = DRM_MODE_FLAG_NHSYNC \| DRM_MODE_FLAG_NVSYNC,
1661	2428	};
1662	2429
..	..	@@ -1669,7 +2436,8 @@
1669	2436	.height = 54,
1670	2437	},
1671	2438	.bus_format = MEDIA_BUS_FMT_RGB888_1X24,
1672		- .bus_flags = DRM_BUS_FLAG_DE_HIGH \| DRM_BUS_FLAG_PIXDATA_POSEDGE,
	2439	+ .connector_type = DRM_MODE_CONNECTOR_DPI,
	2440	+ .bus_flags = DRM_BUS_FLAG_DE_HIGH \| DRM_BUS_FLAG_PIXDATA_DRIVE_POSEDGE,
1673	2441	};
1674	2442
1675	2443	static const struct drm_display_mode innolux_at070tn92_mode = {
..	..	@@ -1682,7 +2450,6 @@
1682	2450	.vsync_start = 480 + 22,
1683	2451	.vsync_end = 480 + 22 + 10,
1684	2452	.vtotal = 480 + 22 + 23 + 10,
1685		- .vrefresh = 60,
1686	2453	};
1687	2454
1688	2455	static const struct panel_desc innolux_at070tn92 = {
..	..	@@ -1711,7 +2478,7 @@
1711	2478	static const struct panel_desc innolux_g070y2_l01 = {
1712	2479	.timings = &innolux_g070y2_l01_timing,
1713	2480	.num_timings = 1,
1714		- .bpc = 6,
	2481	+ .bpc = 8,
1715	2482	.size = {
1716	2483	.width = 152,
1717	2484	.height = 91,
..	..	@@ -1723,6 +2490,8 @@
1723	2490	.unprepare = 800,
1724	2491	},
1725	2492	.bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG,
	2493	+ .bus_flags = DRM_BUS_FLAG_DE_HIGH,
	2494	+ .connector_type = DRM_MODE_CONNECTOR_LVDS,
1726	2495	};
1727	2496
1728	2497	static const struct display_timing innolux_g101ice_l01_timing = {
..	..	@@ -1751,6 +2520,7 @@
1751	2520	.disable = 200,
1752	2521	},
1753	2522	.bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG,
	2523	+ .connector_type = DRM_MODE_CONNECTOR_LVDS,
1754	2524	};
1755	2525
1756	2526	static const struct display_timing innolux_g121i1_l01_timing = {
..	..	@@ -1777,7 +2547,8 @@
1777	2547	.enable = 200,
1778	2548	.disable = 20,
1779	2549	},
1780		- .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG,
	2550	+ .bus_format = MEDIA_BUS_FMT_RGB666_1X7X3_SPWG,
	2551	+ .connector_type = DRM_MODE_CONNECTOR_LVDS,
1781	2552	};
1782	2553
1783	2554	static const struct drm_display_mode innolux_g121x1_l03_mode = {
..	..	@@ -1790,7 +2561,6 @@
1790	2561	.vsync_start = 768 + 38,
1791	2562	.vsync_end = 768 + 38 + 1,
1792	2563	.vtotal = 768 + 38 + 1 + 0,
1793		- .vrefresh = 60,
1794	2564	.flags = DRM_MODE_FLAG_NHSYNC \| DRM_MODE_FLAG_NVSYNC,
1795	2565	};
1796	2566
..	..	@@ -1809,23 +2579,32 @@
1809	2579	},
1810	2580	};
1811	2581
1812		-static const struct drm_display_mode innolux_n116bge_mode = {
1813		- .clock = 76420,
1814		- .hdisplay = 1366,
1815		- .hsync_start = 1366 + 136,
1816		- .hsync_end = 1366 + 136 + 30,
1817		- .htotal = 1366 + 136 + 30 + 60,
1818		- .vdisplay = 768,
1819		- .vsync_start = 768 + 8,
1820		- .vsync_end = 768 + 8 + 12,
1821		- .vtotal = 768 + 8 + 12 + 12,
1822		- .vrefresh = 60,
1823		- .flags = DRM_MODE_FLAG_NHSYNC \| DRM_MODE_FLAG_NVSYNC,
	2582	+/*
	2583	+ * Datasheet specifies that at 60 Hz refresh rate:
	2584	+ * - total horizontal time: { 1506, 1592, 1716 }
	2585	+ * - total vertical time: { 788, 800, 868 }
	2586	+ *
	2587	+ * ...but doesn't go into exactly how that should be split into a front
	2588	+ * porch, back porch, or sync length. For now we'll leave a single setting
	2589	+ * here which allows a bit of tweaking of the pixel clock at the expense of
	2590	+ * refresh rate.
	2591	+ */
	2592	+static const struct display_timing innolux_n116bge_timing = {
	2593	+ .pixelclock = { 72600000, 76420000, 80240000 },
	2594	+ .hactive = { 1366, 1366, 1366 },
	2595	+ .hfront_porch = { 136, 136, 136 },
	2596	+ .hback_porch = { 60, 60, 60 },
	2597	+ .hsync_len = { 30, 30, 30 },
	2598	+ .vactive = { 768, 768, 768 },
	2599	+ .vfront_porch = { 8, 8, 8 },
	2600	+ .vback_porch = { 12, 12, 12 },
	2601	+ .vsync_len = { 12, 12, 12 },
	2602	+ .flags = DISPLAY_FLAGS_VSYNC_LOW \| DISPLAY_FLAGS_HSYNC_LOW,
1824	2603	};
1825	2604
1826	2605	static const struct panel_desc innolux_n116bge = {
1827		- .modes = &innolux_n116bge_mode,
1828		- .num_modes = 1,
	2606	+ .timings = &innolux_n116bge_timing,
	2607	+ .num_timings = 1,
1829	2608	.bpc = 6,
1830	2609	.size = {
1831	2610	.width = 256,
..	..	@@ -1843,7 +2622,6 @@
1843	2622	.vsync_start = 768 + 2,
1844	2623	.vsync_end = 768 + 2 + 6,
1845	2624	.vtotal = 768 + 2 + 6 + 12,
1846		- .vrefresh = 60,
1847	2625	};
1848	2626
1849	2627	static const struct panel_desc innolux_n156bge_l21 = {
..	..	@@ -1854,9 +2632,12 @@
1854	2632	.width = 344,
1855	2633	.height = 193,
1856	2634	},
	2635	+ .bus_format = MEDIA_BUS_FMT_RGB666_1X7X3_SPWG,
	2636	+ .bus_flags = DRM_BUS_FLAG_DE_HIGH,
	2637	+ .connector_type = DRM_MODE_CONNECTOR_LVDS,
1857	2638	};
1858	2639
1859		-static const struct drm_display_mode innolux_tv123wam_mode = {
	2640	+static const struct drm_display_mode innolux_p120zdg_bf1_mode = {
1860	2641	.clock = 206016,
1861	2642	.hdisplay = 2160,
1862	2643	.hsync_start = 2160 + 48,
..	..	@@ -1866,19 +2647,19 @@
1866	2647	.vsync_start = 1440 + 3,
1867	2648	.vsync_end = 1440 + 3 + 10,
1868	2649	.vtotal = 1440 + 3 + 10 + 27,
1869		- .vrefresh = 60,
1870	2650	.flags = DRM_MODE_FLAG_PHSYNC \| DRM_MODE_FLAG_PVSYNC,
1871	2651	};
1872	2652
1873		-static const struct panel_desc innolux_tv123wam = {
1874		- .modes = &innolux_tv123wam_mode,
	2653	+static const struct panel_desc innolux_p120zdg_bf1 = {
	2654	+ .modes = &innolux_p120zdg_bf1_mode,
1875	2655	.num_modes = 1,
1876	2656	.bpc = 8,
1877	2657	.size = {
1878		- .width = 259,
1879		- .height = 173,
	2658	+ .width = 254,
	2659	+ .height = 169,
1880	2660	},
1881	2661	.delay = {
	2662	+ .hpd_absent_delay = 200,
1882	2663	.unprepare = 500,
1883	2664	},
1884	2665	};
..	..	@@ -1893,7 +2674,6 @@
1893	2674	.vsync_start = 600 + 16,
1894	2675	.vsync_end = 600 + 16 + 4,
1895	2676	.vtotal = 600 + 16 + 4 + 16,
1896		- .vrefresh = 60,
1897	2677	};
1898	2678
1899	2679	static const struct panel_desc innolux_zj070na_01p = {
..	..	@@ -1904,6 +2684,118 @@
1904	2684	.width = 154,
1905	2685	.height = 90,
1906	2686	},
	2687	+};
	2688	+
	2689	+static const struct drm_display_mode ivo_m133nwf4_r0_mode = {
	2690	+ .clock = 138778,
	2691	+ .hdisplay = 1920,
	2692	+ .hsync_start = 1920 + 24,
	2693	+ .hsync_end = 1920 + 24 + 48,
	2694	+ .htotal = 1920 + 24 + 48 + 88,
	2695	+ .vdisplay = 1080,
	2696	+ .vsync_start = 1080 + 3,
	2697	+ .vsync_end = 1080 + 3 + 12,
	2698	+ .vtotal = 1080 + 3 + 12 + 17,
	2699	+ .flags = DRM_MODE_FLAG_PHSYNC \| DRM_MODE_FLAG_PVSYNC,
	2700	+};
	2701	+
	2702	+static const struct panel_desc ivo_m133nwf4_r0 = {
	2703	+ .modes = &ivo_m133nwf4_r0_mode,
	2704	+ .num_modes = 1,
	2705	+ .bpc = 8,
	2706	+ .size = {
	2707	+ .width = 294,
	2708	+ .height = 165,
	2709	+ },
	2710	+ .delay = {
	2711	+ .hpd_absent_delay = 200,
	2712	+ .unprepare = 500,
	2713	+ },
	2714	+ .bus_format = MEDIA_BUS_FMT_RGB888_1X24,
	2715	+ .bus_flags = DRM_BUS_FLAG_DATA_MSB_TO_LSB,
	2716	+ .connector_type = DRM_MODE_CONNECTOR_eDP,
	2717	+};
	2718	+
	2719	+static const struct drm_display_mode kingdisplay_kd116n21_30nv_a010_mode = {
	2720	+ .clock = 81000,
	2721	+ .hdisplay = 1366,
	2722	+ .hsync_start = 1366 + 40,
	2723	+ .hsync_end = 1366 + 40 + 32,
	2724	+ .htotal = 1366 + 40 + 32 + 62,
	2725	+ .vdisplay = 768,
	2726	+ .vsync_start = 768 + 5,
	2727	+ .vsync_end = 768 + 5 + 5,
	2728	+ .vtotal = 768 + 5 + 5 + 122,
	2729	+ .flags = DRM_MODE_FLAG_NVSYNC \| DRM_MODE_FLAG_NHSYNC,
	2730	+};
	2731	+
	2732	+static const struct panel_desc kingdisplay_kd116n21_30nv_a010 = {
	2733	+ .modes = &kingdisplay_kd116n21_30nv_a010_mode,
	2734	+ .num_modes = 1,
	2735	+ .bpc = 6,
	2736	+ .size = {
	2737	+ .width = 256,
	2738	+ .height = 144,
	2739	+ },
	2740	+ .delay = {
	2741	+ .hpd_absent_delay = 200,
	2742	+ },
	2743	+ .bus_format = MEDIA_BUS_FMT_RGB666_1X18,
	2744	+ .connector_type = DRM_MODE_CONNECTOR_eDP,
	2745	+};
	2746	+
	2747	+static const struct display_timing koe_tx14d24vm1bpa_timing = {
	2748	+ .pixelclock = { 5580000, 5850000, 6200000 },
	2749	+ .hactive = { 320, 320, 320 },
	2750	+ .hfront_porch = { 30, 30, 30 },
	2751	+ .hback_porch = { 30, 30, 30 },
	2752	+ .hsync_len = { 1, 5, 17 },
	2753	+ .vactive = { 240, 240, 240 },
	2754	+ .vfront_porch = { 6, 6, 6 },
	2755	+ .vback_porch = { 5, 5, 5 },
	2756	+ .vsync_len = { 1, 2, 11 },
	2757	+ .flags = DISPLAY_FLAGS_DE_HIGH,
	2758	+};
	2759	+
	2760	+static const struct panel_desc koe_tx14d24vm1bpa = {
	2761	+ .timings = &koe_tx14d24vm1bpa_timing,
	2762	+ .num_timings = 1,
	2763	+ .bpc = 6,
	2764	+ .size = {
	2765	+ .width = 115,
	2766	+ .height = 86,
	2767	+ },
	2768	+};
	2769	+
	2770	+static const struct display_timing koe_tx26d202vm0bwa_timing = {
	2771	+ .pixelclock = { 151820000, 156720000, 159780000 },
	2772	+ .hactive = { 1920, 1920, 1920 },
	2773	+ .hfront_porch = { 105, 130, 142 },
	2774	+ .hback_porch = { 45, 70, 82 },
	2775	+ .hsync_len = { 30, 30, 30 },
	2776	+ .vactive = { 1200, 1200, 1200},
	2777	+ .vfront_porch = { 3, 5, 10 },
	2778	+ .vback_porch = { 2, 5, 10 },
	2779	+ .vsync_len = { 5, 5, 5 },
	2780	+};
	2781	+
	2782	+static const struct panel_desc koe_tx26d202vm0bwa = {
	2783	+ .timings = &koe_tx26d202vm0bwa_timing,
	2784	+ .num_timings = 1,
	2785	+ .bpc = 8,
	2786	+ .size = {
	2787	+ .width = 217,
	2788	+ .height = 136,
	2789	+ },
	2790	+ .delay = {
	2791	+ .prepare = 1000,
	2792	+ .enable = 1000,
	2793	+ .unprepare = 1000,
	2794	+ .disable = 1000,
	2795	+ },
	2796	+ .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG,
	2797	+ .bus_flags = DRM_BUS_FLAG_DE_HIGH,
	2798	+ .connector_type = DRM_MODE_CONNECTOR_LVDS,
1907	2799	};
1908	2800
1909	2801	static const struct display_timing koe_tx31d200vm0baa_timing = {
..	..	@@ -1928,6 +2820,7 @@
1928	2820	.height = 109,
1929	2821	},
1930	2822	.bus_format = MEDIA_BUS_FMT_RGB666_1X7X3_SPWG,
	2823	+ .connector_type = DRM_MODE_CONNECTOR_LVDS,
1931	2824	};
1932	2825
1933	2826	static const struct display_timing kyo_tcg121xglp_timing = {
..	..	@@ -1952,6 +2845,30 @@
1952	2845	.height = 184,
1953	2846	},
1954	2847	.bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG,
	2848	+ .connector_type = DRM_MODE_CONNECTOR_LVDS,
	2849	+};
	2850	+
	2851	+static const struct drm_display_mode lemaker_bl035_rgb_002_mode = {
	2852	+ .clock = 7000,
	2853	+ .hdisplay = 320,
	2854	+ .hsync_start = 320 + 20,
	2855	+ .hsync_end = 320 + 20 + 30,
	2856	+ .htotal = 320 + 20 + 30 + 38,
	2857	+ .vdisplay = 240,
	2858	+ .vsync_start = 240 + 4,
	2859	+ .vsync_end = 240 + 4 + 3,
	2860	+ .vtotal = 240 + 4 + 3 + 15,
	2861	+};
	2862	+
	2863	+static const struct panel_desc lemaker_bl035_rgb_002 = {
	2864	+ .modes = &lemaker_bl035_rgb_002_mode,
	2865	+ .num_modes = 1,
	2866	+ .size = {
	2867	+ .width = 70,
	2868	+ .height = 52,
	2869	+ },
	2870	+ .bus_format = MEDIA_BUS_FMT_RGB888_1X24,
	2871	+ .bus_flags = DRM_BUS_FLAG_DE_LOW,
1955	2872	};
1956	2873
1957	2874	static const struct drm_display_mode lg_lb070wv8_mode = {
..	..	@@ -1964,7 +2881,6 @@
1964	2881	.vsync_start = 480 + 10,
1965	2882	.vsync_end = 480 + 10 + 25,
1966	2883	.vtotal = 480 + 10 + 25 + 10,
1967		- .vrefresh = 60,
1968	2884	};
1969	2885
1970	2886	static const struct panel_desc lg_lb070wv8 = {
..	..	@@ -1976,6 +2892,7 @@
1976	2892	.height = 91,
1977	2893	},
1978	2894	.bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG,
	2895	+ .connector_type = DRM_MODE_CONNECTOR_LVDS,
1979	2896	};
1980	2897
1981	2898	static const struct drm_display_mode lg_lp079qx1_sp0v_mode = {
..	..	@@ -1988,7 +2905,6 @@
1988	2905	.vsync_start = 2048 + 8,
1989	2906	.vsync_end = 2048 + 8 + 4,
1990	2907	.vtotal = 2048 + 8 + 4 + 8,
1991		- .vrefresh = 60,
1992	2908	.flags = DRM_MODE_FLAG_NVSYNC \| DRM_MODE_FLAG_NHSYNC,
1993	2909	};
1994	2910
..	..	@@ -2011,7 +2927,6 @@
2011	2927	.vsync_start = 1536 + 3,
2012	2928	.vsync_end = 1536 + 3 + 1,
2013	2929	.vtotal = 1536 + 3 + 1 + 9,
2014		- .vrefresh = 60,
2015	2930	};
2016	2931
2017	2932	static const struct panel_desc lg_lp097qx1_spa1 = {
..	..	@@ -2033,7 +2948,6 @@
2033	2948	.vsync_start = 1280 + 4,
2034	2949	.vsync_end = 1280 + 4 + 4,
2035	2950	.vtotal = 1280 + 4 + 4 + 12,
2036		- .vrefresh = 60,
2037	2951	};
2038	2952
2039	2953	static const struct panel_desc lg_lp120up1 = {
..	..	@@ -2044,6 +2958,7 @@
2044	2958	.width = 267,
2045	2959	.height = 183,
2046	2960	},
	2961	+ .connector_type = DRM_MODE_CONNECTOR_eDP,
2047	2962	};
2048	2963
2049	2964	static const struct drm_display_mode lg_lp129qe_mode = {
..	..	@@ -2056,7 +2971,6 @@
2056	2971	.vsync_start = 1700 + 3,
2057	2972	.vsync_end = 1700 + 3 + 10,
2058	2973	.vtotal = 1700 + 3 + 10 + 36,
2059		- .vrefresh = 60,
2060	2974	};
2061	2975
2062	2976	static const struct panel_desc lg_lp129qe = {
..	..	@@ -2069,6 +2983,64 @@
2069	2983	},
2070	2984	};
2071	2985
	2986	+static const struct display_timing logictechno_lt161010_2nh_timing = {
	2987	+ .pixelclock = { 26400000, 33300000, 46800000 },
	2988	+ .hactive = { 800, 800, 800 },
	2989	+ .hfront_porch = { 16, 210, 354 },
	2990	+ .hback_porch = { 46, 46, 46 },
	2991	+ .hsync_len = { 1, 20, 40 },
	2992	+ .vactive = { 480, 480, 480 },
	2993	+ .vfront_porch = { 7, 22, 147 },
	2994	+ .vback_porch = { 23, 23, 23 },
	2995	+ .vsync_len = { 1, 10, 20 },
	2996	+ .flags = DISPLAY_FLAGS_HSYNC_LOW \| DISPLAY_FLAGS_VSYNC_LOW \|
	2997	+ DISPLAY_FLAGS_DE_HIGH \| DISPLAY_FLAGS_PIXDATA_POSEDGE \|
	2998	+ DISPLAY_FLAGS_SYNC_POSEDGE,
	2999	+};
	3000	+
	3001	+static const struct panel_desc logictechno_lt161010_2nh = {
	3002	+ .timings = &logictechno_lt161010_2nh_timing,
	3003	+ .num_timings = 1,
	3004	+ .bpc = 6,
	3005	+ .size = {
	3006	+ .width = 154,
	3007	+ .height = 86,
	3008	+ },
	3009	+ .bus_format = MEDIA_BUS_FMT_RGB666_1X18,
	3010	+ .bus_flags = DRM_BUS_FLAG_DE_HIGH \|
	3011	+ DRM_BUS_FLAG_PIXDATA_SAMPLE_NEGEDGE \|
	3012	+ DRM_BUS_FLAG_SYNC_SAMPLE_NEGEDGE,
	3013	+ .connector_type = DRM_MODE_CONNECTOR_DPI,
	3014	+};
	3015	+
	3016	+static const struct display_timing logictechno_lt170410_2whc_timing = {
	3017	+ .pixelclock = { 68900000, 71100000, 73400000 },
	3018	+ .hactive = { 1280, 1280, 1280 },
	3019	+ .hfront_porch = { 23, 60, 71 },
	3020	+ .hback_porch = { 23, 60, 71 },
	3021	+ .hsync_len = { 15, 40, 47 },
	3022	+ .vactive = { 800, 800, 800 },
	3023	+ .vfront_porch = { 5, 7, 10 },
	3024	+ .vback_porch = { 5, 7, 10 },
	3025	+ .vsync_len = { 6, 9, 12 },
	3026	+ .flags = DISPLAY_FLAGS_HSYNC_LOW \| DISPLAY_FLAGS_VSYNC_LOW \|
	3027	+ DISPLAY_FLAGS_DE_HIGH \| DISPLAY_FLAGS_PIXDATA_POSEDGE \|
	3028	+ DISPLAY_FLAGS_SYNC_POSEDGE,
	3029	+};
	3030	+
	3031	+static const struct panel_desc logictechno_lt170410_2whc = {
	3032	+ .timings = &logictechno_lt170410_2whc_timing,
	3033	+ .num_timings = 1,
	3034	+ .bpc = 8,
	3035	+ .size = {
	3036	+ .width = 217,
	3037	+ .height = 136,
	3038	+ },
	3039	+ .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG,
	3040	+ .bus_flags = DRM_BUS_FLAG_DE_HIGH,
	3041	+ .connector_type = DRM_MODE_CONNECTOR_LVDS,
	3042	+};
	3043	+
2072	3044	static const struct drm_display_mode mitsubishi_aa070mc01_mode = {
2073	3045	.clock = 30400,
2074	3046	.hdisplay = 800,
..	..	@@ -2079,8 +3051,41 @@
2079	3051	.vsync_start = 480 + 0,
2080	3052	.vsync_end = 480 + 48 + 1,
2081	3053	.vtotal = 480 + 48 + 1 + 0,
2082		- .vrefresh = 60,
2083	3054	.flags = DRM_MODE_FLAG_NHSYNC \| DRM_MODE_FLAG_NVSYNC,
	3055	+};
	3056	+
	3057	+static const struct drm_display_mode logicpd_type_28_mode = {
	3058	+ .clock = 9107,
	3059	+ .hdisplay = 480,
	3060	+ .hsync_start = 480 + 3,
	3061	+ .hsync_end = 480 + 3 + 42,
	3062	+ .htotal = 480 + 3 + 42 + 2,
	3063	+
	3064	+ .vdisplay = 272,
	3065	+ .vsync_start = 272 + 2,
	3066	+ .vsync_end = 272 + 2 + 11,
	3067	+ .vtotal = 272 + 2 + 11 + 3,
	3068	+ .flags = DRM_MODE_FLAG_PHSYNC \| DRM_MODE_FLAG_PVSYNC,
	3069	+};
	3070	+
	3071	+static const struct panel_desc logicpd_type_28 = {
	3072	+ .modes = &logicpd_type_28_mode,
	3073	+ .num_modes = 1,
	3074	+ .bpc = 8,
	3075	+ .size = {
	3076	+ .width = 105,
	3077	+ .height = 67,
	3078	+ },
	3079	+ .delay = {
	3080	+ .prepare = 200,
	3081	+ .enable = 200,
	3082	+ .unprepare = 200,
	3083	+ .disable = 200,
	3084	+ },
	3085	+ .bus_format = MEDIA_BUS_FMT_RGB888_1X24,
	3086	+ .bus_flags = DRM_BUS_FLAG_DE_HIGH \| DRM_BUS_FLAG_PIXDATA_DRIVE_POSEDGE \|
	3087	+ DRM_BUS_FLAG_SYNC_DRIVE_NEGEDGE,
	3088	+ .connector_type = DRM_MODE_CONNECTOR_DPI,
2084	3089	};
2085	3090
2086	3091	static const struct panel_desc mitsubishi_aa070mc01 = {
..	..	@@ -2098,6 +3103,7 @@
2098	3103	.disable = 400,
2099	3104	},
2100	3105	.bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG,
	3106	+ .connector_type = DRM_MODE_CONNECTOR_LVDS,
2101	3107	.bus_flags = DRM_BUS_FLAG_DE_HIGH,
2102	3108	};
2103	3109
..	..	@@ -2126,6 +3132,7 @@
2126	3132	.disable = 50,
2127	3133	},
2128	3134	.bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG,
	3135	+ .connector_type = DRM_MODE_CONNECTOR_LVDS,
2129	3136	};
2130	3137
2131	3138	static const struct drm_display_mode nec_nl4827hc19_05b_mode = {
..	..	@@ -2138,7 +3145,6 @@
2138	3145	.vsync_start = 272 + 2,
2139	3146	.vsync_end = 272 + 2 + 4,
2140	3147	.vtotal = 272 + 2 + 4 + 2,
2141		- .vrefresh = 74,
2142	3148	.flags = DRM_MODE_FLAG_NVSYNC \| DRM_MODE_FLAG_NHSYNC,
2143	3149	};
2144	3150
..	..	@@ -2151,7 +3157,7 @@
2151	3157	.height = 54,
2152	3158	},
2153	3159	.bus_format = MEDIA_BUS_FMT_RGB888_1X24,
2154		- .bus_flags = DRM_BUS_FLAG_PIXDATA_POSEDGE,
	3160	+ .bus_flags = DRM_BUS_FLAG_PIXDATA_DRIVE_POSEDGE,
2155	3161	};
2156	3162
2157	3163	static const struct drm_display_mode netron_dy_e231732_mode = {
..	..	@@ -2164,7 +3170,6 @@
2164	3170	.vsync_start = 600 + 127,
2165	3171	.vsync_end = 600 + 127 + 20,
2166	3172	.vtotal = 600 + 127 + 20 + 3,
2167		- .vrefresh = 60,
2168	3173	};
2169	3174
2170	3175	static const struct panel_desc netron_dy_e231732 = {
..	..	@@ -2177,6 +3182,49 @@
2177	3182	.bus_format = MEDIA_BUS_FMT_RGB666_1X18,
2178	3183	};
2179	3184
	3185	+static const struct drm_display_mode neweast_wjfh116008a_modes[] = {
	3186	+ {
	3187	+ .clock = 138500,
	3188	+ .hdisplay = 1920,
	3189	+ .hsync_start = 1920 + 48,
	3190	+ .hsync_end = 1920 + 48 + 32,
	3191	+ .htotal = 1920 + 48 + 32 + 80,
	3192	+ .vdisplay = 1080,
	3193	+ .vsync_start = 1080 + 3,
	3194	+ .vsync_end = 1080 + 3 + 5,
	3195	+ .vtotal = 1080 + 3 + 5 + 23,
	3196	+ .flags = DRM_MODE_FLAG_NVSYNC \| DRM_MODE_FLAG_NHSYNC,
	3197	+ }, {
	3198	+ .clock = 110920,
	3199	+ .hdisplay = 1920,
	3200	+ .hsync_start = 1920 + 48,
	3201	+ .hsync_end = 1920 + 48 + 32,
	3202	+ .htotal = 1920 + 48 + 32 + 80,
	3203	+ .vdisplay = 1080,
	3204	+ .vsync_start = 1080 + 3,
	3205	+ .vsync_end = 1080 + 3 + 5,
	3206	+ .vtotal = 1080 + 3 + 5 + 23,
	3207	+ .flags = DRM_MODE_FLAG_NVSYNC \| DRM_MODE_FLAG_NHSYNC,
	3208	+ }
	3209	+};
	3210	+
	3211	+static const struct panel_desc neweast_wjfh116008a = {
	3212	+ .modes = neweast_wjfh116008a_modes,
	3213	+ .num_modes = 2,
	3214	+ .bpc = 6,
	3215	+ .size = {
	3216	+ .width = 260,
	3217	+ .height = 150,
	3218	+ },
	3219	+ .delay = {
	3220	+ .prepare = 110,
	3221	+ .enable = 20,
	3222	+ .unprepare = 500,
	3223	+ },
	3224	+ .bus_format = MEDIA_BUS_FMT_RGB666_1X18,
	3225	+ .connector_type = DRM_MODE_CONNECTOR_eDP,
	3226	+};
	3227	+
2180	3228	static const struct drm_display_mode newhaven_nhd_43_480272ef_atxl_mode = {
2181	3229	.clock = 9000,
2182	3230	.hdisplay = 480,
..	..	@@ -2187,7 +3235,6 @@
2187	3235	.vsync_start = 272 + 2,
2188	3236	.vsync_end = 272 + 2 + 10,
2189	3237	.vtotal = 272 + 2 + 10 + 2,
2190		- .vrefresh = 60,
2191	3238	.flags = DRM_MODE_FLAG_NVSYNC \| DRM_MODE_FLAG_NHSYNC,
2192	3239	};
2193	3240
..	..	@@ -2200,8 +3247,9 @@
2200	3247	.height = 54,
2201	3248	},
2202	3249	.bus_format = MEDIA_BUS_FMT_RGB888_1X24,
2203		- .bus_flags = DRM_BUS_FLAG_DE_HIGH \| DRM_BUS_FLAG_PIXDATA_POSEDGE \|
2204		- DRM_BUS_FLAG_SYNC_POSEDGE,
	3250	+ .bus_flags = DRM_BUS_FLAG_DE_HIGH \| DRM_BUS_FLAG_PIXDATA_DRIVE_POSEDGE \|
	3251	+ DRM_BUS_FLAG_SYNC_DRIVE_POSEDGE,
	3252	+ .connector_type = DRM_MODE_CONNECTOR_DPI,
2205	3253	};
2206	3254
2207	3255	static const struct display_timing nlt_nl192108ac18_02d_timing = {
..	..	@@ -2228,6 +3276,7 @@
2228	3276	.unprepare = 500,
2229	3277	},
2230	3278	.bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG,
	3279	+ .connector_type = DRM_MODE_CONNECTOR_LVDS,
2231	3280	};
2232	3281
2233	3282	static const struct drm_display_mode nvd_9128_mode = {
..	..	@@ -2251,6 +3300,7 @@
2251	3300	.height = 88,
2252	3301	},
2253	3302	.bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG,
	3303	+ .connector_type = DRM_MODE_CONNECTOR_LVDS,
2254	3304	};
2255	3305
2256	3306	static const struct display_timing okaya_rs800480t_7x0gp_timing = {
..	..	@@ -2293,7 +3343,6 @@
2293	3343	.vsync_start = 272 + 8,
2294	3344	.vsync_end = 272 + 8 + 5,
2295	3345	.vtotal = 272 + 8 + 5 + 3,
2296		- .vrefresh = 60,
2297	3346	};
2298	3347
2299	3348	static const struct panel_desc olimex_lcd_olinuxino_43ts = {
..	..	@@ -2321,7 +3370,6 @@
2321	3370	.vsync_start = 483,
2322	3371	.vsync_end = 493,
2323	3372	.vtotal = 500,
2324		- .vrefresh = 60,
2325	3373	.flags = DRM_MODE_FLAG_NVSYNC \| DRM_MODE_FLAG_NHSYNC,
2326	3374	};
2327	3375
..	..	@@ -2340,6 +3388,32 @@
2340	3388	.bus_format = MEDIA_BUS_FMT_RGB666_1X18,
2341	3389	};
2342	3390
	3391	+static const struct drm_display_mode ortustech_com37h3m_mode = {
	3392	+ .clock = 22230,
	3393	+ .hdisplay = 480,
	3394	+ .hsync_start = 480 + 40,
	3395	+ .hsync_end = 480 + 40 + 10,
	3396	+ .htotal = 480 + 40 + 10 + 40,
	3397	+ .vdisplay = 640,
	3398	+ .vsync_start = 640 + 4,
	3399	+ .vsync_end = 640 + 4 + 2,
	3400	+ .vtotal = 640 + 4 + 2 + 4,
	3401	+ .flags = DRM_MODE_FLAG_NVSYNC \| DRM_MODE_FLAG_NHSYNC,
	3402	+};
	3403	+
	3404	+static const struct panel_desc ortustech_com37h3m = {
	3405	+ .modes = &ortustech_com37h3m_mode,
	3406	+ .num_modes = 1,
	3407	+ .bpc = 8,
	3408	+ .size = {
	3409	+ .width = 56, /* 56.16mm */
	3410	+ .height = 75, /* 74.88mm */
	3411	+ },
	3412	+ .bus_format = MEDIA_BUS_FMT_RGB888_1X24,
	3413	+ .bus_flags = DRM_BUS_FLAG_DE_HIGH \| DRM_BUS_FLAG_PIXDATA_SAMPLE_NEGEDGE \|
	3414	+ DRM_BUS_FLAG_SYNC_DRIVE_POSEDGE,
	3415	+};
	3416	+
2343	3417	static const struct drm_display_mode ortustech_com43h4m85ulc_mode = {
2344	3418	.clock = 25000,
2345	3419	.hdisplay = 480,
..	..	@@ -2350,19 +3424,95 @@
2350	3424	.vsync_start = 800 + 3,
2351	3425	.vsync_end = 800 + 3 + 3,
2352	3426	.vtotal = 800 + 3 + 3 + 3,
2353		- .vrefresh = 60,
2354	3427	};
2355	3428
2356	3429	static const struct panel_desc ortustech_com43h4m85ulc = {
2357	3430	.modes = &ortustech_com43h4m85ulc_mode,
2358	3431	.num_modes = 1,
2359		- .bpc = 8,
	3432	+ .bpc = 6,
2360	3433	.size = {
2361	3434	.width = 56,
2362	3435	.height = 93,
2363	3436	},
	3437	+ .bus_format = MEDIA_BUS_FMT_RGB666_1X18,
	3438	+ .bus_flags = DRM_BUS_FLAG_DE_HIGH \| DRM_BUS_FLAG_PIXDATA_DRIVE_POSEDGE,
	3439	+ .connector_type = DRM_MODE_CONNECTOR_DPI,
	3440	+};
	3441	+
	3442	+static const struct drm_display_mode osddisplays_osd070t1718_19ts_mode = {
	3443	+ .clock = 33000,
	3444	+ .hdisplay = 800,
	3445	+ .hsync_start = 800 + 210,
	3446	+ .hsync_end = 800 + 210 + 30,
	3447	+ .htotal = 800 + 210 + 30 + 16,
	3448	+ .vdisplay = 480,
	3449	+ .vsync_start = 480 + 22,
	3450	+ .vsync_end = 480 + 22 + 13,
	3451	+ .vtotal = 480 + 22 + 13 + 10,
	3452	+ .flags = DRM_MODE_FLAG_NVSYNC \| DRM_MODE_FLAG_NHSYNC,
	3453	+};
	3454	+
	3455	+static const struct panel_desc osddisplays_osd070t1718_19ts = {
	3456	+ .modes = &osddisplays_osd070t1718_19ts_mode,
	3457	+ .num_modes = 1,
	3458	+ .bpc = 8,
	3459	+ .size = {
	3460	+ .width = 152,
	3461	+ .height = 91,
	3462	+ },
2364	3463	.bus_format = MEDIA_BUS_FMT_RGB888_1X24,
2365		- .bus_flags = DRM_BUS_FLAG_DE_HIGH \| DRM_BUS_FLAG_PIXDATA_POSEDGE,
	3464	+ .bus_flags = DRM_BUS_FLAG_DE_HIGH \| DRM_BUS_FLAG_PIXDATA_DRIVE_POSEDGE \|
	3465	+ DRM_BUS_FLAG_SYNC_DRIVE_POSEDGE,
	3466	+ .connector_type = DRM_MODE_CONNECTOR_DPI,
	3467	+};
	3468	+
	3469	+static const struct drm_display_mode pda_91_00156_a0_mode = {
	3470	+ .clock = 33300,
	3471	+ .hdisplay = 800,
	3472	+ .hsync_start = 800 + 1,
	3473	+ .hsync_end = 800 + 1 + 64,
	3474	+ .htotal = 800 + 1 + 64 + 64,
	3475	+ .vdisplay = 480,
	3476	+ .vsync_start = 480 + 1,
	3477	+ .vsync_end = 480 + 1 + 23,
	3478	+ .vtotal = 480 + 1 + 23 + 22,
	3479	+};
	3480	+
	3481	+static const struct panel_desc pda_91_00156_a0 = {
	3482	+ .modes = &pda_91_00156_a0_mode,
	3483	+ .num_modes = 1,
	3484	+ .size = {
	3485	+ .width = 152,
	3486	+ .height = 91,
	3487	+ },
	3488	+ .bus_format = MEDIA_BUS_FMT_RGB888_1X24,
	3489	+};
	3490	+
	3491	+static const struct drm_display_mode powertip_ph800480t013_idf02_mode = {
	3492	+ .clock = 24750,
	3493	+ .hdisplay = 800,
	3494	+ .hsync_start = 800 + 54,
	3495	+ .hsync_end = 800 + 54 + 2,
	3496	+ .htotal = 800 + 54 + 2 + 44,
	3497	+ .vdisplay = 480,
	3498	+ .vsync_start = 480 + 49,
	3499	+ .vsync_end = 480 + 49 + 2,
	3500	+ .vtotal = 480 + 49 + 2 + 22,
	3501	+ .flags = DRM_MODE_FLAG_NVSYNC \| DRM_MODE_FLAG_NHSYNC,
	3502	+};
	3503	+
	3504	+static const struct panel_desc powertip_ph800480t013_idf02 = {
	3505	+ .modes = &powertip_ph800480t013_idf02_mode,
	3506	+ .num_modes = 1,
	3507	+ .size = {
	3508	+ .width = 152,
	3509	+ .height = 91,
	3510	+ },
	3511	+ .bus_flags = DRM_BUS_FLAG_DE_HIGH \|
	3512	+ DRM_BUS_FLAG_PIXDATA_SAMPLE_NEGEDGE \|
	3513	+ DRM_BUS_FLAG_SYNC_SAMPLE_NEGEDGE,
	3514	+ .bus_format = MEDIA_BUS_FMT_RGB888_1X24,
	3515	+ .connector_type = DRM_MODE_CONNECTOR_DPI,
2366	3516	};
2367	3517
2368	3518	static const struct drm_display_mode qd43003c0_40_mode = {
..	..	@@ -2375,7 +3525,6 @@
2375	3525	.vsync_start = 272 + 4,
2376	3526	.vsync_end = 272 + 4 + 10,
2377	3527	.vtotal = 272 + 4 + 10 + 2,
2378		- .vrefresh = 60,
2379	3528	};
2380	3529
2381	3530	static const struct panel_desc qd43003c0_40 = {
..	..	@@ -2419,6 +3568,34 @@
2419	3568	.bus_format = MEDIA_BUS_FMT_RGB666_1X18,
2420	3569	};
2421	3570
	3571	+static const struct drm_display_mode rocktech_rk101ii01d_ct_mode = {
	3572	+ .clock = 71100,
	3573	+ .hdisplay = 1280,
	3574	+ .hsync_start = 1280 + 48,
	3575	+ .hsync_end = 1280 + 48 + 32,
	3576	+ .htotal = 1280 + 48 + 32 + 80,
	3577	+ .vdisplay = 800,
	3578	+ .vsync_start = 800 + 2,
	3579	+ .vsync_end = 800 + 2 + 5,
	3580	+ .vtotal = 800 + 2 + 5 + 16,
	3581	+};
	3582	+
	3583	+static const struct panel_desc rocktech_rk101ii01d_ct = {
	3584	+ .modes = &rocktech_rk101ii01d_ct_mode,
	3585	+ .num_modes = 1,
	3586	+ .size = {
	3587	+ .width = 217,
	3588	+ .height = 136,
	3589	+ },
	3590	+ .delay = {
	3591	+ .prepare = 50,
	3592	+ .disable = 50,
	3593	+ },
	3594	+ .bus_flags = DRM_BUS_FLAG_DE_HIGH,
	3595	+ .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG,
	3596	+ .connector_type = DRM_MODE_CONNECTOR_LVDS,
	3597	+};
	3598	+
2422	3599	static const struct drm_display_mode samsung_lsn122dl01_c01_mode = {
2423	3600	.clock = 271560,
2424	3601	.hdisplay = 2560,
..	..	@@ -2429,7 +3606,6 @@
2429	3606	.vsync_start = 1600 + 2,
2430	3607	.vsync_end = 1600 + 2 + 5,
2431	3608	.vtotal = 1600 + 2 + 5 + 57,
2432		- .vrefresh = 60,
2433	3609	};
2434	3610
2435	3611	static const struct panel_desc samsung_lsn122dl01_c01 = {
..	..	@@ -2451,7 +3627,6 @@
2451	3627	.vsync_start = 600 + 3,
2452	3628	.vsync_end = 600 + 3 + 6,
2453	3629	.vtotal = 600 + 3 + 6 + 61,
2454		- .vrefresh = 60,
2455	3630	};
2456	3631
2457	3632	static const struct panel_desc samsung_ltn101nt05 = {
..	..	@@ -2462,6 +3637,9 @@
2462	3637	.width = 223,
2463	3638	.height = 125,
2464	3639	},
	3640	+ .bus_format = MEDIA_BUS_FMT_RGB666_1X7X3_SPWG,
	3641	+ .bus_flags = DRM_BUS_FLAG_DE_HIGH,
	3642	+ .connector_type = DRM_MODE_CONNECTOR_LVDS,
2465	3643	};
2466	3644
2467	3645	static const struct drm_display_mode samsung_ltn140at29_301_mode = {
..	..	@@ -2474,7 +3652,6 @@
2474	3652	.vsync_start = 768 + 2,
2475	3653	.vsync_end = 768 + 2 + 5,
2476	3654	.vtotal = 768 + 2 + 5 + 17,
2477		- .vrefresh = 60,
2478	3655	};
2479	3656
2480	3657	static const struct panel_desc samsung_ltn140at29_301 = {
..	..	@@ -2487,6 +3664,81 @@
2487	3664	},
2488	3665	};
2489	3666
	3667	+static const struct display_timing satoz_sat050at40h12r2_timing = {
	3668	+ .pixelclock = {33300000, 33300000, 50000000},
	3669	+ .hactive = {800, 800, 800},
	3670	+ .hfront_porch = {16, 210, 354},
	3671	+ .hback_porch = {46, 46, 46},
	3672	+ .hsync_len = {1, 1, 40},
	3673	+ .vactive = {480, 480, 480},
	3674	+ .vfront_porch = {7, 22, 147},
	3675	+ .vback_porch = {23, 23, 23},
	3676	+ .vsync_len = {1, 1, 20},
	3677	+};
	3678	+
	3679	+static const struct panel_desc satoz_sat050at40h12r2 = {
	3680	+ .timings = &satoz_sat050at40h12r2_timing,
	3681	+ .num_timings = 1,
	3682	+ .bpc = 8,
	3683	+ .size = {
	3684	+ .width = 108,
	3685	+ .height = 65,
	3686	+ },
	3687	+ .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG,
	3688	+ .connector_type = DRM_MODE_CONNECTOR_LVDS,
	3689	+};
	3690	+
	3691	+static const struct drm_display_mode sharp_ld_d5116z01b_mode = {
	3692	+ .clock = 168480,
	3693	+ .hdisplay = 1920,
	3694	+ .hsync_start = 1920 + 48,
	3695	+ .hsync_end = 1920 + 48 + 32,
	3696	+ .htotal = 1920 + 48 + 32 + 80,
	3697	+ .vdisplay = 1280,
	3698	+ .vsync_start = 1280 + 3,
	3699	+ .vsync_end = 1280 + 3 + 10,
	3700	+ .vtotal = 1280 + 3 + 10 + 57,
	3701	+ .flags = DRM_MODE_FLAG_PHSYNC \| DRM_MODE_FLAG_PVSYNC,
	3702	+};
	3703	+
	3704	+static const struct panel_desc sharp_ld_d5116z01b = {
	3705	+ .modes = &sharp_ld_d5116z01b_mode,
	3706	+ .num_modes = 1,
	3707	+ .bpc = 8,
	3708	+ .size = {
	3709	+ .width = 260,
	3710	+ .height = 120,
	3711	+ },
	3712	+ .bus_format = MEDIA_BUS_FMT_RGB888_1X24,
	3713	+ .bus_flags = DRM_BUS_FLAG_DATA_MSB_TO_LSB,
	3714	+};
	3715	+
	3716	+static const struct drm_display_mode sharp_lq070y3dg3b_mode = {
	3717	+ .clock = 33260,
	3718	+ .hdisplay = 800,
	3719	+ .hsync_start = 800 + 64,
	3720	+ .hsync_end = 800 + 64 + 128,
	3721	+ .htotal = 800 + 64 + 128 + 64,
	3722	+ .vdisplay = 480,
	3723	+ .vsync_start = 480 + 8,
	3724	+ .vsync_end = 480 + 8 + 2,
	3725	+ .vtotal = 480 + 8 + 2 + 35,
	3726	+ .flags = DISPLAY_FLAGS_PIXDATA_POSEDGE,
	3727	+};
	3728	+
	3729	+static const struct panel_desc sharp_lq070y3dg3b = {
	3730	+ .modes = &sharp_lq070y3dg3b_mode,
	3731	+ .num_modes = 1,
	3732	+ .bpc = 8,
	3733	+ .size = {
	3734	+ .width = 152, /* 152.4mm */
	3735	+ .height = 91, /* 91.4mm */
	3736	+ },
	3737	+ .bus_format = MEDIA_BUS_FMT_RGB888_1X24,
	3738	+ .bus_flags = DRM_BUS_FLAG_DE_HIGH \| DRM_BUS_FLAG_PIXDATA_SAMPLE_NEGEDGE \|
	3739	+ DRM_BUS_FLAG_SYNC_DRIVE_POSEDGE,
	3740	+};
	3741	+
2490	3742	static const struct drm_display_mode sharp_lq035q7db03_mode = {
2491	3743	.clock = 5500,
2492	3744	.hdisplay = 240,
..	..	@@ -2497,7 +3749,6 @@
2497	3749	.vsync_start = 320 + 9,
2498	3750	.vsync_end = 320 + 9 + 1,
2499	3751	.vtotal = 320 + 9 + 1 + 7,
2500		- .vrefresh = 60,
2501	3752	};
2502	3753
2503	3754	static const struct panel_desc sharp_lq035q7db03 = {
..	..	@@ -2533,6 +3784,7 @@
2533	3784	.height = 136,
2534	3785	},
2535	3786	.bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_JEIDA,
	3787	+ .connector_type = DRM_MODE_CONNECTOR_LVDS,
2536	3788	};
2537	3789
2538	3790	static const struct display_timing sharp_lq123p1jx31_timing = {
..	..	@@ -2563,28 +3815,45 @@
2563	3815	},
2564	3816	};
2565	3817
2566		-static const struct drm_display_mode sharp_lq150x1lg11_mode = {
2567		- .clock = 71100,
2568		- .hdisplay = 1024,
2569		- .hsync_start = 1024 + 168,
2570		- .hsync_end = 1024 + 168 + 64,
2571		- .htotal = 1024 + 168 + 64 + 88,
2572		- .vdisplay = 768,
2573		- .vsync_start = 768 + 37,
2574		- .vsync_end = 768 + 37 + 2,
2575		- .vtotal = 768 + 37 + 2 + 8,
2576		- .vrefresh = 60,
	3818	+static const struct drm_display_mode sharp_ls020b1dd01d_modes[] = {
	3819	+ { /* 50 Hz */
	3820	+ .clock = 3000,
	3821	+ .hdisplay = 240,
	3822	+ .hsync_start = 240 + 58,
	3823	+ .hsync_end = 240 + 58 + 1,
	3824	+ .htotal = 240 + 58 + 1 + 1,
	3825	+ .vdisplay = 160,
	3826	+ .vsync_start = 160 + 24,
	3827	+ .vsync_end = 160 + 24 + 10,
	3828	+ .vtotal = 160 + 24 + 10 + 6,
	3829	+ .flags = DRM_MODE_FLAG_PHSYNC \| DRM_MODE_FLAG_NVSYNC,
	3830	+ },
	3831	+ { /* 60 Hz */
	3832	+ .clock = 3000,
	3833	+ .hdisplay = 240,
	3834	+ .hsync_start = 240 + 8,
	3835	+ .hsync_end = 240 + 8 + 1,
	3836	+ .htotal = 240 + 8 + 1 + 1,
	3837	+ .vdisplay = 160,
	3838	+ .vsync_start = 160 + 24,
	3839	+ .vsync_end = 160 + 24 + 10,
	3840	+ .vtotal = 160 + 24 + 10 + 6,
	3841	+ .flags = DRM_MODE_FLAG_PHSYNC \| DRM_MODE_FLAG_NVSYNC,
	3842	+ },
2577	3843	};
2578	3844
2579		-static const struct panel_desc sharp_lq150x1lg11 = {
2580		- .modes = &sharp_lq150x1lg11_mode,
2581		- .num_modes = 1,
	3845	+static const struct panel_desc sharp_ls020b1dd01d = {
	3846	+ .modes = sharp_ls020b1dd01d_modes,
	3847	+ .num_modes = ARRAY_SIZE(sharp_ls020b1dd01d_modes),
2582	3848	.bpc = 6,
2583	3849	.size = {
2584		- .width = 304,
2585		- .height = 228,
	3850	+ .width = 42,
	3851	+ .height = 28,
2586	3852	},
2587	3853	.bus_format = MEDIA_BUS_FMT_RGB565_1X16,
	3854	+ .bus_flags = DRM_BUS_FLAG_DE_HIGH
	3855	+ \| DRM_BUS_FLAG_PIXDATA_SAMPLE_POSEDGE
	3856	+ \| DRM_BUS_FLAG_SHARP_SIGNALS,
2588	3857	};
2589	3858
2590	3859	static const struct drm_display_mode shelly_sca07010_bfn_lnn_mode = {
..	..	@@ -2597,7 +3866,6 @@
2597	3866	.vsync_start = 480 + 1,
2598	3867	.vsync_end = 480 + 1 + 23,
2599	3868	.vtotal = 480 + 1 + 23 + 22,
2600		- .vrefresh = 60,
2601	3869	};
2602	3870
2603	3871	static const struct panel_desc shelly_sca07010_bfn_lnn = {
..	..	@@ -2610,6 +3878,31 @@
2610	3878	.bus_format = MEDIA_BUS_FMT_RGB666_1X18,
2611	3879	};
2612	3880
	3881	+static const struct drm_display_mode starry_kr070pe2t_mode = {
	3882	+ .clock = 33000,
	3883	+ .hdisplay = 800,
	3884	+ .hsync_start = 800 + 209,
	3885	+ .hsync_end = 800 + 209 + 1,
	3886	+ .htotal = 800 + 209 + 1 + 45,
	3887	+ .vdisplay = 480,
	3888	+ .vsync_start = 480 + 22,
	3889	+ .vsync_end = 480 + 22 + 1,
	3890	+ .vtotal = 480 + 22 + 1 + 22,
	3891	+};
	3892	+
	3893	+static const struct panel_desc starry_kr070pe2t = {
	3894	+ .modes = &starry_kr070pe2t_mode,
	3895	+ .num_modes = 1,
	3896	+ .bpc = 8,
	3897	+ .size = {
	3898	+ .width = 152,
	3899	+ .height = 86,
	3900	+ },
	3901	+ .bus_format = MEDIA_BUS_FMT_RGB888_1X24,
	3902	+ .bus_flags = DRM_BUS_FLAG_DE_HIGH \| DRM_BUS_FLAG_PIXDATA_DRIVE_NEGEDGE,
	3903	+ .connector_type = DRM_MODE_CONNECTOR_DPI,
	3904	+};
	3905	+
2613	3906	static const struct drm_display_mode starry_kr122ea0sra_mode = {
2614	3907	.clock = 147000,
2615	3908	.hdisplay = 1920,
..	..	@@ -2620,7 +3913,6 @@
2620	3913	.vsync_start = 1200 + 15,
2621	3914	.vsync_end = 1200 + 15 + 2,
2622	3915	.vtotal = 1200 + 15 + 2 + 18,
2623		- .vrefresh = 60,
2624	3916	.flags = DRM_MODE_FLAG_NVSYNC \| DRM_MODE_FLAG_NHSYNC,
2625	3917	};
2626	3918
..	..	@@ -2636,6 +3928,30 @@
2636	3928	.enable = 50,
2637	3929	.unprepare = 10 + 500,
2638	3930	},
	3931	+};
	3932	+
	3933	+static const struct drm_display_mode tfc_s9700rtwv43tr_01b_mode = {
	3934	+ .clock = 30000,
	3935	+ .hdisplay = 800,
	3936	+ .hsync_start = 800 + 39,
	3937	+ .hsync_end = 800 + 39 + 47,
	3938	+ .htotal = 800 + 39 + 47 + 39,
	3939	+ .vdisplay = 480,
	3940	+ .vsync_start = 480 + 13,
	3941	+ .vsync_end = 480 + 13 + 2,
	3942	+ .vtotal = 480 + 13 + 2 + 29,
	3943	+};
	3944	+
	3945	+static const struct panel_desc tfc_s9700rtwv43tr_01b = {
	3946	+ .modes = &tfc_s9700rtwv43tr_01b_mode,
	3947	+ .num_modes = 1,
	3948	+ .bpc = 8,
	3949	+ .size = {
	3950	+ .width = 155,
	3951	+ .height = 90,
	3952	+ },
	3953	+ .bus_format = MEDIA_BUS_FMT_RGB888_1X24,
	3954	+ .bus_flags = DRM_BUS_FLAG_DE_HIGH \| DRM_BUS_FLAG_PIXDATA_SAMPLE_NEGEDGE,
2639	3955	};
2640	3956
2641	3957	static const struct display_timing tianma_tm070jdhg30_timing = {
..	..	@@ -2660,6 +3976,19 @@
2660	3976	.height = 95,
2661	3977	},
2662	3978	.bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG,
	3979	+ .connector_type = DRM_MODE_CONNECTOR_LVDS,
	3980	+};
	3981	+
	3982	+static const struct panel_desc tianma_tm070jvhg33 = {
	3983	+ .timings = &tianma_tm070jdhg30_timing,
	3984	+ .num_timings = 1,
	3985	+ .bpc = 8,
	3986	+ .size = {
	3987	+ .width = 150,
	3988	+ .height = 94,
	3989	+ },
	3990	+ .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG,
	3991	+ .connector_type = DRM_MODE_CONNECTOR_LVDS,
2663	3992	};
2664	3993
2665	3994	static const struct display_timing tianma_tm070rvhg71_timing = {
..	..	@@ -2684,6 +4013,63 @@
2684	4013	.height = 86,
2685	4014	},
2686	4015	.bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG,
	4016	+ .connector_type = DRM_MODE_CONNECTOR_LVDS,
	4017	+};
	4018	+
	4019	+static const struct drm_display_mode ti_nspire_cx_lcd_mode[] = {
	4020	+ {
	4021	+ .clock = 10000,
	4022	+ .hdisplay = 320,
	4023	+ .hsync_start = 320 + 50,
	4024	+ .hsync_end = 320 + 50 + 6,
	4025	+ .htotal = 320 + 50 + 6 + 38,
	4026	+ .vdisplay = 240,
	4027	+ .vsync_start = 240 + 3,
	4028	+ .vsync_end = 240 + 3 + 1,
	4029	+ .vtotal = 240 + 3 + 1 + 17,
	4030	+ .flags = DRM_MODE_FLAG_NVSYNC \| DRM_MODE_FLAG_NHSYNC,
	4031	+ },
	4032	+};
	4033	+
	4034	+static const struct panel_desc ti_nspire_cx_lcd_panel = {
	4035	+ .modes = ti_nspire_cx_lcd_mode,
	4036	+ .num_modes = 1,
	4037	+ .bpc = 8,
	4038	+ .size = {
	4039	+ .width = 65,
	4040	+ .height = 49,
	4041	+ },
	4042	+ .bus_format = MEDIA_BUS_FMT_RGB888_1X24,
	4043	+ .bus_flags = DRM_BUS_FLAG_PIXDATA_SAMPLE_POSEDGE,
	4044	+};
	4045	+
	4046	+static const struct drm_display_mode ti_nspire_classic_lcd_mode[] = {
	4047	+ {
	4048	+ .clock = 10000,
	4049	+ .hdisplay = 320,
	4050	+ .hsync_start = 320 + 6,
	4051	+ .hsync_end = 320 + 6 + 6,
	4052	+ .htotal = 320 + 6 + 6 + 6,
	4053	+ .vdisplay = 240,
	4054	+ .vsync_start = 240 + 0,
	4055	+ .vsync_end = 240 + 0 + 1,
	4056	+ .vtotal = 240 + 0 + 1 + 0,
	4057	+ .flags = DRM_MODE_FLAG_PHSYNC \| DRM_MODE_FLAG_PVSYNC,
	4058	+ },
	4059	+};
	4060	+
	4061	+static const struct panel_desc ti_nspire_classic_lcd_panel = {
	4062	+ .modes = ti_nspire_classic_lcd_mode,
	4063	+ .num_modes = 1,
	4064	+ /* The grayscale panel has 8 bit for the color .. Y (black) */
	4065	+ .bpc = 8,
	4066	+ .size = {
	4067	+ .width = 71,
	4068	+ .height = 53,
	4069	+ },
	4070	+ /* This is the grayscale bus format */
	4071	+ .bus_format = MEDIA_BUS_FMT_Y8_1X8,
	4072	+ .bus_flags = DRM_BUS_FLAG_PIXDATA_SAMPLE_NEGEDGE,
2687	4073	};
2688	4074
2689	4075	static const struct drm_display_mode toshiba_lt089ac29000_mode = {
..	..	@@ -2696,7 +4082,6 @@
2696	4082	.vsync_start = 768 + 20,
2697	4083	.vsync_end = 768 + 20 + 7,
2698	4084	.vtotal = 768 + 20 + 7 + 3,
2699		- .vrefresh = 60,
2700	4085	};
2701	4086
2702	4087	static const struct panel_desc toshiba_lt089ac29000 = {
..	..	@@ -2706,8 +4091,9 @@
2706	4091	.width = 194,
2707	4092	.height = 116,
2708	4093	},
2709		- .bus_format = MEDIA_BUS_FMT_RGB888_1X24,
2710		- .bus_flags = DRM_BUS_FLAG_DE_HIGH \| DRM_BUS_FLAG_PIXDATA_POSEDGE,
	4094	+ .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_JEIDA,
	4095	+ .bus_flags = DRM_BUS_FLAG_DE_HIGH,
	4096	+ .connector_type = DRM_MODE_CONNECTOR_LVDS,
2711	4097	};
2712	4098
2713	4099	static const struct drm_display_mode tpk_f07a_0102_mode = {
..	..	@@ -2720,7 +4106,6 @@
2720	4106	.vsync_start = 480 + 10,
2721	4107	.vsync_end = 480 + 10 + 2,
2722	4108	.vtotal = 480 + 10 + 2 + 33,
2723		- .vrefresh = 60,
2724	4109	};
2725	4110
2726	4111	static const struct panel_desc tpk_f07a_0102 = {
..	..	@@ -2730,7 +4115,7 @@
2730	4115	.width = 152,
2731	4116	.height = 91,
2732	4117	},
2733		- .bus_flags = DRM_BUS_FLAG_PIXDATA_POSEDGE,
	4118	+ .bus_flags = DRM_BUS_FLAG_PIXDATA_DRIVE_POSEDGE,
2734	4119	};
2735	4120
2736	4121	static const struct drm_display_mode tpk_f10a_0102_mode = {
..	..	@@ -2743,7 +4128,6 @@
2743	4128	.vsync_start = 600 + 20,
2744	4129	.vsync_end = 600 + 20 + 5,
2745	4130	.vtotal = 600 + 20 + 5 + 25,
2746		- .vrefresh = 60,
2747	4131	};
2748	4132
2749	4133	static const struct panel_desc tpk_f10a_0102 = {
..	..	@@ -2778,6 +4162,7 @@
2778	4162	.height = 91,
2779	4163	},
2780	4164	.bus_format = MEDIA_BUS_FMT_RGB666_1X7X3_SPWG,
	4165	+ .connector_type = DRM_MODE_CONNECTOR_LVDS,
2781	4166	};
2782	4167
2783	4168	static const struct panel_desc urt_umsh_8596md_parallel = {
..	..	@@ -2791,6 +4176,31 @@
2791	4176	.bus_format = MEDIA_BUS_FMT_RGB666_1X18,
2792	4177	};
2793	4178
	4179	+static const struct drm_display_mode vl050_8048nt_c01_mode = {
	4180	+ .clock = 33333,
	4181	+ .hdisplay = 800,
	4182	+ .hsync_start = 800 + 210,
	4183	+ .hsync_end = 800 + 210 + 20,
	4184	+ .htotal = 800 + 210 + 20 + 46,
	4185	+ .vdisplay = 480,
	4186	+ .vsync_start = 480 + 22,
	4187	+ .vsync_end = 480 + 22 + 10,
	4188	+ .vtotal = 480 + 22 + 10 + 23,
	4189	+ .flags = DRM_MODE_FLAG_NHSYNC \| DRM_MODE_FLAG_NVSYNC,
	4190	+};
	4191	+
	4192	+static const struct panel_desc vl050_8048nt_c01 = {
	4193	+ .modes = &vl050_8048nt_c01_mode,
	4194	+ .num_modes = 1,
	4195	+ .bpc = 8,
	4196	+ .size = {
	4197	+ .width = 120,
	4198	+ .height = 76,
	4199	+ },
	4200	+ .bus_format = MEDIA_BUS_FMT_RGB888_1X24,
	4201	+ .bus_flags = DRM_BUS_FLAG_DE_HIGH \| DRM_BUS_FLAG_PIXDATA_SAMPLE_NEGEDGE,
	4202	+};
	4203	+
2794	4204	static const struct drm_display_mode winstar_wf35ltiacd_mode = {
2795	4205	.clock = 6410,
2796	4206	.hdisplay = 320,
..	..	@@ -2801,7 +4211,6 @@
2801	4211	.vsync_start = 240 + 4,
2802	4212	.vsync_end = 240 + 4 + 3,
2803	4213	.vtotal = 240 + 4 + 3 + 15,
2804		- .vrefresh = 60,
2805	4214	.flags = DRM_MODE_FLAG_NVSYNC \| DRM_MODE_FLAG_NHSYNC,
2806	4215	};
2807	4216
..	..	@@ -2816,17 +4225,48 @@
2816	4225	.bus_format = MEDIA_BUS_FMT_RGB888_1X24,
2817	4226	};
2818	4227
	4228	+static const struct drm_display_mode arm_rtsm_mode[] = {
	4229	+ {
	4230	+ .clock = 65000,
	4231	+ .hdisplay = 1024,
	4232	+ .hsync_start = 1024 + 24,
	4233	+ .hsync_end = 1024 + 24 + 136,
	4234	+ .htotal = 1024 + 24 + 136 + 160,
	4235	+ .vdisplay = 768,
	4236	+ .vsync_start = 768 + 3,
	4237	+ .vsync_end = 768 + 3 + 6,
	4238	+ .vtotal = 768 + 3 + 6 + 29,
	4239	+ .flags = DRM_MODE_FLAG_NVSYNC \| DRM_MODE_FLAG_NHSYNC,
	4240	+ },
	4241	+};
	4242	+
	4243	+static const struct panel_desc arm_rtsm = {
	4244	+ .modes = arm_rtsm_mode,
	4245	+ .num_modes = 1,
	4246	+ .bpc = 8,
	4247	+ .size = {
	4248	+ .width = 400,
	4249	+ .height = 300,
	4250	+ },
	4251	+ .bus_format = MEDIA_BUS_FMT_RGB888_1X24,
	4252	+};
	4253	+
2819	4254	static const struct of_device_id platform_of_match[] = {
2820	4255	{
2821	4256	.compatible = "simple-panel",
2822	4257	.data = NULL,
2823		-#ifndef CONFIG_DRM_PANEL_SIMPLE_OF_ONLY
	4258	+ }, {
	4259	+ .compatible = "ampire,am-1280800n3tzqw-t00h",
	4260	+ .data = &ampire_am_1280800n3tzqw_t00h,
2824	4261	}, {
2825	4262	.compatible = "ampire,am-480272h3tmqw-t01h",
2826	4263	.data = &ampire_am_480272h3tmqw_t01h,
2827	4264	}, {
2828	4265	.compatible = "ampire,am800480r3tmqwa1h",
2829	4266	.data = &ampire_am800480r3tmqwa1h,
	4267	+ }, {
	4268	+ .compatible = "arm,rtsm-display",
	4269	+ .data = &arm_rtsm,
2830	4270	}, {
2831	4271	.compatible = "armadeus,st0700-adapt",
2832	4272	.data = &armadeus_st0700_adapt,
..	..	@@ -2840,6 +4280,9 @@
2840	4280	.compatible = "auo,b101xtn01",
2841	4281	.data = &auo_b101xtn01,
2842	4282	}, {
	4283	+ .compatible = "auo,b116xa01",
	4284	+ .data = &auo_b116xak01,
	4285	+ }, {
2843	4286	.compatible = "auo,b116xw03",
2844	4287	.data = &auo_b116xw03,
2845	4288	}, {
..	..	@@ -2852,14 +4295,26 @@
2852	4295	.compatible = "auo,g070vvn01",
2853	4296	.data = &auo_g070vvn01,
2854	4297	}, {
	4298	+ .compatible = "auo,g101evn010",
	4299	+ .data = &auo_g101evn010,
	4300	+ }, {
2855	4301	.compatible = "auo,g104sn02",
2856	4302	.data = &auo_g104sn02,
	4303	+ }, {
	4304	+ .compatible = "auo,g121ean01",
	4305	+ .data = &auo_g121ean01,
2857	4306	}, {
2858	4307	.compatible = "auo,g133han01",
2859	4308	.data = &auo_g133han01,
2860	4309	}, {
	4310	+ .compatible = "auo,g156xtn01",
	4311	+ .data = &auo_g156xtn01,
	4312	+ }, {
2861	4313	.compatible = "auo,g185han01",
2862	4314	.data = &auo_g185han01,
	4315	+ }, {
	4316	+ .compatible = "auo,g190ean01",
	4317	+ .data = &auo_g190ean01,
2863	4318	}, {
2864	4319	.compatible = "auo,p320hvn03",
2865	4320	.data = &auo_p320hvn03,
..	..	@@ -2870,11 +4325,38 @@
2870	4325	.compatible = "avic,tm070ddh03",
2871	4326	.data = &avic_tm070ddh03,
2872	4327	}, {
	4328	+ .compatible = "bananapi,s070wv20-ct16",
	4329	+ .data = &bananapi_s070wv20_ct16,
	4330	+ }, {
2873	4331	.compatible = "boe,hv070wsa-100",
2874	4332	.data = &boe_hv070wsa
2875	4333	}, {
2876	4334	.compatible = "boe,nv101wxmn51",
2877	4335	.data = &boe_nv101wxmn51,
	4336	+ }, {
	4337	+ .compatible = "boe,nv133fhm-n61",
	4338	+ .data = &boe_nv133fhm_n61,
	4339	+ }, {
	4340	+ .compatible = "boe,nv133fhm-n62",
	4341	+ .data = &boe_nv133fhm_n61,
	4342	+ }, {
	4343	+ .compatible = "boe,nv140fhmn49",
	4344	+ .data = &boe_nv140fhmn49,
	4345	+ }, {
	4346	+ .compatible = "cdtech,s043wq26h-ct7",
	4347	+ .data = &cdtech_s043wq26h_ct7,
	4348	+ }, {
	4349	+ .compatible = "cdtech,s070pws19hp-fc21",
	4350	+ .data = &cdtech_s070pws19hp_fc21,
	4351	+ }, {
	4352	+ .compatible = "cdtech,s070swv29hg-dc44",
	4353	+ .data = &cdtech_s070swv29hg_dc44,
	4354	+ }, {
	4355	+ .compatible = "cdtech,s070wv95-ct16",
	4356	+ .data = &cdtech_s070wv95_ct16,
	4357	+ }, {
	4358	+ .compatible = "chefree,ch101olhlwh-002",
	4359	+ .data = &chefree_ch101olhlwh_002,
2878	4360	}, {
2879	4361	.compatible = "chunghwa,claa070wp03xg",
2880	4362	.data = &chunghwa_claa070wp03xg,
..	..	@@ -2891,6 +4373,18 @@
2891	4373	.compatible = "dlc,dlc0700yzg-1",
2892	4374	.data = &dlc_dlc0700yzg_1,
2893	4375	}, {
	4376	+ .compatible = "dlc,dlc1010gig",
	4377	+ .data = &dlc_dlc1010gig,
	4378	+ }, {
	4379	+ .compatible = "edt,et035012dm6",
	4380	+ .data = &edt_et035012dm6,
	4381	+ }, {
	4382	+ .compatible = "edt,etm043080dh6gp",
	4383	+ .data = &edt_etm043080dh6gp,
	4384	+ }, {
	4385	+ .compatible = "edt,etm0430g0dh6",
	4386	+ .data = &edt_etm0430g0dh6,
	4387	+ }, {
2894	4388	.compatible = "edt,et057090dhu",
2895	4389	.data = &edt_et057090dhu,
2896	4390	}, {
..	..	@@ -2906,11 +4400,23 @@
2906	4400	.compatible = "edt,etm0700g0edh6",
2907	4401	.data = &edt_etm0700g0bdh6,
2908	4402	}, {
	4403	+ .compatible = "evervision,vgg804821",
	4404	+ .data = &evervision_vgg804821,
	4405	+ }, {
2909	4406	.compatible = "foxlink,fl500wvr00-a0t",
2910	4407	.data = &foxlink_fl500wvr00_a0t,
2911	4408	}, {
	4409	+ .compatible = "frida,frd350h54004",
	4410	+ .data = &frida_frd350h54004,
	4411	+ }, {
	4412	+ .compatible = "friendlyarm,hd702e",
	4413	+ .data = &friendlyarm_hd702e,
	4414	+ }, {
2912	4415	.compatible = "giantplus,gpg482739qs5",
2913	4416	.data = &giantplus_gpg482739qs5
	4417	+ }, {
	4418	+ .compatible = "giantplus,gpm940b0",
	4419	+ .data = &giantplus_gpm940b0,
2914	4420	}, {
2915	4421	.compatible = "hannstar,hsd070pww1",
2916	4422	.data = &hannstar_hsd070pww1,
..	..	@@ -2945,17 +4451,32 @@
2945	4451	.compatible = "innolux,n156bge-l21",
2946	4452	.data = &innolux_n156bge_l21,
2947	4453	}, {
2948		- .compatible = "innolux,tv123wam",
2949		- .data = &innolux_tv123wam,
	4454	+ .compatible = "innolux,p120zdg-bf1",
	4455	+ .data = &innolux_p120zdg_bf1,
2950	4456	}, {
2951	4457	.compatible = "innolux,zj070na-01p",
2952	4458	.data = &innolux_zj070na_01p,
	4459	+ }, {
	4460	+ .compatible = "ivo,m133nwf4-r0",
	4461	+ .data = &ivo_m133nwf4_r0,
	4462	+ }, {
	4463	+ .compatible = "kingdisplay,kd116n21-30nv-a010",
	4464	+ .data = &kingdisplay_kd116n21_30nv_a010,
	4465	+ }, {
	4466	+ .compatible = "koe,tx14d24vm1bpa",
	4467	+ .data = &koe_tx14d24vm1bpa,
	4468	+ }, {
	4469	+ .compatible = "koe,tx26d202vm0bwa",
	4470	+ .data = &koe_tx26d202vm0bwa,
2953	4471	}, {
2954	4472	.compatible = "koe,tx31d200vm0baa",
2955	4473	.data = &koe_tx31d200vm0baa,
2956	4474	}, {
2957	4475	.compatible = "kyo,tcg121xglp",
2958	4476	.data = &kyo_tcg121xglp,
	4477	+ }, {
	4478	+ .compatible = "lemaker,bl035-rgb-002",
	4479	+ .data = &lemaker_bl035_rgb_002,
2959	4480	}, {
2960	4481	.compatible = "lg,lb070wv8",
2961	4482	.data = &lg_lb070wv8,
..	..	@@ -2972,6 +4493,18 @@
2972	4493	.compatible = "lg,lp129qe",
2973	4494	.data = &lg_lp129qe,
2974	4495	}, {
	4496	+ .compatible = "logicpd,type28",
	4497	+ .data = &logicpd_type_28,
	4498	+ }, {
	4499	+ .compatible = "logictechno,lt161010-2nhc",
	4500	+ .data = &logictechno_lt161010_2nh,
	4501	+ }, {
	4502	+ .compatible = "logictechno,lt161010-2nhr",
	4503	+ .data = &logictechno_lt161010_2nh,
	4504	+ }, {
	4505	+ .compatible = "logictechno,lt170410-2whc",
	4506	+ .data = &logictechno_lt170410_2whc,
	4507	+ }, {
2975	4508	.compatible = "mitsubishi,aa070mc01-ca1",
2976	4509	.data = &mitsubishi_aa070mc01,
2977	4510	}, {
..	..	@@ -2983,6 +4516,9 @@
2983	4516	}, {
2984	4517	.compatible = "netron-dy,e231732",
2985	4518	.data = &netron_dy_e231732,
	4519	+ }, {
	4520	+ .compatible = "neweast,wjfh116008a",
	4521	+ .data = &neweast_wjfh116008a,
2986	4522	}, {
2987	4523	.compatible = "newhaven,nhd-4.3-480272ef-atxl",
2988	4524	.data = &newhaven_nhd_43_480272ef_atxl,
..	..	@@ -3002,14 +4538,32 @@
3002	4538	.compatible = "ontat,yx700wv03",
3003	4539	.data = &ontat_yx700wv03,
3004	4540	}, {
	4541	+ .compatible = "ortustech,com37h3m05dtc",
	4542	+ .data = &ortustech_com37h3m,
	4543	+ }, {
	4544	+ .compatible = "ortustech,com37h3m99dtc",
	4545	+ .data = &ortustech_com37h3m,
	4546	+ }, {
3005	4547	.compatible = "ortustech,com43h4m85ulc",
3006	4548	.data = &ortustech_com43h4m85ulc,
	4549	+ }, {
	4550	+ .compatible = "osddisplays,osd070t1718-19ts",
	4551	+ .data = &osddisplays_osd070t1718_19ts,
	4552	+ }, {
	4553	+ .compatible = "pda,91-00156-a0",
	4554	+ .data = &pda_91_00156_a0,
	4555	+ }, {
	4556	+ .compatible = "powertip,ph800480t013-idf02",
	4557	+ .data = &powertip_ph800480t013_idf02,
3007	4558	}, {
3008	4559	.compatible = "qiaodian,qd43003c0-40",
3009	4560	.data = &qd43003c0_40,
3010	4561	}, {
3011	4562	.compatible = "rocktech,rk070er9427",
3012	4563	.data = &rocktech_rk070er9427,
	4564	+ }, {
	4565	+ .compatible = "rocktech,rk101ii01d-ct",
	4566	+ .data = &rocktech_rk101ii01d_ct,
3013	4567	}, {
3014	4568	.compatible = "samsung,lsn122dl01-c01",
3015	4569	.data = &samsung_lsn122dl01_c01,
..	..	@@ -3020,8 +4574,17 @@
3020	4574	.compatible = "samsung,ltn140at29-301",
3021	4575	.data = &samsung_ltn140at29_301,
3022	4576	}, {
	4577	+ .compatible = "satoz,sat050at40h12r2",
	4578	+ .data = &satoz_sat050at40h12r2,
	4579	+ }, {
	4580	+ .compatible = "sharp,ld-d5116z01b",
	4581	+ .data = &sharp_ld_d5116z01b,
	4582	+ }, {
3023	4583	.compatible = "sharp,lq035q7db03",
3024	4584	.data = &sharp_lq035q7db03,
	4585	+ }, {
	4586	+ .compatible = "sharp,lq070y3dg3b",
	4587	+ .data = &sharp_lq070y3dg3b,
3025	4588	}, {
3026	4589	.compatible = "sharp,lq101k1ly04",
3027	4590	.data = &sharp_lq101k1ly04,
..	..	@@ -3029,20 +4592,35 @@
3029	4592	.compatible = "sharp,lq123p1jx31",
3030	4593	.data = &sharp_lq123p1jx31,
3031	4594	}, {
3032		- .compatible = "sharp,lq150x1lg11",
3033		- .data = &sharp_lq150x1lg11,
	4595	+ .compatible = "sharp,ls020b1dd01d",
	4596	+ .data = &sharp_ls020b1dd01d,
3034	4597	}, {
3035	4598	.compatible = "shelly,sca07010-bfn-lnn",
3036	4599	.data = &shelly_sca07010_bfn_lnn,
3037	4600	}, {
	4601	+ .compatible = "starry,kr070pe2t",
	4602	+ .data = &starry_kr070pe2t,
	4603	+ }, {
3038	4604	.compatible = "starry,kr122ea0sra",
3039	4605	.data = &starry_kr122ea0sra,
	4606	+ }, {
	4607	+ .compatible = "tfc,s9700rtwv43tr-01b",
	4608	+ .data = &tfc_s9700rtwv43tr_01b,
3040	4609	}, {
3041	4610	.compatible = "tianma,tm070jdhg30",
3042	4611	.data = &tianma_tm070jdhg30,
3043	4612	}, {
	4613	+ .compatible = "tianma,tm070jvhg33",
	4614	+ .data = &tianma_tm070jvhg33,
	4615	+ }, {
3044	4616	.compatible = "tianma,tm070rvhg71",
3045	4617	.data = &tianma_tm070rvhg71,
	4618	+ }, {
	4619	+ .compatible = "ti,nspire-cx-lcd-panel",
	4620	+ .data = &ti_nspire_cx_lcd_panel,
	4621	+ }, {
	4622	+ .compatible = "ti,nspire-classic-lcd-panel",
	4623	+ .data = &ti_nspire_classic_lcd_panel,
3046	4624	}, {
3047	4625	.compatible = "toshiba,lt089ac29000",
3048	4626	.data = &toshiba_lt089ac29000,
..	..	@@ -3071,35 +4649,74 @@
3071	4649	.compatible = "urt,umsh-8596md-20t",
3072	4650	.data = &urt_umsh_8596md_parallel,
3073	4651	}, {
	4652	+ .compatible = "vxt,vl050-8048nt-c01",
	4653	+ .data = &vl050_8048nt_c01,
	4654	+ }, {
3074	4655	.compatible = "winstar,wf35ltiacd",
3075	4656	.data = &winstar_wf35ltiacd,
3076		-#endif /* !CONFIG_DRM_PANEL_SIMPLE_OF_ONLY */
	4657	+ }, {
	4658	+ /* Must be the last entry */
	4659	+ .compatible = "panel-dpi",
	4660	+ .data = &panel_dpi,
3077	4661	}, {
3078	4662	/* sentinel */
3079	4663	}
3080	4664	};
3081	4665	MODULE_DEVICE_TABLE(of, platform_of_match);
3082	4666
	4667	+static bool of_child_node_is_present(const struct device_node *node,
	4668	+ const char *name)
	4669	+{
	4670	+ struct device_node *child;
	4671	+
	4672	+ child = of_get_child_by_name(node, name);
	4673	+ of_node_put(child);
	4674	+
	4675	+ return !!child;
	4676	+}
	4677	+
3083	4678	static int panel_simple_of_get_desc_data(struct device *dev,
3084	4679	struct panel_desc *desc)
3085	4680	{
3086	4681	struct device_node *np = dev->of_node;
3087		- struct drm_display_mode *mode;
3088	4682	u32 bus_flags;
3089	4683	const void *data;
3090	4684	int len;
3091	4685	int err;
3092	4686
3093		- mode = devm_kzalloc(dev, sizeof(*mode), GFP_KERNEL);
3094		- if (!mode)
3095		- return -ENOMEM;
	4687	+ if (of_child_node_is_present(np, "display-timings")) {
	4688	+ struct drm_display_mode *mode;
3096	4689
3097		- err = of_get_drm_display_mode(np, mode, &bus_flags, OF_USE_NATIVE_MODE);
3098		- if (!err) {
3099		- desc->modes = mode;
3100		- desc->num_modes = 1;
3101		- desc->bus_flags = bus_flags;
	4690	+ mode = devm_kzalloc(dev, sizeof(*mode), GFP_KERNEL);
	4691	+ if (!mode)
	4692	+ return -ENOMEM;
3102	4693
	4694	+ if (!of_get_drm_display_mode(np, mode, &bus_flags,
	4695	+ OF_USE_NATIVE_MODE)) {
	4696	+ desc->modes = mode;
	4697	+ desc->num_modes = 1;
	4698	+ desc->bus_flags = bus_flags;
	4699	+ }
	4700	+ } else if (of_child_node_is_present(np, "panel-timing")) {
	4701	+ struct display_timing *timing;
	4702	+ struct videomode vm;
	4703	+
	4704	+ timing = devm_kzalloc(dev, sizeof(*timing), GFP_KERNEL);
	4705	+ if (!timing)
	4706	+ return -ENOMEM;
	4707	+
	4708	+ if (!of_get_display_timing(np, "panel-timing", timing)) {
	4709	+ desc->timings = timing;
	4710	+ desc->num_timings = 1;
	4711	+
	4712	+ bus_flags = 0;
	4713	+ vm.flags = timing->flags;
	4714	+ drm_bus_flags_from_videomode(&vm, &bus_flags);
	4715	+ desc->bus_flags = bus_flags;
	4716	+ }
	4717	+ }
	4718	+
	4719	+ if (desc->num_modes \|\| desc->num_timings) {
3103	4720	of_property_read_u32(np, "bpc", &desc->bpc);
3104	4721	of_property_read_u32(np, "bus-format", &desc->bus_format);
3105	4722	of_property_read_u32(np, "width-mm", &desc->size.width);
..	..	@@ -3213,7 +4830,6 @@
3213	4830	.vsync_start = 1920 + 9,
3214	4831	.vsync_end = 1920 + 9 + 2,
3215	4832	.vtotal = 1920 + 9 + 2 + 8,
3216		- .vrefresh = 60,
3217	4833	};
3218	4834
3219	4835	static const struct panel_desc_dsi auo_b080uan01 = {
..	..	@@ -3225,6 +4841,7 @@
3225	4841	.width = 108,
3226	4842	.height = 272,
3227	4843	},
	4844	+ .connector_type = DRM_MODE_CONNECTOR_DSI,
3228	4845	},
3229	4846	.flags = MIPI_DSI_MODE_VIDEO \| MIPI_DSI_CLOCK_NON_CONTINUOUS,
3230	4847	.format = MIPI_DSI_FMT_RGB888,
..	..	@@ -3241,7 +4858,6 @@
3241	4858	.vsync_start = 1920 + 21,
3242	4859	.vsync_end = 1920 + 21 + 3,
3243	4860	.vtotal = 1920 + 21 + 3 + 18,
3244		- .vrefresh = 60,
3245	4861	.flags = DRM_MODE_FLAG_NVSYNC \| DRM_MODE_FLAG_NHSYNC,
3246	4862	};
3247	4863
..	..	@@ -3253,6 +4869,7 @@
3253	4869	.width = 107,
3254	4870	.height = 172,
3255	4871	},
	4872	+ .connector_type = DRM_MODE_CONNECTOR_DSI,
3256	4873	},
3257	4874	.flags = MIPI_DSI_MODE_VIDEO \|
3258	4875	MIPI_DSI_MODE_VIDEO_BURST \|
..	..	@@ -3271,7 +4888,6 @@
3271	4888	.vsync_start = 1280 + 28,
3272	4889	.vsync_end = 1280 + 28 + 1,
3273	4890	.vtotal = 1280 + 28 + 1 + 14,
3274		- .vrefresh = 60,
3275	4891	};
3276	4892
3277	4893	static const struct panel_desc_dsi lg_ld070wx3_sl01 = {
..	..	@@ -3283,6 +4899,7 @@
3283	4899	.width = 94,
3284	4900	.height = 151,
3285	4901	},
	4902	+ .connector_type = DRM_MODE_CONNECTOR_DSI,
3286	4903	},
3287	4904	.flags = MIPI_DSI_MODE_VIDEO \| MIPI_DSI_CLOCK_NON_CONTINUOUS,
3288	4905	.format = MIPI_DSI_FMT_RGB888,
..	..	@@ -3299,7 +4916,6 @@
3299	4916	.vsync_start = 1280 + 8,
3300	4917	.vsync_end = 1280 + 8 + 4,
3301	4918	.vtotal = 1280 + 8 + 4 + 12,
3302		- .vrefresh = 60,
3303	4919	};
3304	4920
3305	4921	static const struct panel_desc_dsi lg_lh500wx1_sd03 = {
..	..	@@ -3311,6 +4927,7 @@
3311	4927	.width = 62,
3312	4928	.height = 110,
3313	4929	},
	4930	+ .connector_type = DRM_MODE_CONNECTOR_DSI,
3314	4931	},
3315	4932	.flags = MIPI_DSI_MODE_VIDEO,
3316	4933	.format = MIPI_DSI_FMT_RGB888,
..	..	@@ -3327,7 +4944,6 @@
3327	4944	.vsync_start = 1200 + 17,
3328	4945	.vsync_end = 1200 + 17 + 2,
3329	4946	.vtotal = 1200 + 17 + 2 + 16,
3330		- .vrefresh = 60,
3331	4947	};
3332	4948
3333	4949	static const struct panel_desc_dsi panasonic_vvx10f004b00 = {
..	..	@@ -3339,9 +4955,69 @@
3339	4955	.width = 217,
3340	4956	.height = 136,
3341	4957	},
	4958	+ .connector_type = DRM_MODE_CONNECTOR_DSI,
3342	4959	},
3343	4960	.flags = MIPI_DSI_MODE_VIDEO \| MIPI_DSI_MODE_VIDEO_SYNC_PULSE \|
3344	4961	MIPI_DSI_CLOCK_NON_CONTINUOUS,
	4962	+ .format = MIPI_DSI_FMT_RGB888,
	4963	+ .lanes = 4,
	4964	+};
	4965	+
	4966	+static const struct drm_display_mode lg_acx467akm_7_mode = {
	4967	+ .clock = 150000,
	4968	+ .hdisplay = 1080,
	4969	+ .hsync_start = 1080 + 2,
	4970	+ .hsync_end = 1080 + 2 + 2,
	4971	+ .htotal = 1080 + 2 + 2 + 2,
	4972	+ .vdisplay = 1920,
	4973	+ .vsync_start = 1920 + 2,
	4974	+ .vsync_end = 1920 + 2 + 2,
	4975	+ .vtotal = 1920 + 2 + 2 + 2,
	4976	+};
	4977	+
	4978	+static const struct panel_desc_dsi lg_acx467akm_7 = {
	4979	+ .desc = {
	4980	+ .modes = &lg_acx467akm_7_mode,
	4981	+ .num_modes = 1,
	4982	+ .bpc = 8,
	4983	+ .size = {
	4984	+ .width = 62,
	4985	+ .height = 110,
	4986	+ },
	4987	+ .connector_type = DRM_MODE_CONNECTOR_DSI,
	4988	+ },
	4989	+ .flags = 0,
	4990	+ .format = MIPI_DSI_FMT_RGB888,
	4991	+ .lanes = 4,
	4992	+};
	4993	+
	4994	+static const struct drm_display_mode osd101t2045_53ts_mode = {
	4995	+ .clock = 154500,
	4996	+ .hdisplay = 1920,
	4997	+ .hsync_start = 1920 + 112,
	4998	+ .hsync_end = 1920 + 112 + 16,
	4999	+ .htotal = 1920 + 112 + 16 + 32,
	5000	+ .vdisplay = 1200,
	5001	+ .vsync_start = 1200 + 16,
	5002	+ .vsync_end = 1200 + 16 + 2,
	5003	+ .vtotal = 1200 + 16 + 2 + 16,
	5004	+ .flags = DRM_MODE_FLAG_NHSYNC \| DRM_MODE_FLAG_NVSYNC,
	5005	+};
	5006	+
	5007	+static const struct panel_desc_dsi osd101t2045_53ts = {
	5008	+ .desc = {
	5009	+ .modes = &osd101t2045_53ts_mode,
	5010	+ .num_modes = 1,
	5011	+ .bpc = 8,
	5012	+ .size = {
	5013	+ .width = 217,
	5014	+ .height = 136,
	5015	+ },
	5016	+ .connector_type = DRM_MODE_CONNECTOR_DSI,
	5017	+ },
	5018	+ .flags = MIPI_DSI_MODE_VIDEO \| MIPI_DSI_MODE_VIDEO_BURST \|
	5019	+ MIPI_DSI_MODE_VIDEO_SYNC_PULSE \|
	5020	+ MIPI_DSI_MODE_EOT_PACKET,
3345	5021	.format = MIPI_DSI_FMT_RGB888,
3346	5022	.lanes = 4,
3347	5023	};
..	..	@@ -3350,7 +5026,6 @@
3350	5026	{
3351	5027	.compatible = "simple-panel-dsi",
3352	5028	.data = NULL,
3353		-#ifndef CONFIG_DRM_PANEL_SIMPLE_OF_ONLY
3354	5029	}, {
3355	5030	.compatible = "auo,b080uan01",
3356	5031	.data = &auo_b080uan01
..	..	@@ -3366,7 +5041,12 @@
3366	5041	}, {
3367	5042	.compatible = "panasonic,vvx10f004b00",
3368	5043	.data = &panasonic_vvx10f004b00
3369		-#endif /* !CONFIG_DRM_PANEL_SIMPLE_OF_ONLY */
	5044	+ }, {
	5045	+ .compatible = "lg,acx467akm-7",
	5046	+ .data = &lg_acx467akm_7
	5047	+ }, {
	5048	+ .compatible = "osddisplays,osd101t2045-53ts",
	5049	+ .data = &osd101t2045_53ts
3370	5050	}, {
3371	5051	/* sentinel */
3372	5052	}
..	..	@@ -3428,6 +5108,26 @@
3428	5108	panel = dev_get_drvdata(dev);
3429	5109	panel->dsi = dsi;
3430	5110
	5111	+ if (!panel->base.backlight) {
	5112	+ struct backlight_properties props;
	5113	+
	5114	+ memset(&props, 0, sizeof(props));
	5115	+ props.type = BACKLIGHT_RAW;
	5116	+ props.brightness = 255;
	5117	+ props.max_brightness = 255;
	5118	+
	5119	+ panel->base.backlight =
	5120	+ devm_backlight_device_register(dev, "dcs-backlight",
	5121	+ dev, panel, &dcs_bl_ops,
	5122	+ &props);
	5123	+ if (IS_ERR(panel->base.backlight)) {
	5124	+ err = PTR_ERR(panel->base.backlight);
	5125	+ dev_err(dev, "failed to register dcs backlight: %d\n",
	5126	+ err);
	5127	+ return err;
	5128	+ }
	5129	+ }
	5130	+
3431	5131	dsi->mode_flags = desc->flags;
3432	5132	dsi->format = desc->format;
3433	5133	dsi->lanes = desc->lanes;
..	..	@@ -3468,6 +5168,113 @@
3468	5168	.shutdown = panel_simple_dsi_shutdown,
3469	5169	};
3470	5170
	5171	+static int panel_simple_spi_read(struct device dev, const u8 cmd, u8 data)
	5172	+{
	5173	+ return 0;
	5174	+}
	5175	+
	5176	+static int panel_simple_spi_write_word(struct device *dev, u16 data)
	5177	+{
	5178	+ struct spi_device *spi = to_spi_device(dev);
	5179	+ struct spi_transfer xfer = {
	5180	+ .len = 2,
	5181	+ .tx_buf = &data,
	5182	+ };
	5183	+ struct spi_message msg;
	5184	+
	5185	+ spi_message_init(&msg);
	5186	+ spi_message_add_tail(&xfer, &msg);
	5187	+
	5188	+ return spi_sync(spi, &msg);
	5189	+}
	5190	+
	5191	+static int panel_simple_spi_write(struct device dev, const u8 data, size_t len, u8 type)
	5192	+{
	5193	+ int ret = 0;
	5194	+ int i;
	5195	+ u16 mask = type ? 0x100 : 0;
	5196	+
	5197	+ for (i = 0; i < len; i++) {
	5198	+ ret = panel_simple_spi_write_word(dev, *data \| mask);
	5199	+ if (ret) {
	5200	+ dev_err(dev, "failed to write spi seq: %*ph\n", (int)len, data);
	5201	+ return ret;
	5202	+ }
	5203	+ data++;
	5204	+ }
	5205	+
	5206	+ return ret;
	5207	+}
	5208	+
	5209	+static const struct of_device_id panel_simple_spi_of_match[] = {
	5210	+ { .compatible = "simple-panel-spi", .data = NULL },
	5211	+ { /* sentinel */ }
	5212	+};
	5213	+MODULE_DEVICE_TABLE(of, panel_simple_spi_of_match);
	5214	+
	5215	+static int panel_simple_spi_probe(struct spi_device *spi)
	5216	+{
	5217	+ struct device *dev = &spi->dev;
	5218	+ const struct of_device_id *id;
	5219	+ const struct panel_desc *desc;
	5220	+ struct panel_desc *d;
	5221	+ int ret;
	5222	+
	5223	+ id = of_match_node(panel_simple_spi_of_match, dev->of_node);
	5224	+ if (!id)
	5225	+ return -ENODEV;
	5226	+
	5227	+ if (!id->data) {
	5228	+ d = devm_kzalloc(dev, sizeof(*d), GFP_KERNEL);
	5229	+ if (!d)
	5230	+ return -ENOMEM;
	5231	+
	5232	+ ret = panel_simple_of_get_desc_data(dev, d);
	5233	+ if (ret) {
	5234	+ dev_err(dev, "failed to get desc data: %d\n", ret);
	5235	+ return ret;
	5236	+ }
	5237	+
	5238	+ d->spi_write = panel_simple_spi_write;
	5239	+ d->spi_read = panel_simple_spi_read;
	5240	+ d->cmd_type = CMD_TYPE_SPI;
	5241	+ }
	5242	+ desc = id->data ? id->data : d;
	5243	+
	5244	+ /*
	5245	+ * Set spi to 3 lines and 9bits/word mode.
	5246	+ */
	5247	+ spi->bits_per_word = 9;
	5248	+ spi->mode = SPI_MODE_3;
	5249	+ ret = spi_setup(spi);
	5250	+ if (ret < 0) {
	5251	+ dev_err(dev, "spi setup failed.\n");
	5252	+ return ret;
	5253	+ }
	5254	+
	5255	+ return panel_simple_probe(dev, desc);
	5256	+}
	5257	+
	5258	+static int panel_simple_spi_remove(struct spi_device *spi)
	5259	+{
	5260	+ return panel_simple_remove(&spi->dev);
	5261	+}
	5262	+
	5263	+static void panel_simple_spi_shutdown(struct spi_device *spi)
	5264	+{
	5265	+ panel_simple_shutdown(&spi->dev);
	5266	+}
	5267	+
	5268	+static struct spi_driver panel_simple_spi_driver = {
	5269	+ .driver = {
	5270	+ .name = "panel-simple-spi",
	5271	+ .of_match_table = panel_simple_spi_of_match,
	5272	+ },
	5273	+ .probe = panel_simple_spi_probe,
	5274	+ .remove = panel_simple_spi_remove,
	5275	+ .shutdown = panel_simple_spi_shutdown,
	5276	+};
	5277	+
3471	5278	static int __init panel_simple_init(void)
3472	5279	{
3473	5280	int err;
..	..	@@ -3475,6 +5282,12 @@
3475	5282	err = platform_driver_register(&panel_simple_platform_driver);
3476	5283	if (err < 0)
3477	5284	return err;
	5285	+
	5286	+ if (IS_ENABLED(CONFIG_SPI_MASTER)) {
	5287	+ err = spi_register_driver(&panel_simple_spi_driver);
	5288	+ if (err < 0)
	5289	+ return err;
	5290	+ }
3478	5291
3479	5292	if (IS_ENABLED(CONFIG_DRM_MIPI_DSI)) {
3480	5293	err = mipi_dsi_driver_register(&panel_simple_dsi_driver);
..	..	@@ -3484,17 +5297,16 @@
3484	5297
3485	5298	return 0;
3486	5299	}
3487		-#ifdef CONFIG_ROCKCHIP_THUNDER_BOOT
3488		-rootfs_initcall(panel_simple_init);
3489		-#else
3490	5300	module_init(panel_simple_init);
3491		-#endif
3492	5301
3493	5302	static void __exit panel_simple_exit(void)
3494	5303	{
3495	5304	if (IS_ENABLED(CONFIG_DRM_MIPI_DSI))
3496	5305	mipi_dsi_driver_unregister(&panel_simple_dsi_driver);
3497	5306
	5307	+ if (IS_ENABLED(CONFIG_SPI_MASTER))
	5308	+ spi_unregister_driver(&panel_simple_spi_driver);
	5309	+
3498	5310	platform_driver_unregister(&panel_simple_platform_driver);
3499	5311	}
3500	5312	module_exit(panel_simple_exit);