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2024-01-05 071106ecf68c401173c58808b1cf5f68cc50d390 
 kernel/drivers/gpu/drm/msm/edp/edp_ctrl.c
....@@ -1,14 +1,6 @@
1
+// SPDX-License-Identifier: GPL-2.0-only
12 /*
23  * Copyright (c) 2014-2015, The Linux Foundation. All rights reserved.
3
- *
4
- * This program is free software; you can redistribute it and/or modify
5
- * it under the terms of the GNU General Public License version 2 and
6
- * only version 2 as published by the Free Software Foundation.
7
- *
8
- * This program is distributed in the hope that it will be useful,
9
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
10
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
11
- * GNU General Public License for more details.
124  */
135 
146 #include <linux/clk.h>
....@@ -97,7 +89,6 @@
9789 	/* edid raw data */
9890 	struct edid *edid;
9991 
100
-	struct drm_dp_link dp_link;
10192 	struct drm_dp_aux *drm_aux;
10293 
10394 	/* dpcd raw data */
....@@ -411,7 +402,7 @@
411402 	u32 prate;
412403 	u32 lrate;
413404 	u32 bpp;
414
-	u8 max_lane = ctrl->dp_link.num_lanes;
405
+	u8 max_lane = drm_dp_max_lane_count(ctrl->dpcd);
415406 	u8 lane;
416407 
417408 	prate = ctrl->pixel_rate;
....@@ -421,7 +412,7 @@
421412 	 * By default, use the maximum link rate and minimum lane count,
422413 	 * so that we can do rate down shift during link training.
423414 	 */
424
-	ctrl->link_rate = drm_dp_link_rate_to_bw_code(ctrl->dp_link.rate);
415
+	ctrl->link_rate = ctrl->dpcd[DP_MAX_LINK_RATE];
425416 
426417 	prate *= bpp;
427418 	prate /= 8; /* in kByte */
....@@ -447,7 +438,7 @@
447438 
448439 	data = EDP_CONFIGURATION_CTRL_LANES(ctrl->lane_cnt - 1);
449440 
450
-	if (ctrl->dp_link.capabilities & DP_LINK_CAP_ENHANCED_FRAMING)
441
+	if (drm_dp_enhanced_frame_cap(ctrl->dpcd))
451442 		data |= EDP_CONFIGURATION_CTRL_ENHANCED_FRAMING;
452443 
453444 	depth = EDP_6BIT;
....@@ -709,7 +700,7 @@
709700 
710701 	rate = ctrl->link_rate;
711702 	lane = ctrl->lane_cnt;
712
-	max_lane = ctrl->dp_link.num_lanes;
703
+	max_lane = drm_dp_max_lane_count(ctrl->dpcd);
713704 
714705 	bpp = ctrl->color_depth * 3;
715706 	prate = ctrl->pixel_rate;
....@@ -759,18 +750,22 @@
759750 
760751 static int edp_do_link_train(struct edp_ctrl *ctrl)
761752 {
753
+	u8 values[2];
762754 	int ret;
763
-	struct drm_dp_link dp_link;
764755 
765756 	DBG("");
766757 	/*
767758 	 * Set the current link rate and lane cnt to panel. They may have been
768759 	 * adjusted and the values are different from them in DPCD CAP
769760 	 */
770
-	dp_link.num_lanes = ctrl->lane_cnt;
771
-	dp_link.rate = drm_dp_bw_code_to_link_rate(ctrl->link_rate);
772
-	dp_link.capabilities = ctrl->dp_link.capabilities;
773
-	if (drm_dp_link_configure(ctrl->drm_aux, &dp_link) < 0)
761
+	values[0] = ctrl->lane_cnt;
762
+	values[1] = ctrl->link_rate;
763
+
764
+	if (drm_dp_enhanced_frame_cap(ctrl->dpcd))
765
+		values[1] |= DP_LANE_COUNT_ENHANCED_FRAME_EN;
766
+
767
+	if (drm_dp_dpcd_write(ctrl->drm_aux, DP_LINK_BW_SET, values,
768
+			      sizeof(values)) < 0)
774769 		return EDP_TRAIN_FAIL;
775770 
776771 	ctrl->v_level = 0; /* start from default level */
....@@ -960,6 +955,7 @@
960955 {
961956 	struct edp_ctrl *ctrl = container_of(
962957 				work, struct edp_ctrl, on_work);
958
+	u8 value;
963959 	int ret;
964960 
965961 	mutex_lock(&ctrl->dev_mutex);
....@@ -973,9 +969,27 @@
973969 	edp_ctrl_link_enable(ctrl, 1);
974970 
975971 	edp_ctrl_irq_enable(ctrl, 1);
976
-	ret = drm_dp_link_power_up(ctrl->drm_aux, &ctrl->dp_link);
977
-	if (ret)
978
-		goto fail;
972
+
973
+	/* DP_SET_POWER register is only available on DPCD v1.1 and later */
974
+	if (ctrl->dpcd[DP_DPCD_REV] >= 0x11) {
975
+		ret = drm_dp_dpcd_readb(ctrl->drm_aux, DP_SET_POWER, &value);
976
+		if (ret < 0)
977
+			goto fail;
978
+
979
+		value &= ~DP_SET_POWER_MASK;
980
+		value |= DP_SET_POWER_D0;
981
+
982
+		ret = drm_dp_dpcd_writeb(ctrl->drm_aux, DP_SET_POWER, value);
983
+		if (ret < 0)
984
+			goto fail;
985
+
986
+		/*
987
+		 * According to the DP 1.1 specification, a "Sink Device must
988
+		 * exit the power saving state within 1 ms" (Section 2.5.3.1,
989
+		 * Table 5-52, "Sink Control Field" (register 0x600).
990
+		 */
991
+		usleep_range(1000, 2000);
992
+	}
979993 
980994 	ctrl->power_on = true;
981995 
....@@ -1019,7 +1033,19 @@
10191033 
10201034 	edp_state_ctrl(ctrl, 0);
10211035 
1022
-	drm_dp_link_power_down(ctrl->drm_aux, &ctrl->dp_link);
1036
+	/* DP_SET_POWER register is only available on DPCD v1.1 and later */
1037
+	if (ctrl->dpcd[DP_DPCD_REV] >= 0x11) {
1038
+		u8 value;
1039
+		int ret;
1040
+
1041
+		ret = drm_dp_dpcd_readb(ctrl->drm_aux, DP_SET_POWER, &value);
1042
+		if (ret > 0) {
1043
+			value &= ~DP_SET_POWER_MASK;
1044
+			value |= DP_SET_POWER_D3;
1045
+
1046
+			drm_dp_dpcd_writeb(ctrl->drm_aux, DP_SET_POWER, value);
1047
+		}
1048
+	}
10231049 
10241050 	edp_ctrl_irq_enable(ctrl, 0);
10251051 
....@@ -1234,14 +1260,8 @@
12341260 		edp_ctrl_irq_enable(ctrl, 1);
12351261 	}
12361262 
1237
-	ret = drm_dp_link_probe(ctrl->drm_aux, &ctrl->dp_link);
1238
-	if (ret) {
1239
-		pr_err("%s: read dpcd cap failed, %d\n", __func__, ret);
1240
-		goto disable_ret;
1241
-	}
1242
-
12431263 	/* Initialize link rate as panel max link rate */
1244
-	ctrl->link_rate = drm_dp_link_rate_to_bw_code(ctrl->dp_link.rate);
1264
+	ctrl->link_rate = ctrl->dpcd[DP_MAX_LINK_RATE];
12451265 
12461266 	ctrl->edid = drm_get_edid(connector, &ctrl->drm_aux->ddc);
12471267 	if (!ctrl->edid) {