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2024-01-05 071106ecf68c401173c58808b1cf5f68cc50d390 
 kernel/drivers/gpu/drm/mediatek/mtk_drm_ddp.c
....@@ -1,14 +1,6 @@
1
+// SPDX-License-Identifier: GPL-2.0-only
12 /*
23  * Copyright (c) 2015 MediaTek Inc.
3
- *
4
- * This program is free software; you can redistribute it and/or modify
5
- * it under the terms of the GNU General Public License version 2 as
6
- * published by the Free Software Foundation.
7
- *
8
- * This program is distributed in the hope that it will be useful,
9
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
10
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
11
- * GNU General Public License for more details.
124  */
135 
146 #include <linux/clk.h>
....@@ -21,31 +13,15 @@
2113 #include "mtk_drm_ddp.h"
2214 #include "mtk_drm_ddp_comp.h"
2315 
24
-#define DISP_REG_CONFIG_DISP_OVL0_MOUT_EN	0x040
25
-#define DISP_REG_CONFIG_DISP_OVL1_MOUT_EN	0x044
26
-#define DISP_REG_CONFIG_DISP_OD_MOUT_EN		0x048
27
-#define DISP_REG_CONFIG_DISP_GAMMA_MOUT_EN	0x04c
28
-#define DISP_REG_CONFIG_DISP_UFOE_MOUT_EN	0x050
29
-#define DISP_REG_CONFIG_DISP_COLOR0_SEL_IN	0x084
30
-#define DISP_REG_CONFIG_DISP_COLOR1_SEL_IN	0x088
31
-#define DISP_REG_CONFIG_DSIE_SEL_IN		0x0a4
32
-#define DISP_REG_CONFIG_DSIO_SEL_IN		0x0a8
33
-#define DISP_REG_CONFIG_DPI_SEL_IN		0x0ac
34
-#define DISP_REG_CONFIG_DISP_RDMA2_SOUT		0x0b8
35
-#define DISP_REG_CONFIG_DISP_RDMA0_SOUT_EN	0x0c4
36
-#define DISP_REG_CONFIG_DISP_RDMA1_SOUT_EN	0x0c8
37
-#define DISP_REG_CONFIG_MMSYS_CG_CON0		0x100
16
+#define MT2701_DISP_MUTEX0_MOD0			0x2c
17
+#define MT2701_DISP_MUTEX0_SOF0			0x30
3818 
39
-#define DISP_REG_CONFIG_DISP_OVL_MOUT_EN	0x030
40
-#define DISP_REG_CONFIG_OUT_SEL			0x04c
41
-#define DISP_REG_CONFIG_DSI_SEL			0x050
42
-
43
-#define DISP_REG_MUTEX_EN(n)	(0x20 + 0x20 * (n))
44
-#define DISP_REG_MUTEX(n)	(0x24 + 0x20 * (n))
45
-#define DISP_REG_MUTEX_RST(n)	(0x28 + 0x20 * (n))
46
-#define DISP_REG_MUTEX_MOD(n)	(0x2c + 0x20 * (n))
47
-#define DISP_REG_MUTEX_SOF(n)	(0x30 + 0x20 * (n))
48
-#define DISP_REG_MUTEX_MOD2(n)	(0x34 + 0x20 * (n))
19
+#define DISP_REG_MUTEX_EN(n)			(0x20 + 0x20 * (n))
20
+#define DISP_REG_MUTEX(n)			(0x24 + 0x20 * (n))
21
+#define DISP_REG_MUTEX_RST(n)			(0x28 + 0x20 * (n))
22
+#define DISP_REG_MUTEX_MOD(mutex_mod_reg, n)	(mutex_mod_reg + 0x20 * (n))
23
+#define DISP_REG_MUTEX_SOF(mutex_sof_reg, n)	(mutex_sof_reg + 0x20 * (n))
24
+#define DISP_REG_MUTEX_MOD2(n)			(0x34 + 0x20 * (n))
4925 
5026 #define INT_MUTEX				BIT(1)
5127 
....@@ -98,49 +74,28 @@
9874 #define MUTEX_SOF_DSI2			5
9975 #define MUTEX_SOF_DSI3			6
10076 
101
-#define OVL0_MOUT_EN_COLOR0		0x1
102
-#define OD_MOUT_EN_RDMA0		0x1
103
-#define OD1_MOUT_EN_RDMA1		BIT(16)
104
-#define UFOE_MOUT_EN_DSI0		0x1
105
-#define COLOR0_SEL_IN_OVL0		0x1
106
-#define OVL1_MOUT_EN_COLOR1		0x1
107
-#define GAMMA_MOUT_EN_RDMA1		0x1
108
-#define RDMA0_SOUT_DPI0			0x2
109
-#define RDMA0_SOUT_DPI1			0x3
110
-#define RDMA0_SOUT_DSI1			0x1
111
-#define RDMA0_SOUT_DSI2			0x4
112
-#define RDMA0_SOUT_DSI3			0x5
113
-#define RDMA1_SOUT_DPI0			0x2
114
-#define RDMA1_SOUT_DPI1			0x3
115
-#define RDMA1_SOUT_DSI1			0x1
116
-#define RDMA1_SOUT_DSI2			0x4
117
-#define RDMA1_SOUT_DSI3			0x5
118
-#define RDMA2_SOUT_DPI0			0x2
119
-#define RDMA2_SOUT_DPI1			0x3
120
-#define RDMA2_SOUT_DSI1			0x1
121
-#define RDMA2_SOUT_DSI2			0x4
122
-#define RDMA2_SOUT_DSI3			0x5
123
-#define DPI0_SEL_IN_RDMA1		0x1
124
-#define DPI0_SEL_IN_RDMA2		0x3
125
-#define DPI1_SEL_IN_RDMA1		(0x1 << 8)
126
-#define DPI1_SEL_IN_RDMA2		(0x3 << 8)
127
-#define DSI0_SEL_IN_RDMA1		0x1
128
-#define DSI0_SEL_IN_RDMA2		0x4
129
-#define DSI1_SEL_IN_RDMA1		0x1
130
-#define DSI1_SEL_IN_RDMA2		0x4
131
-#define DSI2_SEL_IN_RDMA1		(0x1 << 16)
132
-#define DSI2_SEL_IN_RDMA2		(0x4 << 16)
133
-#define DSI3_SEL_IN_RDMA1		(0x1 << 16)
134
-#define DSI3_SEL_IN_RDMA2		(0x4 << 16)
135
-#define COLOR1_SEL_IN_OVL1		0x1
136
-
137
-#define OVL_MOUT_EN_RDMA		0x1
138
-#define BLS_TO_DSI_RDMA1_TO_DPI1	0x8
139
-#define DSI_SEL_IN_BLS			0x0
14077 
14178 struct mtk_disp_mutex {
14279 	int id;
14380 	bool claimed;
81
+};
82
+
83
+enum mtk_ddp_mutex_sof_id {
84
+	DDP_MUTEX_SOF_SINGLE_MODE,
85
+	DDP_MUTEX_SOF_DSI0,
86
+	DDP_MUTEX_SOF_DSI1,
87
+	DDP_MUTEX_SOF_DPI0,
88
+	DDP_MUTEX_SOF_DPI1,
89
+	DDP_MUTEX_SOF_DSI2,
90
+	DDP_MUTEX_SOF_DSI3,
91
+};
92
+
93
+struct mtk_ddp_data {
94
+	const unsigned int *mutex_mod;
95
+	const unsigned int *mutex_sof;
96
+	const unsigned int mutex_mod_reg;
97
+	const unsigned int mutex_sof_reg;
98
+	const bool no_clk;
14499 };
145100 
146101 struct mtk_ddp {
....@@ -148,7 +103,7 @@
148103 	struct clk			*clk;
149104 	void __iomem			*regs;
150105 	struct mtk_disp_mutex		mutex[10];
151
-	const unsigned int		*mutex_mod;
106
+	const struct mtk_ddp_data	*data;
152107 };
153108 
154109 static const unsigned int mt2701_mutex_mod[DDP_COMPONENT_ID_MAX] = {
....@@ -198,191 +153,36 @@
198153 	[DDP_COMPONENT_WDMA1] = MT8173_MUTEX_MOD_DISP_WDMA1,
199154 };
200155 
201
-static unsigned int mtk_ddp_mout_en(enum mtk_ddp_comp_id cur,
202
-				    enum mtk_ddp_comp_id next,
203
-				    unsigned int *addr)
204
-{
205
-	unsigned int value;
156
+static const unsigned int mt2712_mutex_sof[DDP_MUTEX_SOF_DSI3 + 1] = {
157
+	[DDP_MUTEX_SOF_SINGLE_MODE] = MUTEX_SOF_SINGLE_MODE,
158
+	[DDP_MUTEX_SOF_DSI0] = MUTEX_SOF_DSI0,
159
+	[DDP_MUTEX_SOF_DSI1] = MUTEX_SOF_DSI1,
160
+	[DDP_MUTEX_SOF_DPI0] = MUTEX_SOF_DPI0,
161
+	[DDP_MUTEX_SOF_DPI1] = MUTEX_SOF_DPI1,
162
+	[DDP_MUTEX_SOF_DSI2] = MUTEX_SOF_DSI2,
163
+	[DDP_MUTEX_SOF_DSI3] = MUTEX_SOF_DSI3,
164
+};
206165 
207
-	if (cur == DDP_COMPONENT_OVL0 && next == DDP_COMPONENT_COLOR0) {
208
-		*addr = DISP_REG_CONFIG_DISP_OVL0_MOUT_EN;
209
-		value = OVL0_MOUT_EN_COLOR0;
210
-	} else if (cur == DDP_COMPONENT_OVL0 && next == DDP_COMPONENT_RDMA0) {
211
-		*addr = DISP_REG_CONFIG_DISP_OVL_MOUT_EN;
212
-		value = OVL_MOUT_EN_RDMA;
213
-	} else if (cur == DDP_COMPONENT_OD0 && next == DDP_COMPONENT_RDMA0) {
214
-		*addr = DISP_REG_CONFIG_DISP_OD_MOUT_EN;
215
-		value = OD_MOUT_EN_RDMA0;
216
-	} else if (cur == DDP_COMPONENT_UFOE && next == DDP_COMPONENT_DSI0) {
217
-		*addr = DISP_REG_CONFIG_DISP_UFOE_MOUT_EN;
218
-		value = UFOE_MOUT_EN_DSI0;
219
-	} else if (cur == DDP_COMPONENT_OVL1 && next == DDP_COMPONENT_COLOR1) {
220
-		*addr = DISP_REG_CONFIG_DISP_OVL1_MOUT_EN;
221
-		value = OVL1_MOUT_EN_COLOR1;
222
-	} else if (cur == DDP_COMPONENT_GAMMA && next == DDP_COMPONENT_RDMA1) {
223
-		*addr = DISP_REG_CONFIG_DISP_GAMMA_MOUT_EN;
224
-		value = GAMMA_MOUT_EN_RDMA1;
225
-	} else if (cur == DDP_COMPONENT_OD1 && next == DDP_COMPONENT_RDMA1) {
226
-		*addr = DISP_REG_CONFIG_DISP_OD_MOUT_EN;
227
-		value = OD1_MOUT_EN_RDMA1;
228
-	} else if (cur == DDP_COMPONENT_RDMA0 && next == DDP_COMPONENT_DPI0) {
229
-		*addr = DISP_REG_CONFIG_DISP_RDMA0_SOUT_EN;
230
-		value = RDMA0_SOUT_DPI0;
231
-	} else if (cur == DDP_COMPONENT_RDMA0 && next == DDP_COMPONENT_DPI1) {
232
-		*addr = DISP_REG_CONFIG_DISP_RDMA0_SOUT_EN;
233
-		value = RDMA0_SOUT_DPI1;
234
-	} else if (cur == DDP_COMPONENT_RDMA0 && next == DDP_COMPONENT_DSI1) {
235
-		*addr = DISP_REG_CONFIG_DISP_RDMA0_SOUT_EN;
236
-		value = RDMA0_SOUT_DSI1;
237
-	} else if (cur == DDP_COMPONENT_RDMA0 && next == DDP_COMPONENT_DSI2) {
238
-		*addr = DISP_REG_CONFIG_DISP_RDMA0_SOUT_EN;
239
-		value = RDMA0_SOUT_DSI2;
240
-	} else if (cur == DDP_COMPONENT_RDMA0 && next == DDP_COMPONENT_DSI3) {
241
-		*addr = DISP_REG_CONFIG_DISP_RDMA0_SOUT_EN;
242
-		value = RDMA0_SOUT_DSI3;
243
-	} else if (cur == DDP_COMPONENT_RDMA1 && next == DDP_COMPONENT_DSI1) {
244
-		*addr = DISP_REG_CONFIG_DISP_RDMA1_SOUT_EN;
245
-		value = RDMA1_SOUT_DSI1;
246
-	} else if (cur == DDP_COMPONENT_RDMA1 && next == DDP_COMPONENT_DSI2) {
247
-		*addr = DISP_REG_CONFIG_DISP_RDMA1_SOUT_EN;
248
-		value = RDMA1_SOUT_DSI2;
249
-	} else if (cur == DDP_COMPONENT_RDMA1 && next == DDP_COMPONENT_DSI3) {
250
-		*addr = DISP_REG_CONFIG_DISP_RDMA1_SOUT_EN;
251
-		value = RDMA1_SOUT_DSI3;
252
-	} else if (cur == DDP_COMPONENT_RDMA1 && next == DDP_COMPONENT_DPI0) {
253
-		*addr = DISP_REG_CONFIG_DISP_RDMA1_SOUT_EN;
254
-		value = RDMA1_SOUT_DPI0;
255
-	} else if (cur == DDP_COMPONENT_RDMA1 && next == DDP_COMPONENT_DPI1) {
256
-		*addr = DISP_REG_CONFIG_DISP_RDMA1_SOUT_EN;
257
-		value = RDMA1_SOUT_DPI1;
258
-	} else if (cur == DDP_COMPONENT_RDMA2 && next == DDP_COMPONENT_DPI0) {
259
-		*addr = DISP_REG_CONFIG_DISP_RDMA2_SOUT;
260
-		value = RDMA2_SOUT_DPI0;
261
-	} else if (cur == DDP_COMPONENT_RDMA2 && next == DDP_COMPONENT_DPI1) {
262
-		*addr = DISP_REG_CONFIG_DISP_RDMA2_SOUT;
263
-		value = RDMA2_SOUT_DPI1;
264
-	} else if (cur == DDP_COMPONENT_RDMA2 && next == DDP_COMPONENT_DSI1) {
265
-		*addr = DISP_REG_CONFIG_DISP_RDMA2_SOUT;
266
-		value = RDMA2_SOUT_DSI1;
267
-	} else if (cur == DDP_COMPONENT_RDMA2 && next == DDP_COMPONENT_DSI2) {
268
-		*addr = DISP_REG_CONFIG_DISP_RDMA2_SOUT;
269
-		value = RDMA2_SOUT_DSI2;
270
-	} else if (cur == DDP_COMPONENT_RDMA2 && next == DDP_COMPONENT_DSI3) {
271
-		*addr = DISP_REG_CONFIG_DISP_RDMA2_SOUT;
272
-		value = RDMA2_SOUT_DSI3;
273
-	} else {
274
-		value = 0;
275
-	}
166
+static const struct mtk_ddp_data mt2701_ddp_driver_data = {
167
+	.mutex_mod = mt2701_mutex_mod,
168
+	.mutex_sof = mt2712_mutex_sof,
169
+	.mutex_mod_reg = MT2701_DISP_MUTEX0_MOD0,
170
+	.mutex_sof_reg = MT2701_DISP_MUTEX0_SOF0,
171
+};
276172 
277
-	return value;
278
-}
173
+static const struct mtk_ddp_data mt2712_ddp_driver_data = {
174
+	.mutex_mod = mt2712_mutex_mod,
175
+	.mutex_sof = mt2712_mutex_sof,
176
+	.mutex_mod_reg = MT2701_DISP_MUTEX0_MOD0,
177
+	.mutex_sof_reg = MT2701_DISP_MUTEX0_SOF0,
178
+};
279179 
280
-static unsigned int mtk_ddp_sel_in(enum mtk_ddp_comp_id cur,
281
-				   enum mtk_ddp_comp_id next,
282
-				   unsigned int *addr)
283
-{
284
-	unsigned int value;
285
-
286
-	if (cur == DDP_COMPONENT_OVL0 && next == DDP_COMPONENT_COLOR0) {
287
-		*addr = DISP_REG_CONFIG_DISP_COLOR0_SEL_IN;
288
-		value = COLOR0_SEL_IN_OVL0;
289
-	} else if (cur == DDP_COMPONENT_RDMA1 && next == DDP_COMPONENT_DPI0) {
290
-		*addr = DISP_REG_CONFIG_DPI_SEL_IN;
291
-		value = DPI0_SEL_IN_RDMA1;
292
-	} else if (cur == DDP_COMPONENT_RDMA1 && next == DDP_COMPONENT_DPI1) {
293
-		*addr = DISP_REG_CONFIG_DPI_SEL_IN;
294
-		value = DPI1_SEL_IN_RDMA1;
295
-	} else if (cur == DDP_COMPONENT_RDMA1 && next == DDP_COMPONENT_DSI0) {
296
-		*addr = DISP_REG_CONFIG_DSIE_SEL_IN;
297
-		value = DSI0_SEL_IN_RDMA1;
298
-	} else if (cur == DDP_COMPONENT_RDMA1 && next == DDP_COMPONENT_DSI1) {
299
-		*addr = DISP_REG_CONFIG_DSIO_SEL_IN;
300
-		value = DSI1_SEL_IN_RDMA1;
301
-	} else if (cur == DDP_COMPONENT_RDMA1 && next == DDP_COMPONENT_DSI2) {
302
-		*addr = DISP_REG_CONFIG_DSIE_SEL_IN;
303
-		value = DSI2_SEL_IN_RDMA1;
304
-	} else if (cur == DDP_COMPONENT_RDMA1 && next == DDP_COMPONENT_DSI3) {
305
-		*addr = DISP_REG_CONFIG_DSIO_SEL_IN;
306
-		value = DSI3_SEL_IN_RDMA1;
307
-	} else if (cur == DDP_COMPONENT_RDMA2 && next == DDP_COMPONENT_DPI0) {
308
-		*addr = DISP_REG_CONFIG_DPI_SEL_IN;
309
-		value = DPI0_SEL_IN_RDMA2;
310
-	} else if (cur == DDP_COMPONENT_RDMA2 && next == DDP_COMPONENT_DPI1) {
311
-		*addr = DISP_REG_CONFIG_DPI_SEL_IN;
312
-		value = DPI1_SEL_IN_RDMA2;
313
-	} else if (cur == DDP_COMPONENT_RDMA2 && next == DDP_COMPONENT_DSI0) {
314
-		*addr = DISP_REG_CONFIG_DSIE_SEL_IN;
315
-		value = DSI0_SEL_IN_RDMA2;
316
-	} else if (cur == DDP_COMPONENT_RDMA2 && next == DDP_COMPONENT_DSI1) {
317
-		*addr = DISP_REG_CONFIG_DSIO_SEL_IN;
318
-		value = DSI1_SEL_IN_RDMA2;
319
-	} else if (cur == DDP_COMPONENT_RDMA2 && next == DDP_COMPONENT_DSI2) {
320
-		*addr = DISP_REG_CONFIG_DSIE_SEL_IN;
321
-		value = DSI2_SEL_IN_RDMA2;
322
-	} else if (cur == DDP_COMPONENT_RDMA2 && next == DDP_COMPONENT_DSI3) {
323
-		*addr = DISP_REG_CONFIG_DSIE_SEL_IN;
324
-		value = DSI3_SEL_IN_RDMA2;
325
-	} else if (cur == DDP_COMPONENT_OVL1 && next == DDP_COMPONENT_COLOR1) {
326
-		*addr = DISP_REG_CONFIG_DISP_COLOR1_SEL_IN;
327
-		value = COLOR1_SEL_IN_OVL1;
328
-	} else if (cur == DDP_COMPONENT_BLS && next == DDP_COMPONENT_DSI0) {
329
-		*addr = DISP_REG_CONFIG_DSI_SEL;
330
-		value = DSI_SEL_IN_BLS;
331
-	} else {
332
-		value = 0;
333
-	}
334
-
335
-	return value;
336
-}
337
-
338
-static void mtk_ddp_sout_sel(void __iomem *config_regs,
339
-			     enum mtk_ddp_comp_id cur,
340
-			     enum mtk_ddp_comp_id next)
341
-{
342
-	if (cur == DDP_COMPONENT_BLS && next == DDP_COMPONENT_DSI0)
343
-		writel_relaxed(BLS_TO_DSI_RDMA1_TO_DPI1,
344
-			       config_regs + DISP_REG_CONFIG_OUT_SEL);
345
-}
346
-
347
-void mtk_ddp_add_comp_to_path(void __iomem *config_regs,
348
-			      enum mtk_ddp_comp_id cur,
349
-			      enum mtk_ddp_comp_id next)
350
-{
351
-	unsigned int addr, value, reg;
352
-
353
-	value = mtk_ddp_mout_en(cur, next, &addr);
354
-	if (value) {
355
-		reg = readl_relaxed(config_regs + addr) | value;
356
-		writel_relaxed(reg, config_regs + addr);
357
-	}
358
-
359
-	mtk_ddp_sout_sel(config_regs, cur, next);
360
-
361
-	value = mtk_ddp_sel_in(cur, next, &addr);
362
-	if (value) {
363
-		reg = readl_relaxed(config_regs + addr) | value;
364
-		writel_relaxed(reg, config_regs + addr);
365
-	}
366
-}
367
-
368
-void mtk_ddp_remove_comp_from_path(void __iomem *config_regs,
369
-				   enum mtk_ddp_comp_id cur,
370
-				   enum mtk_ddp_comp_id next)
371
-{
372
-	unsigned int addr, value, reg;
373
-
374
-	value = mtk_ddp_mout_en(cur, next, &addr);
375
-	if (value) {
376
-		reg = readl_relaxed(config_regs + addr) & ~value;
377
-		writel_relaxed(reg, config_regs + addr);
378
-	}
379
-
380
-	value = mtk_ddp_sel_in(cur, next, &addr);
381
-	if (value) {
382
-		reg = readl_relaxed(config_regs + addr) & ~value;
383
-		writel_relaxed(reg, config_regs + addr);
384
-	}
385
-}
180
+static const struct mtk_ddp_data mt8173_ddp_driver_data = {
181
+	.mutex_mod = mt8173_mutex_mod,
182
+	.mutex_sof = mt2712_mutex_sof,
183
+	.mutex_mod_reg = MT2701_DISP_MUTEX0_MOD0,
184
+	.mutex_sof_reg = MT2701_DISP_MUTEX0_SOF0,
185
+};
386186 
387187 struct mtk_disp_mutex *mtk_disp_mutex_get(struct device *dev, unsigned int id)
388188 {
....@@ -428,45 +228,49 @@
428228 	struct mtk_ddp *ddp = container_of(mutex, struct mtk_ddp,
429229 					   mutex[mutex->id]);
430230 	unsigned int reg;
231
+	unsigned int sof_id;
431232 	unsigned int offset;
432233 
433234 	WARN_ON(&ddp->mutex[mutex->id] != mutex);
434235 
435236 	switch (id) {
436237 	case DDP_COMPONENT_DSI0:
437
-		reg = MUTEX_SOF_DSI0;
238
+		sof_id = DDP_MUTEX_SOF_DSI0;
438239 		break;
439240 	case DDP_COMPONENT_DSI1:
440
-		reg = MUTEX_SOF_DSI0;
241
+		sof_id = DDP_MUTEX_SOF_DSI0;
441242 		break;
442243 	case DDP_COMPONENT_DSI2:
443
-		reg = MUTEX_SOF_DSI2;
244
+		sof_id = DDP_MUTEX_SOF_DSI2;
444245 		break;
445246 	case DDP_COMPONENT_DSI3:
446
-		reg = MUTEX_SOF_DSI3;
247
+		sof_id = DDP_MUTEX_SOF_DSI3;
447248 		break;
448249 	case DDP_COMPONENT_DPI0:
449
-		reg = MUTEX_SOF_DPI0;
250
+		sof_id = DDP_MUTEX_SOF_DPI0;
450251 		break;
451252 	case DDP_COMPONENT_DPI1:
452
-		reg = MUTEX_SOF_DPI1;
253
+		sof_id = DDP_MUTEX_SOF_DPI1;
453254 		break;
454255 	default:
455
-		if (ddp->mutex_mod[id] < 32) {
456
-			offset = DISP_REG_MUTEX_MOD(mutex->id);
256
+		if (ddp->data->mutex_mod[id] < 32) {
257
+			offset = DISP_REG_MUTEX_MOD(ddp->data->mutex_mod_reg,
258
+						    mutex->id);
457259 			reg = readl_relaxed(ddp->regs + offset);
458
-			reg |= 1 << ddp->mutex_mod[id];
260
+			reg |= 1 << ddp->data->mutex_mod[id];
459261 			writel_relaxed(reg, ddp->regs + offset);
460262 		} else {
461263 			offset = DISP_REG_MUTEX_MOD2(mutex->id);
462264 			reg = readl_relaxed(ddp->regs + offset);
463
-			reg |= 1 << (ddp->mutex_mod[id] - 32);
265
+			reg |= 1 << (ddp->data->mutex_mod[id] - 32);
464266 			writel_relaxed(reg, ddp->regs + offset);
465267 		}
466268 		return;
467269 	}
468270 
469
-	writel_relaxed(reg, ddp->regs + DISP_REG_MUTEX_SOF(mutex->id));
271
+	writel_relaxed(ddp->data->mutex_sof[sof_id],
272
+		       ddp->regs +
273
+		       DISP_REG_MUTEX_SOF(ddp->data->mutex_sof_reg, mutex->id));
470274 }
471275 
472276 void mtk_disp_mutex_remove_comp(struct mtk_disp_mutex *mutex,
....@@ -487,18 +291,21 @@
487291 	case DDP_COMPONENT_DPI0:
488292 	case DDP_COMPONENT_DPI1:
489293 		writel_relaxed(MUTEX_SOF_SINGLE_MODE,
490
-			       ddp->regs + DISP_REG_MUTEX_SOF(mutex->id));
294
+			       ddp->regs +
295
+			       DISP_REG_MUTEX_SOF(ddp->data->mutex_sof_reg,
296
+						  mutex->id));
491297 		break;
492298 	default:
493
-		if (ddp->mutex_mod[id] < 32) {
494
-			offset = DISP_REG_MUTEX_MOD(mutex->id);
299
+		if (ddp->data->mutex_mod[id] < 32) {
300
+			offset = DISP_REG_MUTEX_MOD(ddp->data->mutex_mod_reg,
301
+						    mutex->id);
495302 			reg = readl_relaxed(ddp->regs + offset);
496
-			reg &= ~(1 << ddp->mutex_mod[id]);
303
+			reg &= ~(1 << ddp->data->mutex_mod[id]);
497304 			writel_relaxed(reg, ddp->regs + offset);
498305 		} else {
499306 			offset = DISP_REG_MUTEX_MOD2(mutex->id);
500307 			reg = readl_relaxed(ddp->regs + offset);
501
-			reg &= ~(1 << (ddp->mutex_mod[id] - 32));
308
+			reg &= ~(1 << (ddp->data->mutex_mod[id] - 32));
502309 			writel_relaxed(reg, ddp->regs + offset);
503310 		}
504311 		break;
....@@ -560,10 +367,15 @@
560367 	for (i = 0; i < 10; i++)
561368 		ddp->mutex[i].id = i;
562369 
563
-	ddp->clk = devm_clk_get(dev, NULL);
564
-	if (IS_ERR(ddp->clk)) {
565
-		dev_err(dev, "Failed to get clock\n");
566
-		return PTR_ERR(ddp->clk);
370
+	ddp->data = of_device_get_match_data(dev);
371
+
372
+	if (!ddp->data->no_clk) {
373
+		ddp->clk = devm_clk_get(dev, NULL);
374
+		if (IS_ERR(ddp->clk)) {
375
+			if (PTR_ERR(ddp->clk) != -EPROBE_DEFER)
376
+				dev_err(dev, "Failed to get clock\n");
377
+			return PTR_ERR(ddp->clk);
378
+		}
567379 	}
568380 
569381 	regs = platform_get_resource(pdev, IORESOURCE_MEM, 0);
....@@ -572,8 +384,6 @@
572384 		dev_err(dev, "Failed to map mutex registers\n");
573385 		return PTR_ERR(ddp->regs);
574386 	}
575
-
576
-	ddp->mutex_mod = of_device_get_match_data(dev);
577387 
578388 	platform_set_drvdata(pdev, ddp);
579389 
....@@ -586,9 +396,12 @@
586396 }
587397 
588398 static const struct of_device_id ddp_driver_dt_match[] = {
589
-	{ .compatible = "mediatek,mt2701-disp-mutex", .data = mt2701_mutex_mod},
590
-	{ .compatible = "mediatek,mt2712-disp-mutex", .data = mt2712_mutex_mod},
591
-	{ .compatible = "mediatek,mt8173-disp-mutex", .data = mt8173_mutex_mod},
399
+	{ .compatible = "mediatek,mt2701-disp-mutex",
400
+	  .data = &mt2701_ddp_driver_data},
401
+	{ .compatible = "mediatek,mt2712-disp-mutex",
402
+	  .data = &mt2712_ddp_driver_data},
403
+	{ .compatible = "mediatek,mt8173-disp-mutex",
404
+	  .data = &mt8173_ddp_driver_data},
592405 	{},
593406 };
594407 MODULE_DEVICE_TABLE(of, ddp_driver_dt_match);