change wifi driver to cypress

hc

2024-01-05 071106ecf68c401173c58808b1cf5f68cc50d390

 kernel/drivers/gpu/drm/amd/display/dc/inc/hw/timing_generator.h
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@@ -59,6 +59,8 @@
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 struct drr_params {
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 	uint32_t vertical_total_min;
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 	uint32_t vertical_total_max;
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+	uint32_t vertical_total_mid;
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+	uint32_t vertical_total_mid_frame_num;
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 	bool immediate_flip;
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 };
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@@ -68,14 +70,6 @@
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 enum crtc_state {
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 	CRTC_STATE_VBLANK = 0,
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 	CRTC_STATE_VACTIVE
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-};
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-
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-struct _dlg_otg_param {
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-	int vstartup_start;
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-	int vupdate_offset;
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-	int vupdate_width;
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-	int vready_offset;
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-	enum signal_type signal;
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 };
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 struct vupdate_keepout_params {
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@@ -104,6 +98,21 @@
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 	INTERSECT_WINDOW_NOT_A_NOT_B,
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 };
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+#ifdef CONFIG_DRM_AMD_DC_DCN3_0
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+enum otg_out_mux_dest {
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+	OUT_MUX_DIO = 0,
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+};
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+#endif
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+
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+enum h_timing_div_mode {
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+	H_TIMING_NO_DIV,
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+	H_TIMING_DIV_BY2,
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+#if defined(CONFIG_DRM_AMD_DC_DCN3_0)
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+	H_TIMING_RESERVED,
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+	H_TIMING_DIV_BY4,
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+#endif
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+};
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+
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 struct crc_params {
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 	/* Regions used to calculate CRC*/
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 	uint16_t windowa_x_start;
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@@ -118,6 +127,9 @@
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 	enum crc_selection selection;
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+	uint8_t dsc_mode;
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+	uint8_t odm_mode;
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+
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 	bool continuous_mode;
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 	bool enable;
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 };
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@@ -126,7 +138,6 @@
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 	const struct timing_generator_funcs *funcs;
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 	struct dc_bios *bp;
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 	struct dc_context *ctx;
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-	struct _dlg_otg_param dlg_otg_param;
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 	int inst;
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 };
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@@ -134,15 +145,30 @@
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 struct drr_params;
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+
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 struct timing_generator_funcs {
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 	bool (*validate_timing)(struct timing_generator *tg,
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 							const struct dc_crtc_timing *timing);
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 	void (*program_timing)(struct timing_generator *tg,
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 							const struct dc_crtc_timing *timing,
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-							bool use_vbios);
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-	void (*program_vline_interrupt)(struct timing_generator *optc,
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-			const struct dc_crtc_timing *dc_crtc_timing,
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-			unsigned long long vsync_delta);
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+							int vready_offset,
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+							int vstartup_start,
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+							int vupdate_offset,
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+							int vupdate_width,
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+							const enum signal_type signal,
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+							bool use_vbios
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+	);
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+	void (*setup_vertical_interrupt0)(
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+			struct timing_generator *optc,
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+			uint32_t start_line,
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+			uint32_t end_line);
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+	void (*setup_vertical_interrupt1)(
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+			struct timing_generator *optc,
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+			uint32_t start_line);
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+	void (*setup_vertical_interrupt2)(
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+			struct timing_generator *optc,
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+			uint32_t start_line);
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+
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 	bool (*enable_crtc)(struct timing_generator *tg);
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 	bool (*disable_crtc)(struct timing_generator *tg);
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 	bool (*is_counter_moving)(struct timing_generator *tg);
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@@ -159,6 +185,8 @@
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 	bool (*get_otg_active_size)(struct timing_generator *optc,
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 			uint32_t *otg_active_width,
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 			uint32_t *otg_active_height);
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+	bool (*is_matching_timing)(struct timing_generator *tg,
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+			const struct dc_crtc_timing *otg_timing);
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 	void (*set_early_control)(struct timing_generator *tg,
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 							   uint32_t early_cntl);
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 	void (*wait_for_state)(struct timing_generator *tg,
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@@ -178,6 +206,10 @@
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 							const struct dcp_gsl_params *gsl_params);
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 	void (*unlock)(struct timing_generator *tg);
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 	void (*lock)(struct timing_generator *tg);
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+	void (*lock_doublebuffer_disable)(struct timing_generator *tg);
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+	void (*lock_doublebuffer_enable)(struct timing_generator *tg);
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+	void(*triplebuffer_unlock)(struct timing_generator *tg);
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+	void(*triplebuffer_lock)(struct timing_generator *tg);
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 	void (*enable_reset_trigger)(struct timing_generator *tg,
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 				     int source_tg_inst);
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 	void (*enable_crtc_reset)(struct timing_generator *tg,
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@@ -189,7 +221,8 @@
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 					bool enable, const struct dc_crtc_timing *timing);
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 	void (*set_drr)(struct timing_generator *tg, const struct drr_params *params);
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 	void (*set_static_screen_control)(struct timing_generator *tg,
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-							uint32_t value);
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+						uint32_t event_triggers,
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+						uint32_t num_frames);
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 	void (*set_test_pattern)(
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 		struct timing_generator *tg,
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 		enum controller_dp_test_pattern test_pattern,
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@@ -197,7 +230,11 @@
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 	bool (*arm_vert_intr)(struct timing_generator *tg, uint8_t width);
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-	void (*program_global_sync)(struct timing_generator *tg);
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+	void (*program_global_sync)(struct timing_generator *tg,
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+			int vready_offset,
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+			int vstartup_start,
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+			int vupdate_offset,
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+			int vupdate_width);
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 	void (*enable_optc_clock)(struct timing_generator *tg, bool enable);
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 	void (*program_stereo)(struct timing_generator *tg,
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 		const struct dc_crtc_timing *timing, struct crtc_stereo_flags *flags);
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@@ -209,6 +246,14 @@
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 	bool (*is_tg_enabled)(struct timing_generator *tg);
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 	bool (*is_optc_underflow_occurred)(struct timing_generator *tg);
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 	void (*clear_optc_underflow)(struct timing_generator *tg);
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+
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+	void (*set_dwb_source)(struct timing_generator *optc,
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+		uint32_t dwb_pipe_inst);
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+
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+	void (*get_optc_source)(struct timing_generator *optc,
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+			uint32_t *num_of_input_segments,
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+			uint32_t *seg0_src_sel,
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+			uint32_t *seg1_src_sel);
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 	/**
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 	 * Configure CRCs for the given timing generator. Return false if TG is
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@@ -224,6 +269,34 @@
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 	bool (*get_crc)(struct timing_generator *tg,
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 			uint32_t *r_cr, uint32_t *g_y, uint32_t *b_cb);
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+	void (*program_manual_trigger)(struct timing_generator *optc);
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+	void (*setup_manual_trigger)(struct timing_generator *optc);
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+	bool (*get_hw_timing)(struct timing_generator *optc,
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+			struct dc_crtc_timing *hw_crtc_timing);
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+
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+	void (*set_vtg_params)(struct timing_generator *optc,
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+			const struct dc_crtc_timing *dc_crtc_timing);
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+
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+	void (*set_dsc_config)(struct timing_generator *optc,
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+			       enum optc_dsc_mode dsc_mode,
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+			       uint32_t dsc_bytes_per_pixel,
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+			       uint32_t dsc_slice_width);
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+	void (*set_odm_bypass)(struct timing_generator *optc, const struct dc_crtc_timing *dc_crtc_timing);
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+	void (*set_odm_combine)(struct timing_generator *optc, int *opp_id, int opp_cnt,
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+			struct dc_crtc_timing *timing);
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+	void (*set_gsl)(struct timing_generator *optc, const struct gsl_params *params);
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+	void (*set_gsl_source_select)(struct timing_generator *optc,
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+			int group_idx,
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+			uint32_t gsl_ready_signal);
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+#if defined(CONFIG_DRM_AMD_DC_DCN3_0)
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+	void (*set_out_mux)(struct timing_generator *tg, enum otg_out_mux_dest dest);
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+	void (*set_vrr_m_const)(struct timing_generator *optc,
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+			double vtotal_avg);
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+	void (*set_drr_trigger_window)(struct timing_generator *optc,
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+			uint32_t window_start, uint32_t window_end);
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+	void (*set_vtotal_change_limit)(struct timing_generator *optc,
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+			uint32_t limit);
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+#endif
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 };
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 #endif