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2024-01-05 071106ecf68c401173c58808b1cf5f68cc50d390 
 kernel/drivers/gpu/drm/amd/display/dc/inc/hw/mpc.h
....@@ -27,9 +27,16 @@
2727 
2828 #include "dc_hw_types.h"
2929 #include "hw_shared.h"
30
+#include "transform.h"
3031 
3132 #define MAX_MPCC 6
3233 #define MAX_OPP 6
34
+
35
+#if defined(CONFIG_DRM_AMD_DC_DCN3_0)
36
+#define MAX_DWB		2
37
+#else
38
+#define MAX_DWB		1
39
+#endif
3340 
3441 enum mpc_output_csc_mode {
3542 	MPC_OUTPUT_CSC_DISABLE = 0,
....@@ -62,8 +69,20 @@
6269 	int global_alpha;
6370 	bool overlap_only;
6471 
72
+	/* MPCC top/bottom gain settings */
73
+	int bottom_gain_mode;
74
+	int background_color_bpc;
75
+	int top_gain;
76
+	int bottom_inside_gain;
77
+	int bottom_outside_gain;
6578 };
6679 
80
+#if defined(CONFIG_DRM_AMD_DC_DCN3_0)
81
+struct mpc_grph_gamut_adjustment {
82
+	struct fixed31_32 temperature_matrix[CSC_TEMPERATURE_MATRIX_SIZE];
83
+	enum graphics_gamut_adjust_type gamut_adjust_type;
84
+};
85
+#endif
6786 struct mpcc_sm_cfg {
6887 	bool enable;
6988 	/* 0-single plane,2-row subsampling,4-column subsampling,6-checkboard subsampling */
....@@ -78,6 +97,22 @@
7897 	int force_next_field_polarity;
7998 };
8099 
100
+struct mpc_denorm_clamp {
101
+	int clamp_max_r_cr;
102
+	int clamp_min_r_cr;
103
+	int clamp_max_g_y;
104
+	int clamp_min_g_y;
105
+	int clamp_max_b_cb;
106
+	int clamp_min_b_cb;
107
+};
108
+
109
+#if defined(CONFIG_DRM_AMD_DC_DCN3_0)
110
+struct mpc_dwb_flow_control {
111
+	int flow_ctrl_mode;
112
+	int flow_ctrl_cnt0;
113
+	int flow_ctrl_cnt1;
114
+};
115
+#endif
81116 /*
82117  * MPCC connection and blending configuration for a single MPCC instance.
83118  * This struct is used as a node in an MPC tree.
....@@ -88,6 +123,9 @@
88123 	struct mpcc *mpcc_bot;		/* pointer to bottom layer MPCC.  NULL when not connected */
89124 	struct mpcc_blnd_cfg blnd_cfg;	/* The blending configuration for this MPCC */
90125 	struct mpcc_sm_cfg sm_cfg;	/* stereo mix setting for this MPCC */
126
+#if defined(CONFIG_DRM_AMD_DC_DCN3_0)
127
+	bool shared_bottom;		/* TRUE if MPCC output to both OPP and DWB endpoints, else FALSE */
128
+#endif
91129 };
92130 
93131 /*
....@@ -103,6 +141,8 @@
103141 	struct dc_context *ctx;
104142 
105143 	struct mpcc mpcc_array[MAX_MPCC];
144
+	struct pwl_params blender_params;
145
+	bool cm_bypass_mode;
106146 };
107147 
108148 struct mpcc_state {
....@@ -172,6 +212,9 @@
172212 	 * Return:  void
173213 	 */
174214 	void (*mpc_init)(struct mpc *mpc);
215
+	void (*mpc_init_single_inst)(
216
+			struct mpc *mpc,
217
+			unsigned int mpcc_id);
175218 
176219 	/*
177220 	 * Update the blending configuration for a specified MPCC.
....@@ -188,6 +231,66 @@
188231 		struct mpcc_blnd_cfg *blnd_cfg,
189232 		int mpcc_id);
190233 
234
+	/*
235
+	 * Lock cursor updates for the specified OPP.
236
+	 * OPP defines the set of MPCC that are locked together for cursor.
237
+	 *
238
+	 * Parameters:
239
+	 * [in] 	mpc		- MPC context.
240
+	 * [in]     opp_id	- The OPP to lock cursor updates on
241
+	 * [in]		lock	- lock/unlock the OPP
242
+	 *
243
+	 * Return:  void
244
+	 */
245
+	void (*cursor_lock)(
246
+			struct mpc *mpc,
247
+			int opp_id,
248
+			bool lock);
249
+
250
+#if defined(CONFIG_DRM_AMD_DC_DCN3_0)
251
+	/*
252
+	 * Add DPP into 'secondary' MPC tree based on specified blending position.
253
+	 * Only used for planes that are part of blending chain for DWB output
254
+	 *
255
+	 * Parameters:
256
+	 * [in/out] mpc		- MPC context.
257
+	 * [in/out] tree		- MPC tree structure that plane will be added to.
258
+	 * [in]	blnd_cfg	- MPCC blending configuration for the new blending layer.
259
+	 * [in]	sm_cfg		- MPCC stereo mix configuration for the new blending layer.
260
+	 *			  stereo mix must disable for the very bottom layer of the tree config.
261
+	 * [in]	insert_above_mpcc - Insert new plane above this MPCC.  If NULL, insert as bottom plane.
262
+	 * [in]	dpp_id		- DPP instance for the plane to be added.
263
+	 * [in]	mpcc_id		- The MPCC physical instance to use for blending.
264
+	 *
265
+	 * Return:  struct mpcc* - MPCC that was added.
266
+	 */
267
+	struct mpcc* (*insert_plane_to_secondary)(
268
+			struct mpc *mpc,
269
+			struct mpc_tree *tree,
270
+			struct mpcc_blnd_cfg *blnd_cfg,
271
+			struct mpcc_sm_cfg *sm_cfg,
272
+			struct mpcc *insert_above_mpcc,
273
+			int dpp_id,
274
+			int mpcc_id);
275
+
276
+	/*
277
+	 * Remove a specified DPP from the 'secondary' MPC tree.
278
+	 *
279
+	 * Parameters:
280
+	 * [in/out] mpc		- MPC context.
281
+	 * [in/out] tree	- MPC tree structure that plane will be removed from.
282
+	 * [in]     mpcc	- MPCC to be removed from tree.
283
+	 * Return:  void
284
+	 */
285
+	void (*remove_mpcc_from_secondary)(
286
+			struct mpc *mpc,
287
+			struct mpc_tree *tree,
288
+			struct mpcc *mpcc);
289
+
290
+	struct mpcc* (*get_mpcc_for_dpp_from_secondary)(
291
+			struct mpc_tree *tree,
292
+			int dpp_id);
293
+#endif
191294 	struct mpcc* (*get_mpcc_for_dpp)(
192295 			struct mpc_tree *tree,
193296 			int dpp_id);
....@@ -200,6 +303,77 @@
200303 		struct mpc *mpc,
201304 		struct mpc_tree *tree);
202305 
306
+	void (*set_denorm)(struct mpc *mpc,
307
+			int opp_id,
308
+			enum dc_color_depth output_depth);
309
+
310
+	void (*set_denorm_clamp)(
311
+			struct mpc *mpc,
312
+			int opp_id,
313
+			struct mpc_denorm_clamp denorm_clamp);
314
+
315
+	void (*set_output_csc)(struct mpc *mpc,
316
+			int opp_id,
317
+			const uint16_t *regval,
318
+			enum mpc_output_csc_mode ocsc_mode);
319
+
320
+	void (*set_ocsc_default)(struct mpc *mpc,
321
+			int opp_id,
322
+			enum dc_color_space color_space,
323
+			enum mpc_output_csc_mode ocsc_mode);
324
+
325
+	void (*set_output_gamma)(
326
+			struct mpc *mpc,
327
+			int mpcc_id,
328
+			const struct pwl_params *params);
329
+	void (*power_on_mpc_mem_pwr)(
330
+			struct mpc *mpc,
331
+			int mpcc_id,
332
+			bool power_on);
333
+#if defined(CONFIG_DRM_AMD_DC_DCN3_0)
334
+	void (*set_dwb_mux)(
335
+			struct mpc *mpc,
336
+			int dwb_id,
337
+			int mpcc_id);
338
+
339
+	void (*disable_dwb_mux)(
340
+		struct mpc *mpc,
341
+		int dwb_id);
342
+
343
+	bool (*is_dwb_idle)(
344
+		struct mpc *mpc,
345
+		int dwb_id);
346
+
347
+	void (*set_out_rate_control)(
348
+		struct mpc *mpc,
349
+		int opp_id,
350
+		bool enable,
351
+		bool rate_2x_mode,
352
+		struct mpc_dwb_flow_control *flow_control);
353
+#endif
354
+
355
+#if defined(CONFIG_DRM_AMD_DC_DCN3_0)
356
+	void (*set_gamut_remap)(
357
+			struct mpc *mpc,
358
+			int mpcc_id,
359
+			const struct mpc_grph_gamut_adjustment *adjust);
360
+
361
+	bool (*program_shaper)(
362
+			struct mpc *mpc,
363
+			const struct pwl_params *params,
364
+			uint32_t rmu_idx);
365
+
366
+	uint32_t (*acquire_rmu)(struct mpc *mpc, int mpcc_id, int rmu_idx);
367
+
368
+	bool (*program_3dlut)(
369
+			struct mpc *mpc,
370
+			const struct tetrahedral_params *params,
371
+			int rmu_idx);
372
+
373
+	int (*release_rmu)(struct mpc *mpc, int mpcc_id);
374
+
375
+#endif
376
+
203377 };
204378 
205379 #endif