| .. | .. |
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| 84 | 84 | #define DCP_REG(reg) (reg + tg110->offsets.dcp) |
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| 85 | 85 | #define DMIF_REG(reg) (reg + tg110->offsets.dmif) |
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| 86 | 86 | |
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| 87 | | -static void program_pix_dur(struct timing_generator *tg, uint32_t pix_clk_khz) |
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| 87 | +static void program_pix_dur(struct timing_generator *tg, uint32_t pix_clk_100hz) |
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| 88 | 88 | { |
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| 89 | 89 | uint64_t pix_dur; |
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| 90 | 90 | uint32_t addr = mmDMIF_PG0_DPG_PIPE_ARBITRATION_CONTROL1 |
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| 91 | 91 | + DCE110TG_FROM_TG(tg)->offsets.dmif; |
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| 92 | 92 | uint32_t value = dm_read_reg(tg->ctx, addr); |
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| 93 | 93 | |
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| 94 | | - if (pix_clk_khz == 0) |
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| 94 | + if (pix_clk_100hz == 0) |
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| 95 | 95 | return; |
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| 96 | 96 | |
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| 97 | | - pix_dur = 1000000000 / pix_clk_khz; |
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| 97 | + pix_dur = div_u64(10000000000ull, pix_clk_100hz); |
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| 98 | 98 | |
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| 99 | 99 | set_reg_field_value( |
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| 100 | 100 | value, |
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| .. | .. |
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| 107 | 107 | |
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| 108 | 108 | static void program_timing(struct timing_generator *tg, |
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| 109 | 109 | const struct dc_crtc_timing *timing, |
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| 110 | + int vready_offset, |
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| 111 | + int vstartup_start, |
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| 112 | + int vupdate_offset, |
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| 113 | + int vupdate_width, |
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| 114 | + const enum signal_type signal, |
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| 110 | 115 | bool use_vbios) |
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| 111 | 116 | { |
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| 112 | 117 | if (!use_vbios) |
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| 113 | | - program_pix_dur(tg, timing->pix_clk_khz); |
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| 118 | + program_pix_dur(tg, timing->pix_clk_100hz); |
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| 114 | 119 | |
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| 115 | | - dce110_tg_program_timing(tg, timing, use_vbios); |
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| 120 | + dce110_tg_program_timing(tg, timing, 0, 0, 0, 0, 0, use_vbios); |
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| 116 | 121 | } |
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| 117 | 122 | |
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| 118 | 123 | static void dce80_timing_generator_enable_advanced_request( |
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