change wifi driver to cypress

hc

2024-01-05 071106ecf68c401173c58808b1cf5f68cc50d390

 kernel/drivers/gpu/drm/amd/display/dc/calcs/dcn_calcs.c
..
..
@@ -459,9 +459,9 @@
459
459
 	struct _vcs_dpi_display_dlg_regs_st *dlg_regs = &pipe->dlg_regs;
460
460
 	struct _vcs_dpi_display_ttu_regs_st *ttu_regs = &pipe->ttu_regs;
461
461
 	struct _vcs_dpi_display_rq_regs_st *rq_regs = &pipe->rq_regs;
462
-	struct _vcs_dpi_display_rq_params_st rq_param = {0};
463
-	struct _vcs_dpi_display_dlg_sys_params_st dlg_sys_param = {0};
464
-	struct _vcs_dpi_display_e2e_pipe_params_st input = { { { 0 } } };
462
+	struct _vcs_dpi_display_rq_params_st *rq_param = &pipe->dml_rq_param;
463
+	struct _vcs_dpi_display_dlg_sys_params_st *dlg_sys_param = &pipe->dml_dlg_sys_param;
464
+	struct _vcs_dpi_display_e2e_pipe_params_st *input = &pipe->dml_input;
465
465
 	float total_active_bw = 0;
466
466
 	float total_prefetch_bw = 0;
467
467
 	int total_flip_bytes = 0;
..
..
@@ -470,45 +470,48 @@
470
470
 	memset(dlg_regs, 0, sizeof(*dlg_regs));
471
471
 	memset(ttu_regs, 0, sizeof(*ttu_regs));
472
472
 	memset(rq_regs, 0, sizeof(*rq_regs));
473
+	memset(rq_param, 0, sizeof(*rq_param));
474
+	memset(dlg_sys_param, 0, sizeof(*dlg_sys_param));
475
+	memset(input, 0, sizeof(*input));
473
476
 
474
477
 	for (i = 0; i < number_of_planes; i++) {
475
478
 		total_active_bw += v->read_bandwidth[i];
476
479
 		total_prefetch_bw += v->prefetch_bandwidth[i];
477
480
 		total_flip_bytes += v->total_immediate_flip_bytes[i];
478
481
 	}
479
-	dlg_sys_param.total_flip_bw = v->return_bw - dcn_bw_max2(total_active_bw, total_prefetch_bw);
480
-	if (dlg_sys_param.total_flip_bw < 0.0)
481
-		dlg_sys_param.total_flip_bw = 0;
482
+	dlg_sys_param->total_flip_bw = v->return_bw - dcn_bw_max2(total_active_bw, total_prefetch_bw);
483
+	if (dlg_sys_param->total_flip_bw < 0.0)
484
+		dlg_sys_param->total_flip_bw = 0;
482
485
 
483
-	dlg_sys_param.t_mclk_wm_us = v->dram_clock_change_watermark;
484
-	dlg_sys_param.t_sr_wm_us = v->stutter_enter_plus_exit_watermark;
485
-	dlg_sys_param.t_urg_wm_us = v->urgent_watermark;
486
-	dlg_sys_param.t_extra_us = v->urgent_extra_latency;
487
-	dlg_sys_param.deepsleep_dcfclk_mhz = v->dcf_clk_deep_sleep;
488
-	dlg_sys_param.total_flip_bytes = total_flip_bytes;
486
+	dlg_sys_param->t_mclk_wm_us = v->dram_clock_change_watermark;
487
+	dlg_sys_param->t_sr_wm_us = v->stutter_enter_plus_exit_watermark;
488
+	dlg_sys_param->t_urg_wm_us = v->urgent_watermark;
489
+	dlg_sys_param->t_extra_us = v->urgent_extra_latency;
490
+	dlg_sys_param->deepsleep_dcfclk_mhz = v->dcf_clk_deep_sleep;
491
+	dlg_sys_param->total_flip_bytes = total_flip_bytes;
489
492
 
490
-	pipe_ctx_to_e2e_pipe_params(pipe, &input.pipe);
491
-	input.clks_cfg.dcfclk_mhz = v->dcfclk;
492
-	input.clks_cfg.dispclk_mhz = v->dispclk;
493
-	input.clks_cfg.dppclk_mhz = v->dppclk;
494
-	input.clks_cfg.refclk_mhz = dc->res_pool->ref_clocks.dchub_ref_clock_inKhz / 1000.0;
495
-	input.clks_cfg.socclk_mhz = v->socclk;
496
-	input.clks_cfg.voltage = v->voltage_level;
493
+	pipe_ctx_to_e2e_pipe_params(pipe, &input->pipe);
494
+	input->clks_cfg.dcfclk_mhz = v->dcfclk;
495
+	input->clks_cfg.dispclk_mhz = v->dispclk;
496
+	input->clks_cfg.dppclk_mhz = v->dppclk;
497
+	input->clks_cfg.refclk_mhz = dc->res_pool->ref_clocks.dchub_ref_clock_inKhz / 1000.0;
498
+	input->clks_cfg.socclk_mhz = v->socclk;
499
+	input->clks_cfg.voltage = v->voltage_level;
497
500
 //	dc->dml.logger = pool->base.logger;
498
-	input.dout.output_format = (v->output_format[in_idx] == dcn_bw_420) ? dm_420 : dm_444;
499
-	input.dout.output_type  = (v->output[in_idx] == dcn_bw_hdmi) ? dm_hdmi : dm_dp;
501
+	input->dout.output_format = (v->output_format[in_idx] == dcn_bw_420) ? dm_420 : dm_444;
502
+	input->dout.output_type  = (v->output[in_idx] == dcn_bw_hdmi) ? dm_hdmi : dm_dp;
500
503
 	//input[in_idx].dout.output_standard;
501
504
 
502
505
 	/*todo: soc->sr_enter_plus_exit_time??*/
503
-	dlg_sys_param.t_srx_delay_us = dc->dcn_ip->dcfclk_cstate_latency / v->dcf_clk_deep_sleep;
506
+	dlg_sys_param->t_srx_delay_us = dc->dcn_ip->dcfclk_cstate_latency / v->dcf_clk_deep_sleep;
504
507
 
505
-	dml1_rq_dlg_get_rq_params(dml, &rq_param, input.pipe.src);
508
+	dml1_rq_dlg_get_rq_params(dml, rq_param, input.pipe.src);
506
509
 	dml1_extract_rq_regs(dml, rq_regs, rq_param);
507
510
 	dml1_rq_dlg_get_dlg_params(
508
511
 			dml,
509
512
 			dlg_regs,
510
513
 			ttu_regs,
511
-			rq_param.dlg,
514
+			rq_param->dlg,
512
515
 			dlg_sys_param,
513
516
 			input,
514
517
 			true,