forked from ~ljy/RK356X_SDK_RELEASE

hc
2024-01-05 071106ecf68c401173c58808b1cf5f68cc50d390
kernel/drivers/gpu/drm/amd/amdkfd/kfd_device_queue_manager.h
....@@ -31,9 +31,8 @@
3131 #include "kfd_priv.h"
3232 #include "kfd_mqd_manager.h"
3333
34
-#define KFD_UNMAP_LATENCY_MS (4000)
35
-#define QUEUE_PREEMPT_DEFAULT_TIMEOUT_MS (2 * KFD_UNMAP_LATENCY_MS + 1000)
36
-#define KFD_SDMA_QUEUES_PER_ENGINE (2)
34
+
35
+#define VMID_NUM 16
3736
3837 struct device_process_node {
3938 struct qcm_process_device *qpd;
....@@ -48,8 +47,6 @@
4847 * @destroy_queue: Queue destruction routine.
4948 *
5049 * @update_queue: Queue update routine.
51
- *
52
- * @get_mqd_manager: Returns the mqd manager according to the mqd type.
5350 *
5451 * @exeute_queues: Dispatches the queues list to the H/W.
5552 *
....@@ -82,6 +79,8 @@
8279 *
8380 * @restore_process_queues: Restore all evicted queues queues of a process
8481 *
82
+ * @get_wave_state: Retrieves context save state and optionally copies the
83
+ * control stack, if kept in the MQD, to the given userspace address.
8584 */
8685
8786 struct device_queue_manager_ops {
....@@ -96,10 +95,6 @@
9695 int (*update_queue)(struct device_queue_manager *dqm,
9796 struct queue *q);
9897
99
- struct mqd_manager * (*get_mqd_manager)
100
- (struct device_queue_manager *dqm,
101
- enum KFD_MQD_TYPE type);
102
-
10398 int (*register_process)(struct device_queue_manager *dqm,
10499 struct qcm_process_device *qpd);
105100
....@@ -109,6 +104,7 @@
109104 int (*initialize)(struct device_queue_manager *dqm);
110105 int (*start)(struct device_queue_manager *dqm);
111106 int (*stop)(struct device_queue_manager *dqm);
107
+ void (*pre_reset)(struct device_queue_manager *dqm);
112108 void (*uninitialize)(struct device_queue_manager *dqm);
113109 int (*create_kernel_queue)(struct device_queue_manager *dqm,
114110 struct kernel_queue *kq,
....@@ -137,6 +133,12 @@
137133 struct qcm_process_device *qpd);
138134 int (*restore_process_queues)(struct device_queue_manager *dqm,
139135 struct qcm_process_device *qpd);
136
+
137
+ int (*get_wave_state)(struct device_queue_manager *dqm,
138
+ struct queue *q,
139
+ void __user *ctl_stack,
140
+ u32 *ctl_stack_used_size,
141
+ u32 *save_area_used_size);
140142 };
141143
142144 struct device_queue_manager_asic_ops {
....@@ -151,6 +153,8 @@
151153 void (*init_sdma_vm)(struct device_queue_manager *dqm,
152154 struct queue *q,
153155 struct qcm_process_device *qpd);
156
+ struct mqd_manager * (*mqd_manager_init)(enum KFD_MQD_TYPE type,
157
+ struct kfd_dev *dev);
154158 };
155159
156160 /**
....@@ -176,24 +180,29 @@
176180 struct list_head queues;
177181 unsigned int saved_flags;
178182 unsigned int processes_count;
179
- unsigned int queue_count;
180
- unsigned int sdma_queue_count;
183
+ unsigned int active_queue_count;
184
+ unsigned int active_cp_queue_count;
185
+ unsigned int gws_queue_count;
181186 unsigned int total_queue_count;
182187 unsigned int next_pipe_to_allocate;
183188 unsigned int *allocated_queues;
184
- unsigned int sdma_bitmap;
185
- unsigned int vmid_bitmap;
189
+ uint64_t sdma_bitmap;
190
+ uint64_t xgmi_sdma_bitmap;
191
+ /* the pasid mapping for each kfd vmid */
192
+ uint16_t vmid_pasid[VMID_NUM];
186193 uint64_t pipelines_addr;
187
- struct kfd_mem_obj *pipeline_mem;
188194 uint64_t fence_gpu_addr;
189
- unsigned int *fence_addr;
195
+ uint64_t *fence_addr;
190196 struct kfd_mem_obj *fence_mem;
191197 bool active_runlist;
192198 int sched_policy;
193199
194200 /* hw exception */
195201 bool is_hws_hang;
202
+ bool is_resetting;
196203 struct work_struct hw_exception_work;
204
+ struct kfd_mem_obj hiq_sdma_mqd;
205
+ bool sched_running;
197206 };
198207
199208 void device_queue_manager_init_cik(
....@@ -206,12 +215,15 @@
206215 struct device_queue_manager_asic_ops *asic_ops);
207216 void device_queue_manager_init_v9(
208217 struct device_queue_manager_asic_ops *asic_ops);
218
+void device_queue_manager_init_v10_navi10(
219
+ struct device_queue_manager_asic_ops *asic_ops);
209220 void program_sh_mem_settings(struct device_queue_manager *dqm,
210221 struct qcm_process_device *qpd);
211
-unsigned int get_queues_num(struct device_queue_manager *dqm);
222
+unsigned int get_cp_queues_num(struct device_queue_manager *dqm);
212223 unsigned int get_queues_per_pipe(struct device_queue_manager *dqm);
213224 unsigned int get_pipes_per_mec(struct device_queue_manager *dqm);
214225 unsigned int get_num_sdma_queues(struct device_queue_manager *dqm);
226
+unsigned int get_num_xgmi_sdma_queues(struct device_queue_manager *dqm);
215227
216228 static inline unsigned int get_sh_mem_bases_32(struct kfd_process_device *pdd)
217229 {
....@@ -231,12 +243,19 @@
231243 static inline void dqm_lock(struct device_queue_manager *dqm)
232244 {
233245 mutex_lock(&dqm->lock_hidden);
234
- dqm->saved_flags = memalloc_nofs_save();
246
+ dqm->saved_flags = memalloc_noreclaim_save();
235247 }
236248 static inline void dqm_unlock(struct device_queue_manager *dqm)
237249 {
238
- memalloc_nofs_restore(dqm->saved_flags);
250
+ memalloc_noreclaim_restore(dqm->saved_flags);
239251 mutex_unlock(&dqm->lock_hidden);
240252 }
241253
254
+static inline int read_sdma_queue_counter(uint64_t __user *q_rptr, uint64_t *val)
255
+{
256
+ /*
257
+ * SDMA activity counter is stored at queue's RPTR + 0x8 location.
258
+ */
259
+ return get_user(*val, q_rptr + 1);
260
+}
242261 #endif /* KFD_DEVICE_QUEUE_MANAGER_H_ */