forked from ~ljy/RK356X_SDK_RELEASE
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2024-01-05 071106ecf68c401173c58808b1cf5f68cc50d390 
 kernel/drivers/gpu/drm/amd/amdgpu/dce_v8_0.c
....@@ -20,7 +20,10 @@
2020  * OTHER DEALINGS IN THE SOFTWARE.
2121  *
2222  */
23
-#include <drm/drmP.h>
23
+
24
+#include <drm/drm_fourcc.h>
25
+#include <drm/drm_vblank.h>
26
+
2427 #include "amdgpu.h"
2528 #include "amdgpu_pm.h"
2629 #include "amdgpu_i2c.h"
....@@ -31,6 +34,7 @@
3134 #include "atombios_encoders.h"
3235 #include "amdgpu_pll.h"
3336 #include "amdgpu_connectors.h"
37
+#include "amdgpu_display.h"
3438 #include "dce_v8_0.h"
3539 
3640 #include "dce/dce_8_0_d.h"
....@@ -180,10 +184,14 @@
180184 			       int crtc_id, u64 crtc_base, bool async)
181185 {
182186 	struct amdgpu_crtc *amdgpu_crtc = adev->mode_info.crtcs[crtc_id];
187
+	struct drm_framebuffer *fb = amdgpu_crtc->base.primary->fb;
183188 
184189 	/* flip at hsync for async, default is vsync */
185190 	WREG32(mmGRPH_FLIP_CONTROL + amdgpu_crtc->crtc_offset, async ?
186191 	       GRPH_FLIP_CONTROL__GRPH_SURFACE_UPDATE_H_RETRACE_EN_MASK : 0);
192
+	/* update pitch */
193
+	WREG32(mmGRPH_PITCH + amdgpu_crtc->crtc_offset,
194
+	       fb->pitches[0] / fb->format->cpp[0]);
187195 	/* update the primary scanout addresses */
188196 	WREG32(mmGRPH_PRIMARY_SURFACE_ADDRESS_HIGH + amdgpu_crtc->crtc_offset,
189197 	       upper_32_bits(crtc_base));
....@@ -265,11 +273,13 @@
265273  */
266274 static void dce_v8_0_hpd_init(struct amdgpu_device *adev)
267275 {
268
-	struct drm_device *dev = adev->ddev;
276
+	struct drm_device *dev = adev_to_drm(adev);
269277 	struct drm_connector *connector;
278
+	struct drm_connector_list_iter iter;
270279 	u32 tmp;
271280 
272
-	list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
281
+	drm_connector_list_iter_begin(dev, &iter);
282
+	drm_for_each_connector_iter(connector, &iter) {
273283 		struct amdgpu_connector *amdgpu_connector = to_amdgpu_connector(connector);
274284 
275285 		if (amdgpu_connector->hpd.hpd >= adev->mode_info.num_hpd)
....@@ -295,6 +305,7 @@
295305 		dce_v8_0_hpd_set_polarity(adev, amdgpu_connector->hpd.hpd);
296306 		amdgpu_irq_get(adev, &adev->hpd_irq, amdgpu_connector->hpd.hpd);
297307 	}
308
+	drm_connector_list_iter_end(&iter);
298309 }
299310 
300311 /**
....@@ -307,11 +318,13 @@
307318  */
308319 static void dce_v8_0_hpd_fini(struct amdgpu_device *adev)
309320 {
310
-	struct drm_device *dev = adev->ddev;
321
+	struct drm_device *dev = adev_to_drm(adev);
311322 	struct drm_connector *connector;
323
+	struct drm_connector_list_iter iter;
312324 	u32 tmp;
313325 
314
-	list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
326
+	drm_connector_list_iter_begin(dev, &iter);
327
+	drm_for_each_connector_iter(connector, &iter) {
315328 		struct amdgpu_connector *amdgpu_connector = to_amdgpu_connector(connector);
316329 
317330 		if (amdgpu_connector->hpd.hpd >= adev->mode_info.num_hpd)
....@@ -323,6 +336,7 @@
323336 
324337 		amdgpu_irq_put(adev, &adev->hpd_irq, amdgpu_connector->hpd.hpd);
325338 	}
339
+	drm_connector_list_iter_end(&iter);
326340 }
327341 
328342 static u32 dce_v8_0_hpd_get_gpio_reg(struct amdgpu_device *adev)
....@@ -430,7 +444,7 @@
430444 static void dce_v8_0_program_fmt(struct drm_encoder *encoder)
431445 {
432446 	struct drm_device *dev = encoder->dev;
433
-	struct amdgpu_device *adev = dev->dev_private;
447
+	struct amdgpu_device *adev = drm_to_adev(dev);
434448 	struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder);
435449 	struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(encoder->crtc);
436450 	struct drm_connector *connector = amdgpu_get_connector_for_encoder(encoder);
....@@ -1132,7 +1146,7 @@
11321146 
11331147 static void dce_v8_0_afmt_audio_select_pin(struct drm_encoder *encoder)
11341148 {
1135
-	struct amdgpu_device *adev = encoder->dev->dev_private;
1149
+	struct amdgpu_device *adev = drm_to_adev(encoder->dev);
11361150 	struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder);
11371151 	struct amdgpu_encoder_atom_dig *dig = amdgpu_encoder->enc_priv;
11381152 	u32 offset;
....@@ -1149,10 +1163,12 @@
11491163 static void dce_v8_0_audio_write_latency_fields(struct drm_encoder *encoder,
11501164 						struct drm_display_mode *mode)
11511165 {
1152
-	struct amdgpu_device *adev = encoder->dev->dev_private;
1166
+	struct drm_device *dev = encoder->dev;
1167
+	struct amdgpu_device *adev = drm_to_adev(dev);
11531168 	struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder);
11541169 	struct amdgpu_encoder_atom_dig *dig = amdgpu_encoder->enc_priv;
11551170 	struct drm_connector *connector;
1171
+	struct drm_connector_list_iter iter;
11561172 	struct amdgpu_connector *amdgpu_connector = NULL;
11571173 	u32 tmp = 0, offset;
11581174 
....@@ -1161,12 +1177,14 @@
11611177 
11621178 	offset = dig->afmt->pin->offset;
11631179 
1164
-	list_for_each_entry(connector, &encoder->dev->mode_config.connector_list, head) {
1180
+	drm_connector_list_iter_begin(dev, &iter);
1181
+	drm_for_each_connector_iter(connector, &iter) {
11651182 		if (connector->encoder == encoder) {
11661183 			amdgpu_connector = to_amdgpu_connector(connector);
11671184 			break;
11681185 		}
11691186 	}
1187
+	drm_connector_list_iter_end(&iter);
11701188 
11711189 	if (!amdgpu_connector) {
11721190 		DRM_ERROR("Couldn't find encoder's connector\n");
....@@ -1206,10 +1224,12 @@
12061224 
12071225 static void dce_v8_0_audio_write_speaker_allocation(struct drm_encoder *encoder)
12081226 {
1209
-	struct amdgpu_device *adev = encoder->dev->dev_private;
1227
+	struct drm_device *dev = encoder->dev;
1228
+	struct amdgpu_device *adev = drm_to_adev(dev);
12101229 	struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder);
12111230 	struct amdgpu_encoder_atom_dig *dig = amdgpu_encoder->enc_priv;
12121231 	struct drm_connector *connector;
1232
+	struct drm_connector_list_iter iter;
12131233 	struct amdgpu_connector *amdgpu_connector = NULL;
12141234 	u32 offset, tmp;
12151235 	u8 *sadb = NULL;
....@@ -1220,12 +1240,14 @@
12201240 
12211241 	offset = dig->afmt->pin->offset;
12221242 
1223
-	list_for_each_entry(connector, &encoder->dev->mode_config.connector_list, head) {
1243
+	drm_connector_list_iter_begin(dev, &iter);
1244
+	drm_for_each_connector_iter(connector, &iter) {
12241245 		if (connector->encoder == encoder) {
12251246 			amdgpu_connector = to_amdgpu_connector(connector);
12261247 			break;
12271248 		}
12281249 	}
1250
+	drm_connector_list_iter_end(&iter);
12291251 
12301252 	if (!amdgpu_connector) {
12311253 		DRM_ERROR("Couldn't find encoder's connector\n");
....@@ -1255,11 +1277,13 @@
12551277 
12561278 static void dce_v8_0_audio_write_sad_regs(struct drm_encoder *encoder)
12571279 {
1258
-	struct amdgpu_device *adev = encoder->dev->dev_private;
1280
+	struct drm_device *dev = encoder->dev;
1281
+	struct amdgpu_device *adev = drm_to_adev(dev);
12591282 	struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder);
12601283 	struct amdgpu_encoder_atom_dig *dig = amdgpu_encoder->enc_priv;
12611284 	u32 offset;
12621285 	struct drm_connector *connector;
1286
+	struct drm_connector_list_iter iter;
12631287 	struct amdgpu_connector *amdgpu_connector = NULL;
12641288 	struct cea_sad *sads;
12651289 	int i, sad_count;
....@@ -1284,12 +1308,14 @@
12841308 
12851309 	offset = dig->afmt->pin->offset;
12861310 
1287
-	list_for_each_entry(connector, &encoder->dev->mode_config.connector_list, head) {
1311
+	drm_connector_list_iter_begin(dev, &iter);
1312
+	drm_for_each_connector_iter(connector, &iter) {
12881313 		if (connector->encoder == encoder) {
12891314 			amdgpu_connector = to_amdgpu_connector(connector);
12901315 			break;
12911316 		}
12921317 	}
1318
+	drm_connector_list_iter_end(&iter);
12931319 
12941320 	if (!amdgpu_connector) {
12951321 		DRM_ERROR("Couldn't find encoder's connector\n");
....@@ -1297,10 +1323,10 @@
12971323 	}
12981324 
12991325 	sad_count = drm_edid_to_sad(amdgpu_connector_edid(connector), &sads);
1300
-	if (sad_count <= 0) {
1326
+	if (sad_count < 0)
13011327 		DRM_ERROR("Couldn't read SADs: %d\n", sad_count);
1328
+	if (sad_count <= 0)
13021329 		return;
1303
-	}
13041330 	BUG_ON(!sads);
13051331 
13061332 	for (i = 0; i < ARRAY_SIZE(eld_reg_to_type); i++) {
....@@ -1420,7 +1446,7 @@
14201446 static void dce_v8_0_afmt_update_ACR(struct drm_encoder *encoder, uint32_t clock)
14211447 {
14221448 	struct drm_device *dev = encoder->dev;
1423
-	struct amdgpu_device *adev = dev->dev_private;
1449
+	struct amdgpu_device *adev = drm_to_adev(dev);
14241450 	struct amdgpu_afmt_acr acr = amdgpu_afmt_acr(clock);
14251451 	struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder);
14261452 	struct amdgpu_encoder_atom_dig *dig = amdgpu_encoder->enc_priv;
....@@ -1443,7 +1469,7 @@
14431469 					       void *buffer, size_t size)
14441470 {
14451471 	struct drm_device *dev = encoder->dev;
1446
-	struct amdgpu_device *adev = dev->dev_private;
1472
+	struct amdgpu_device *adev = drm_to_adev(dev);
14471473 	struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder);
14481474 	struct amdgpu_encoder_atom_dig *dig = amdgpu_encoder->enc_priv;
14491475 	uint32_t offset = dig->afmt->offset;
....@@ -1463,7 +1489,7 @@
14631489 static void dce_v8_0_audio_set_dto(struct drm_encoder *encoder, u32 clock)
14641490 {
14651491 	struct drm_device *dev = encoder->dev;
1466
-	struct amdgpu_device *adev = dev->dev_private;
1492
+	struct amdgpu_device *adev = drm_to_adev(dev);
14671493 	struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder);
14681494 	struct amdgpu_encoder_atom_dig *dig = amdgpu_encoder->enc_priv;
14691495 	struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(encoder->crtc);
....@@ -1490,7 +1516,7 @@
14901516 				  struct drm_display_mode *mode)
14911517 {
14921518 	struct drm_device *dev = encoder->dev;
1493
-	struct amdgpu_device *adev = dev->dev_private;
1519
+	struct amdgpu_device *adev = drm_to_adev(dev);
14941520 	struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder);
14951521 	struct amdgpu_encoder_atom_dig *dig = amdgpu_encoder->enc_priv;
14961522 	struct drm_connector *connector = amdgpu_get_connector_for_encoder(encoder);
....@@ -1615,7 +1641,7 @@
16151641 	dce_v8_0_audio_write_sad_regs(encoder);
16161642 	dce_v8_0_audio_write_latency_fields(encoder, mode);
16171643 
1618
-	err = drm_hdmi_avi_infoframe_from_display_mode(&frame, mode, false);
1644
+	err = drm_hdmi_avi_infoframe_from_display_mode(&frame, connector, mode);
16191645 	if (err < 0) {
16201646 		DRM_ERROR("failed to setup AVI infoframe: %zd\n", err);
16211647 		return;
....@@ -1652,7 +1678,7 @@
16521678 static void dce_v8_0_afmt_enable(struct drm_encoder *encoder, bool enable)
16531679 {
16541680 	struct drm_device *dev = encoder->dev;
1655
-	struct amdgpu_device *adev = dev->dev_private;
1681
+	struct amdgpu_device *adev = drm_to_adev(dev);
16561682 	struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder);
16571683 	struct amdgpu_encoder_atom_dig *dig = amdgpu_encoder->enc_priv;
16581684 
....@@ -1725,7 +1751,7 @@
17251751 {
17261752 	struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
17271753 	struct drm_device *dev = crtc->dev;
1728
-	struct amdgpu_device *adev = dev->dev_private;
1754
+	struct amdgpu_device *adev = drm_to_adev(dev);
17291755 	u32 vga_control;
17301756 
17311757 	vga_control = RREG32(vga_control_regs[amdgpu_crtc->crtc_id]) & ~1;
....@@ -1739,7 +1765,7 @@
17391765 {
17401766 	struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
17411767 	struct drm_device *dev = crtc->dev;
1742
-	struct amdgpu_device *adev = dev->dev_private;
1768
+	struct amdgpu_device *adev = drm_to_adev(dev);
17431769 
17441770 	if (enable)
17451771 		WREG32(mmGRPH_ENABLE + amdgpu_crtc->crtc_offset, 1);
....@@ -1753,7 +1779,7 @@
17531779 {
17541780 	struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
17551781 	struct drm_device *dev = crtc->dev;
1756
-	struct amdgpu_device *adev = dev->dev_private;
1782
+	struct amdgpu_device *adev = drm_to_adev(dev);
17571783 	struct drm_framebuffer *target_fb;
17581784 	struct drm_gem_object *obj;
17591785 	struct amdgpu_bo *abo;
....@@ -1864,6 +1890,16 @@
18641890 		/* Greater 8 bpc fb needs to bypass hw-lut to retain precision */
18651891 		bypass_lut = true;
18661892 		break;
1893
+	case DRM_FORMAT_XBGR8888:
1894
+	case DRM_FORMAT_ABGR8888:
1895
+		fb_format = ((GRPH_DEPTH_32BPP << GRPH_CONTROL__GRPH_DEPTH__SHIFT) |
1896
+		             (GRPH_FORMAT_ARGB8888 << GRPH_CONTROL__GRPH_FORMAT__SHIFT));
1897
+		fb_swap = ((GRPH_RED_SEL_B << GRPH_SWAP_CNTL__GRPH_RED_CROSSBAR__SHIFT) |
1898
+		           (GRPH_BLUE_SEL_R << GRPH_SWAP_CNTL__GRPH_BLUE_CROSSBAR__SHIFT));
1899
+#ifdef __BIG_ENDIAN
1900
+		fb_swap |= (GRPH_ENDIAN_8IN32 << GRPH_SWAP_CNTL__GRPH_ENDIAN_SWAP__SHIFT);
1901
+#endif
1902
+		break;
18671903 	default:
18681904 		DRM_ERROR("Unsupported screen format %s\n",
18691905 		          drm_get_format_name(target_fb->format->format, &format_name));
....@@ -1968,7 +2004,7 @@
19682004 				    struct drm_display_mode *mode)
19692005 {
19702006 	struct drm_device *dev = crtc->dev;
1971
-	struct amdgpu_device *adev = dev->dev_private;
2007
+	struct amdgpu_device *adev = drm_to_adev(dev);
19722008 	struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
19732009 
19742010 	if (mode->flags & DRM_MODE_FLAG_INTERLACE)
....@@ -1982,7 +2018,7 @@
19822018 {
19832019 	struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
19842020 	struct drm_device *dev = crtc->dev;
1985
-	struct amdgpu_device *adev = dev->dev_private;
2021
+	struct amdgpu_device *adev = drm_to_adev(dev);
19862022 	u16 *r, *g, *b;
19872023 	int i;
19882024 
....@@ -2104,7 +2140,7 @@
21042140 {
21052141 	struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
21062142 	struct drm_device *dev = crtc->dev;
2107
-	struct amdgpu_device *adev = dev->dev_private;
2143
+	struct amdgpu_device *adev = drm_to_adev(dev);
21082144 	u32 pll_in_use;
21092145 	int pll;
21102146 
....@@ -2152,7 +2188,7 @@
21522188 
21532189 static void dce_v8_0_lock_cursor(struct drm_crtc *crtc, bool lock)
21542190 {
2155
-	struct amdgpu_device *adev = crtc->dev->dev_private;
2191
+	struct amdgpu_device *adev = drm_to_adev(crtc->dev);
21562192 	struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
21572193 	uint32_t cur_lock;
21582194 
....@@ -2167,34 +2203,34 @@
21672203 static void dce_v8_0_hide_cursor(struct drm_crtc *crtc)
21682204 {
21692205 	struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
2170
-	struct amdgpu_device *adev = crtc->dev->dev_private;
2206
+	struct amdgpu_device *adev = drm_to_adev(crtc->dev);
21712207 
2172
-	WREG32_IDX(mmCUR_CONTROL + amdgpu_crtc->crtc_offset,
2173
-		   (CURSOR_24_8_PRE_MULT << CUR_CONTROL__CURSOR_MODE__SHIFT) |
2174
-		   (CURSOR_URGENT_1_2 << CUR_CONTROL__CURSOR_URGENT_CONTROL__SHIFT));
2208
+	WREG32(mmCUR_CONTROL + amdgpu_crtc->crtc_offset,
2209
+	       (CURSOR_24_8_PRE_MULT << CUR_CONTROL__CURSOR_MODE__SHIFT) |
2210
+	       (CURSOR_URGENT_1_2 << CUR_CONTROL__CURSOR_URGENT_CONTROL__SHIFT));
21752211 }
21762212 
21772213 static void dce_v8_0_show_cursor(struct drm_crtc *crtc)
21782214 {
21792215 	struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
2180
-	struct amdgpu_device *adev = crtc->dev->dev_private;
2216
+	struct amdgpu_device *adev = drm_to_adev(crtc->dev);
21812217 
21822218 	WREG32(mmCUR_SURFACE_ADDRESS_HIGH + amdgpu_crtc->crtc_offset,
21832219 	       upper_32_bits(amdgpu_crtc->cursor_addr));
21842220 	WREG32(mmCUR_SURFACE_ADDRESS + amdgpu_crtc->crtc_offset,
21852221 	       lower_32_bits(amdgpu_crtc->cursor_addr));
21862222 
2187
-	WREG32_IDX(mmCUR_CONTROL + amdgpu_crtc->crtc_offset,
2188
-		   CUR_CONTROL__CURSOR_EN_MASK |
2189
-		   (CURSOR_24_8_PRE_MULT << CUR_CONTROL__CURSOR_MODE__SHIFT) |
2190
-		   (CURSOR_URGENT_1_2 << CUR_CONTROL__CURSOR_URGENT_CONTROL__SHIFT));
2223
+	WREG32(mmCUR_CONTROL + amdgpu_crtc->crtc_offset,
2224
+	       CUR_CONTROL__CURSOR_EN_MASK |
2225
+	       (CURSOR_24_8_PRE_MULT << CUR_CONTROL__CURSOR_MODE__SHIFT) |
2226
+	       (CURSOR_URGENT_1_2 << CUR_CONTROL__CURSOR_URGENT_CONTROL__SHIFT));
21912227 }
21922228 
21932229 static int dce_v8_0_cursor_move_locked(struct drm_crtc *crtc,
21942230 				       int x, int y)
21952231 {
21962232 	struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
2197
-	struct amdgpu_device *adev = crtc->dev->dev_private;
2233
+	struct amdgpu_device *adev = drm_to_adev(crtc->dev);
21982234 	int xorigin = 0, yorigin = 0;
21992235 
22002236 	amdgpu_crtc->cursor_x = x;
....@@ -2269,7 +2305,7 @@
22692305 	aobj = gem_to_amdgpu_bo(obj);
22702306 	ret = amdgpu_bo_reserve(aobj, false);
22712307 	if (ret != 0) {
2272
-		drm_gem_object_put_unlocked(obj);
2308
+		drm_gem_object_put(obj);
22732309 		return ret;
22742310 	}
22752311 
....@@ -2277,7 +2313,7 @@
22772313 	amdgpu_bo_unreserve(aobj);
22782314 	if (ret) {
22792315 		DRM_ERROR("Failed to pin new cursor BO (%d)\n", ret);
2280
-		drm_gem_object_put_unlocked(obj);
2316
+		drm_gem_object_put(obj);
22812317 		return ret;
22822318 	}
22832319 	amdgpu_crtc->cursor_addr = amdgpu_bo_gpu_offset(aobj);
....@@ -2312,7 +2348,7 @@
23122348 			amdgpu_bo_unpin(aobj);
23132349 			amdgpu_bo_unreserve(aobj);
23142350 		}
2315
-		drm_gem_object_put_unlocked(amdgpu_crtc->cursor_bo);
2351
+		drm_gem_object_put(amdgpu_crtc->cursor_bo);
23162352 	}
23172353 
23182354 	amdgpu_crtc->cursor_bo = obj;
....@@ -2359,12 +2395,16 @@
23592395 	.set_config = amdgpu_display_crtc_set_config,
23602396 	.destroy = dce_v8_0_crtc_destroy,
23612397 	.page_flip_target = amdgpu_display_crtc_page_flip_target,
2398
+	.get_vblank_counter = amdgpu_get_vblank_counter_kms,
2399
+	.enable_vblank = amdgpu_enable_vblank_kms,
2400
+	.disable_vblank = amdgpu_disable_vblank_kms,
2401
+	.get_vblank_timestamp = drm_crtc_vblank_helper_get_vblank_timestamp,
23622402 };
23632403 
23642404 static void dce_v8_0_crtc_dpms(struct drm_crtc *crtc, int mode)
23652405 {
23662406 	struct drm_device *dev = crtc->dev;
2367
-	struct amdgpu_device *adev = dev->dev_private;
2407
+	struct amdgpu_device *adev = drm_to_adev(dev);
23682408 	struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
23692409 	unsigned type;
23702410 
....@@ -2418,7 +2458,7 @@
24182458 {
24192459 	struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
24202460 	struct drm_device *dev = crtc->dev;
2421
-	struct amdgpu_device *adev = dev->dev_private;
2461
+	struct amdgpu_device *adev = drm_to_adev(dev);
24222462 	struct amdgpu_atom_ss ss;
24232463 	int i;
24242464 
....@@ -2557,6 +2597,7 @@
25572597 	.prepare = dce_v8_0_crtc_prepare,
25582598 	.commit = dce_v8_0_crtc_commit,
25592599 	.disable = dce_v8_0_crtc_disable,
2600
+	.get_scanout_position = amdgpu_crtc_get_scanout_position,
25602601 };
25612602 
25622603 static int dce_v8_0_crtc_init(struct amdgpu_device *adev, int index)
....@@ -2568,7 +2609,7 @@
25682609 	if (amdgpu_crtc == NULL)
25692610 		return -ENOMEM;
25702611 
2571
-	drm_crtc_init(adev->ddev, &amdgpu_crtc->base, &dce_v8_0_crtc_funcs);
2612
+	drm_crtc_init(adev_to_drm(adev), &amdgpu_crtc->base, &dce_v8_0_crtc_funcs);
25722613 
25732614 	drm_mode_crtc_set_gamma_size(&amdgpu_crtc->base, 256);
25742615 	amdgpu_crtc->crtc_id = index;
....@@ -2576,8 +2617,8 @@
25762617 
25772618 	amdgpu_crtc->max_cursor_width = CIK_CURSOR_WIDTH;
25782619 	amdgpu_crtc->max_cursor_height = CIK_CURSOR_HEIGHT;
2579
-	adev->ddev->mode_config.cursor_width = amdgpu_crtc->max_cursor_width;
2580
-	adev->ddev->mode_config.cursor_height = amdgpu_crtc->max_cursor_height;
2620
+	adev_to_drm(adev)->mode_config.cursor_width = amdgpu_crtc->max_cursor_width;
2621
+	adev_to_drm(adev)->mode_config.cursor_height = amdgpu_crtc->max_cursor_height;
25812622 
25822623 	amdgpu_crtc->crtc_offset = crtc_offsets[amdgpu_crtc->crtc_id];
25832624 
....@@ -2632,40 +2673,40 @@
26322673 	struct amdgpu_device *adev = (struct amdgpu_device *)handle;
26332674 
26342675 	for (i = 0; i < adev->mode_info.num_crtc; i++) {
2635
-		r = amdgpu_irq_add_id(adev, AMDGPU_IH_CLIENTID_LEGACY, i + 1, &adev->crtc_irq);
2676
+		r = amdgpu_irq_add_id(adev, AMDGPU_IRQ_CLIENTID_LEGACY, i + 1, &adev->crtc_irq);
26362677 		if (r)
26372678 			return r;
26382679 	}
26392680 
26402681 	for (i = 8; i < 20; i += 2) {
2641
-		r = amdgpu_irq_add_id(adev, AMDGPU_IH_CLIENTID_LEGACY, i, &adev->pageflip_irq);
2682
+		r = amdgpu_irq_add_id(adev, AMDGPU_IRQ_CLIENTID_LEGACY, i, &adev->pageflip_irq);
26422683 		if (r)
26432684 			return r;
26442685 	}
26452686 
26462687 	/* HPD hotplug */
2647
-	r = amdgpu_irq_add_id(adev, AMDGPU_IH_CLIENTID_LEGACY, 42, &adev->hpd_irq);
2688
+	r = amdgpu_irq_add_id(adev, AMDGPU_IRQ_CLIENTID_LEGACY, 42, &adev->hpd_irq);
26482689 	if (r)
26492690 		return r;
26502691 
2651
-	adev->ddev->mode_config.funcs = &amdgpu_mode_funcs;
2692
+	adev_to_drm(adev)->mode_config.funcs = &amdgpu_mode_funcs;
26522693 
2653
-	adev->ddev->mode_config.async_page_flip = true;
2694
+	adev_to_drm(adev)->mode_config.async_page_flip = true;
26542695 
2655
-	adev->ddev->mode_config.max_width = 16384;
2656
-	adev->ddev->mode_config.max_height = 16384;
2696
+	adev_to_drm(adev)->mode_config.max_width = 16384;
2697
+	adev_to_drm(adev)->mode_config.max_height = 16384;
26572698 
2658
-	adev->ddev->mode_config.preferred_depth = 24;
2659
-	adev->ddev->mode_config.prefer_shadow = 1;
2699
+	adev_to_drm(adev)->mode_config.preferred_depth = 24;
2700
+	adev_to_drm(adev)->mode_config.prefer_shadow = 1;
26602701 
2661
-	adev->ddev->mode_config.fb_base = adev->gmc.aper_base;
2702
+	adev_to_drm(adev)->mode_config.fb_base = adev->gmc.aper_base;
26622703 
26632704 	r = amdgpu_display_modeset_create_props(adev);
26642705 	if (r)
26652706 		return r;
26662707 
2667
-	adev->ddev->mode_config.max_width = 16384;
2668
-	adev->ddev->mode_config.max_height = 16384;
2708
+	adev_to_drm(adev)->mode_config.max_width = 16384;
2709
+	adev_to_drm(adev)->mode_config.max_height = 16384;
26692710 
26702711 	/* allocate crtcs */
26712712 	for (i = 0; i < adev->mode_info.num_crtc; i++) {
....@@ -2675,7 +2716,7 @@
26752716 	}
26762717 
26772718 	if (amdgpu_atombios_get_connector_info_from_object_table(adev))
2678
-		amdgpu_display_print_display_setup(adev->ddev);
2719
+		amdgpu_display_print_display_setup(adev_to_drm(adev));
26792720 	else
26802721 		return -EINVAL;
26812722 
....@@ -2688,7 +2729,7 @@
26882729 	if (r)
26892730 		return r;
26902731 
2691
-	drm_kms_helper_poll_init(adev->ddev);
2732
+	drm_kms_helper_poll_init(adev_to_drm(adev));
26922733 
26932734 	adev->mode_info.mode_config_initialized = true;
26942735 	return 0;
....@@ -2700,13 +2741,13 @@
27002741 
27012742 	kfree(adev->mode_info.bios_hardcoded_edid);
27022743 
2703
-	drm_kms_helper_poll_fini(adev->ddev);
2744
+	drm_kms_helper_poll_fini(adev_to_drm(adev));
27042745 
27052746 	dce_v8_0_audio_fini(adev);
27062747 
27072748 	dce_v8_0_afmt_fini(adev);
27082749 
2709
-	drm_mode_config_cleanup(adev->ddev);
2750
+	drm_mode_config_cleanup(adev_to_drm(adev));
27102751 	adev->mode_info.mode_config_initialized = false;
27112752 
27122753 	return 0;
....@@ -3016,7 +3057,7 @@
30163057 			DRM_DEBUG("IH: IH event w/o asserted irq bit?\n");
30173058 
30183059 		if (amdgpu_irq_enabled(adev, source, irq_type)) {
3019
-			drm_handle_vblank(adev->ddev, crtc);
3060
+			drm_handle_vblank(adev_to_drm(adev), crtc);
30203061 		}
30213062 		DRM_DEBUG("IH: D%d vblank\n", crtc + 1);
30223063 		break;
....@@ -3085,14 +3126,14 @@
30853126 	if (amdgpu_crtc == NULL)
30863127 		return 0;
30873128 
3088
-	spin_lock_irqsave(&adev->ddev->event_lock, flags);
3129
+	spin_lock_irqsave(&adev_to_drm(adev)->event_lock, flags);
30893130 	works = amdgpu_crtc->pflip_works;
30903131 	if (amdgpu_crtc->pflip_status != AMDGPU_FLIP_SUBMITTED){
30913132 		DRM_DEBUG_DRIVER("amdgpu_crtc->pflip_status = %d != "
30923133 						"AMDGPU_FLIP_SUBMITTED(%d)\n",
30933134 						amdgpu_crtc->pflip_status,
30943135 						AMDGPU_FLIP_SUBMITTED);
3095
-		spin_unlock_irqrestore(&adev->ddev->event_lock, flags);
3136
+		spin_unlock_irqrestore(&adev_to_drm(adev)->event_lock, flags);
30963137 		return 0;
30973138 	}
30983139 
....@@ -3104,7 +3145,7 @@
31043145 	if (works->event)
31053146 		drm_crtc_send_vblank_event(&amdgpu_crtc->base, works->event);
31063147 
3107
-	spin_unlock_irqrestore(&adev->ddev->event_lock, flags);
3148
+	spin_unlock_irqrestore(&adev_to_drm(adev)->event_lock, flags);
31083149 
31093150 	drm_crtc_vblank_put(&amdgpu_crtc->base);
31103151 	schedule_work(&works->unpin_work);
....@@ -3192,7 +3233,7 @@
31923233 
31933234 static void dce_v8_0_encoder_prepare(struct drm_encoder *encoder)
31943235 {
3195
-	struct amdgpu_device *adev = encoder->dev->dev_private;
3236
+	struct amdgpu_device *adev = drm_to_adev(encoder->dev);
31963237 	struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder);
31973238 	struct drm_connector *connector = amdgpu_get_connector_for_encoder(encoder);
31983239 
....@@ -3232,7 +3273,7 @@
32323273 static void dce_v8_0_encoder_commit(struct drm_encoder *encoder)
32333274 {
32343275 	struct drm_device *dev = encoder->dev;
3235
-	struct amdgpu_device *adev = dev->dev_private;
3276
+	struct amdgpu_device *adev = drm_to_adev(dev);
32363277 
32373278 	/* need to call this here as we need the crtc set up */
32383279 	amdgpu_atombios_encoder_dpms(encoder, DRM_MODE_DPMS_ON);
....@@ -3332,7 +3373,7 @@
33323373 				 uint32_t supported_device,
33333374 				 u16 caps)
33343375 {
3335
-	struct drm_device *dev = adev->ddev;
3376
+	struct drm_device *dev = adev_to_drm(adev);
33363377 	struct drm_encoder *encoder;
33373378 	struct amdgpu_encoder *amdgpu_encoder;
33383379 
....@@ -3447,8 +3488,7 @@
34473488 
34483489 static void dce_v8_0_set_display_funcs(struct amdgpu_device *adev)
34493490 {
3450
-	if (adev->mode_info.funcs == NULL)
3451
-		adev->mode_info.funcs = &dce_v8_0_display_funcs;
3491
+	adev->mode_info.funcs = &dce_v8_0_display_funcs;
34523492 }
34533493 
34543494 static const struct amdgpu_irq_src_funcs dce_v8_0_crtc_irq_funcs = {