change wifi driver to cypress

hc

2024-01-05 071106ecf68c401173c58808b1cf5f68cc50d390

 kernel/drivers/gpu/drm/amd/amdgpu/amdgpu_ring.h
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@@ -29,11 +29,15 @@
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 #include <drm/drm_print.h>
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 /* max number of rings */
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-#define AMDGPU_MAX_RINGS		21
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-#define AMDGPU_MAX_GFX_RINGS		1
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+#define AMDGPU_MAX_RINGS		28
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+#define AMDGPU_MAX_HWIP_RINGS		8
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+#define AMDGPU_MAX_GFX_RINGS		2
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 #define AMDGPU_MAX_COMPUTE_RINGS	8
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 #define AMDGPU_MAX_VCE_RINGS		3
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 #define AMDGPU_MAX_UVD_ENC_RINGS	2
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+
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+#define AMDGPU_RING_PRIO_DEFAULT	1
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+#define AMDGPU_RING_PRIO_MAX		AMDGPU_GFX_PIPE_PRIO_MAX
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 /* some special values for the owner field */
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 #define AMDGPU_FENCE_OWNER_UNDEFINED	((void *)0ul)
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@@ -46,17 +50,31 @@
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 #define to_amdgpu_ring(s) container_of((s), struct amdgpu_ring, sched)
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+#define AMDGPU_IB_POOL_SIZE	(1024 * 1024)
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+
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 enum amdgpu_ring_type {
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-	AMDGPU_RING_TYPE_GFX,
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-	AMDGPU_RING_TYPE_COMPUTE,
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-	AMDGPU_RING_TYPE_SDMA,
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-	AMDGPU_RING_TYPE_UVD,
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-	AMDGPU_RING_TYPE_VCE,
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+	AMDGPU_RING_TYPE_GFX		= AMDGPU_HW_IP_GFX,
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+	AMDGPU_RING_TYPE_COMPUTE	= AMDGPU_HW_IP_COMPUTE,
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+	AMDGPU_RING_TYPE_SDMA		= AMDGPU_HW_IP_DMA,
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+	AMDGPU_RING_TYPE_UVD		= AMDGPU_HW_IP_UVD,
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+	AMDGPU_RING_TYPE_VCE		= AMDGPU_HW_IP_VCE,
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+	AMDGPU_RING_TYPE_UVD_ENC	= AMDGPU_HW_IP_UVD_ENC,
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+	AMDGPU_RING_TYPE_VCN_DEC	= AMDGPU_HW_IP_VCN_DEC,
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+	AMDGPU_RING_TYPE_VCN_ENC	= AMDGPU_HW_IP_VCN_ENC,
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+	AMDGPU_RING_TYPE_VCN_JPEG	= AMDGPU_HW_IP_VCN_JPEG,
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 	AMDGPU_RING_TYPE_KIQ,
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-	AMDGPU_RING_TYPE_UVD_ENC,
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-	AMDGPU_RING_TYPE_VCN_DEC,
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-	AMDGPU_RING_TYPE_VCN_ENC,
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-	AMDGPU_RING_TYPE_VCN_JPEG
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+	AMDGPU_RING_TYPE_MES
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+};
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+
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+enum amdgpu_ib_pool_type {
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+	/* Normal submissions to the top of the pipeline. */
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+	AMDGPU_IB_POOL_DELAYED,
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+	/* Immediate submissions to the bottom of the pipeline. */
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+	AMDGPU_IB_POOL_IMMEDIATE,
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+	/* Direct submission to the ring buffer during init and reset. */
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+	AMDGPU_IB_POOL_DIRECT,
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+
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+	AMDGPU_IB_POOL_MAX
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 };
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 struct amdgpu_device;
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@@ -64,6 +82,11 @@
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 struct amdgpu_ib;
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 struct amdgpu_cs_parser;
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 struct amdgpu_job;
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+
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+struct amdgpu_sched {
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+	u32				num_scheds;
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+	struct drm_gpu_scheduler	*sched[AMDGPU_MAX_HWIP_RINGS];
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+};
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 /*
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  * Fences.
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@@ -96,8 +119,9 @@
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 void amdgpu_fence_driver_resume(struct amdgpu_device *adev);
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 int amdgpu_fence_emit(struct amdgpu_ring *ring, struct dma_fence **fence,
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 		      unsigned flags);
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-int amdgpu_fence_emit_polling(struct amdgpu_ring *ring, uint32_t *s);
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-void amdgpu_fence_process(struct amdgpu_ring *ring);
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+int amdgpu_fence_emit_polling(struct amdgpu_ring *ring, uint32_t *s,
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+			      uint32_t timeout);
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+bool amdgpu_fence_process(struct amdgpu_ring *ring);
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 int amdgpu_fence_wait_empty(struct amdgpu_ring *ring);
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 signed long amdgpu_fence_wait_polling(struct amdgpu_ring *ring,
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 				      uint32_t wait_seq,
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@@ -114,6 +138,7 @@
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 	uint32_t		align_mask;
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 	u32			nop;
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 	bool			support_64bit_ptrs;
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+	bool			no_user_fence;
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 	unsigned		vmhub;
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 	unsigned		extra_dw;
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@@ -129,8 +154,9 @@
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 	unsigned emit_ib_size;
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 	/* command emit functions */
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 	void (*emit_ib)(struct amdgpu_ring *ring,
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+			struct amdgpu_job *job,
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 			struct amdgpu_ib *ib,
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-			unsigned vmid, bool ctx_switch);
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+			uint32_t flags);
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 	void (*emit_fence)(struct amdgpu_ring *ring, uint64_t addr,
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 			   uint64_t seq, unsigned flags);
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 	void (*emit_pipeline_sync)(struct amdgpu_ring *ring);
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@@ -157,17 +183,20 @@
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 	void (*end_use)(struct amdgpu_ring *ring);
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 	void (*emit_switch_buffer) (struct amdgpu_ring *ring);
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 	void (*emit_cntxcntl) (struct amdgpu_ring *ring, uint32_t flags);
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-	void (*emit_rreg)(struct amdgpu_ring *ring, uint32_t reg);
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+	void (*emit_rreg)(struct amdgpu_ring *ring, uint32_t reg,
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+			  uint32_t reg_val_offs);
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 	void (*emit_wreg)(struct amdgpu_ring *ring, uint32_t reg, uint32_t val);
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 	void (*emit_reg_wait)(struct amdgpu_ring *ring, uint32_t reg,
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 			      uint32_t val, uint32_t mask);
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 	void (*emit_reg_write_reg_wait)(struct amdgpu_ring *ring,
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 					uint32_t reg0, uint32_t reg1,
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 					uint32_t ref, uint32_t mask);
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-	void (*emit_tmz)(struct amdgpu_ring *ring, bool start);
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-	/* priority functions */
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-	void (*set_priority) (struct amdgpu_ring *ring,
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-			      enum drm_sched_priority priority);
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+	void (*emit_frame_cntl)(struct amdgpu_ring *ring, bool start,
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+				bool secure);
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+	/* Try to soft recover the ring to make the fence signal */
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+	void (*soft_recovery)(struct amdgpu_ring *ring, unsigned vmid);
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+	int (*preempt_ib)(struct amdgpu_ring *ring);
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+	void (*emit_mem_sync)(struct amdgpu_ring *ring);
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 };
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 struct amdgpu_ring {
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@@ -175,7 +204,6 @@
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 	const struct amdgpu_ring_funcs	*funcs;
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 	struct amdgpu_fence_driver	fence_drv;
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 	struct drm_gpu_scheduler	sched;
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-	struct list_head		lru_list;
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 	struct amdgpu_bo	*ring_obj;
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 	volatile uint32_t	*ring;
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@@ -188,7 +216,6 @@
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 	uint64_t		gpu_addr;
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 	uint64_t		ptr_mask;
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 	uint32_t		buf_mask;
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-	bool			ready;
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 	u32			idx;
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 	u32			me;
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 	u32			pipe;
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@@ -204,14 +231,19 @@
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 	unsigned		fence_offs;
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 	uint64_t		current_ctx;
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 	char			name[16];
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+	u32                     trail_seq;
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+	unsigned		trail_fence_offs;
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+	u64			trail_fence_gpu_addr;
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+	volatile u32		*trail_fence_cpu_addr;
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 	unsigned		cond_exe_offs;
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 	u64			cond_exe_gpu_addr;
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 	volatile u32		*cond_exe_cpu_addr;
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 	unsigned		vm_inv_eng;
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 	struct dma_fence	*vmid_wait;
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 	bool			has_compute_vm_bug;
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+	bool			no_scheduler;
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-	atomic_t		num_jobs[DRM_SCHED_PRIORITY_MAX];
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+	atomic_t		num_jobs[DRM_SCHED_PRIORITY_COUNT];
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 	struct mutex		priority_mutex;
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 	/* protected by priority_mutex */
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 	int			priority;
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@@ -221,26 +253,51 @@
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 #endif
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 };
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+#define amdgpu_ring_parse_cs(r, p, ib) ((r)->funcs->parse_cs((p), (ib)))
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+#define amdgpu_ring_patch_cs_in_place(r, p, ib) ((r)->funcs->patch_cs_in_place((p), (ib)))
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+#define amdgpu_ring_test_ring(r) (r)->funcs->test_ring((r))
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+#define amdgpu_ring_test_ib(r, t) (r)->funcs->test_ib((r), (t))
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+#define amdgpu_ring_get_rptr(r) (r)->funcs->get_rptr((r))
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+#define amdgpu_ring_get_wptr(r) (r)->funcs->get_wptr((r))
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+#define amdgpu_ring_set_wptr(r) (r)->funcs->set_wptr((r))
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+#define amdgpu_ring_emit_ib(r, job, ib, flags) ((r)->funcs->emit_ib((r), (job), (ib), (flags)))
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+#define amdgpu_ring_emit_pipeline_sync(r) (r)->funcs->emit_pipeline_sync((r))
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+#define amdgpu_ring_emit_vm_flush(r, vmid, addr) (r)->funcs->emit_vm_flush((r), (vmid), (addr))
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+#define amdgpu_ring_emit_fence(r, addr, seq, flags) (r)->funcs->emit_fence((r), (addr), (seq), (flags))
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+#define amdgpu_ring_emit_gds_switch(r, v, db, ds, wb, ws, ab, as) (r)->funcs->emit_gds_switch((r), (v), (db), (ds), (wb), (ws), (ab), (as))
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+#define amdgpu_ring_emit_hdp_flush(r) (r)->funcs->emit_hdp_flush((r))
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+#define amdgpu_ring_emit_switch_buffer(r) (r)->funcs->emit_switch_buffer((r))
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+#define amdgpu_ring_emit_cntxcntl(r, d) (r)->funcs->emit_cntxcntl((r), (d))
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+#define amdgpu_ring_emit_rreg(r, d, o) (r)->funcs->emit_rreg((r), (d), (o))
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+#define amdgpu_ring_emit_wreg(r, d, v) (r)->funcs->emit_wreg((r), (d), (v))
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+#define amdgpu_ring_emit_reg_wait(r, d, v, m) (r)->funcs->emit_reg_wait((r), (d), (v), (m))
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+#define amdgpu_ring_emit_reg_write_reg_wait(r, d0, d1, v, m) (r)->funcs->emit_reg_write_reg_wait((r), (d0), (d1), (v), (m))
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+#define amdgpu_ring_emit_frame_cntl(r, b, s) (r)->funcs->emit_frame_cntl((r), (b), (s))
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+#define amdgpu_ring_pad_ib(r, ib) ((r)->funcs->pad_ib((r), (ib)))
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+#define amdgpu_ring_init_cond_exec(r) (r)->funcs->init_cond_exec((r))
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+#define amdgpu_ring_patch_cond_exec(r,o) (r)->funcs->patch_cond_exec((r),(o))
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+#define amdgpu_ring_preempt_ib(r) (r)->funcs->preempt_ib(r)
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+
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 int amdgpu_ring_alloc(struct amdgpu_ring *ring, unsigned ndw);
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 void amdgpu_ring_insert_nop(struct amdgpu_ring *ring, uint32_t count);
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 void amdgpu_ring_generic_pad_ib(struct amdgpu_ring *ring, struct amdgpu_ib *ib);
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 void amdgpu_ring_commit(struct amdgpu_ring *ring);
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 void amdgpu_ring_undo(struct amdgpu_ring *ring);
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-void amdgpu_ring_priority_get(struct amdgpu_ring *ring,
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-			      enum drm_sched_priority priority);
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-void amdgpu_ring_priority_put(struct amdgpu_ring *ring,
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-			      enum drm_sched_priority priority);
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 int amdgpu_ring_init(struct amdgpu_device *adev, struct amdgpu_ring *ring,
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-		     unsigned ring_size, struct amdgpu_irq_src *irq_src,
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-		     unsigned irq_type);
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+		     unsigned int ring_size, struct amdgpu_irq_src *irq_src,
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+		     unsigned int irq_type, unsigned int prio);
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 void amdgpu_ring_fini(struct amdgpu_ring *ring);
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-int amdgpu_ring_lru_get(struct amdgpu_device *adev, int type,
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-			int *blacklist, int num_blacklist,
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-			bool lru_pipe_order, struct amdgpu_ring **ring);
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-void amdgpu_ring_lru_touch(struct amdgpu_device *adev, struct amdgpu_ring *ring);
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 void amdgpu_ring_emit_reg_write_reg_wait_helper(struct amdgpu_ring *ring,
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 						uint32_t reg0, uint32_t val0,
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 						uint32_t reg1, uint32_t val1);
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+bool amdgpu_ring_soft_recovery(struct amdgpu_ring *ring, unsigned int vmid,
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+			       struct dma_fence *fence);
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+
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+static inline void amdgpu_ring_set_preempt_cond_exec(struct amdgpu_ring *ring,
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+							bool cond_exec)
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+{
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+	*ring->cond_exe_cpu_addr = cond_exec;
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+}
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 static inline void amdgpu_ring_clear_ring(struct amdgpu_ring *ring)
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 {
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@@ -290,4 +347,10 @@
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 	ring->count_dw -= count_dw;
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 }
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+int amdgpu_ring_test_helper(struct amdgpu_ring *ring);
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+
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+int amdgpu_debugfs_ring_init(struct amdgpu_device *adev,
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+			     struct amdgpu_ring *ring);
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+void amdgpu_debugfs_ring_fini(struct amdgpu_ring *ring);
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+
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 #endif