| .. | .. |
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| 25 | 25 | #define __AMDGPU_IRQ_H__ |
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| 26 | 26 | |
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| 27 | 27 | #include <linux/irqdomain.h> |
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| 28 | +#include "soc15_ih_clientid.h" |
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| 28 | 29 | #include "amdgpu_ih.h" |
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| 29 | 30 | |
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| 30 | | -#define AMDGPU_MAX_IRQ_SRC_ID 0x100 |
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| 31 | +#define AMDGPU_MAX_IRQ_SRC_ID 0x100 |
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| 31 | 32 | #define AMDGPU_MAX_IRQ_CLIENT_ID 0x100 |
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| 32 | 33 | |
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| 34 | +#define AMDGPU_IRQ_CLIENTID_LEGACY 0 |
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| 35 | +#define AMDGPU_IRQ_CLIENTID_MAX SOC15_IH_CLIENTID_MAX |
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| 36 | + |
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| 37 | +#define AMDGPU_IRQ_SRC_DATA_MAX_SIZE_DW 4 |
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| 38 | + |
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| 33 | 39 | struct amdgpu_device; |
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| 34 | | -struct amdgpu_iv_entry; |
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| 35 | 40 | |
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| 36 | 41 | enum amdgpu_interrupt_state { |
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| 37 | 42 | AMDGPU_IRQ_STATE_DISABLE, |
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| 38 | 43 | AMDGPU_IRQ_STATE_ENABLE, |
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| 44 | +}; |
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| 45 | + |
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| 46 | +struct amdgpu_iv_entry { |
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| 47 | + unsigned client_id; |
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| 48 | + unsigned src_id; |
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| 49 | + unsigned ring_id; |
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| 50 | + unsigned vmid; |
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| 51 | + unsigned vmid_src; |
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| 52 | + uint64_t timestamp; |
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| 53 | + unsigned timestamp_src; |
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| 54 | + unsigned pasid; |
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| 55 | + unsigned pasid_src; |
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| 56 | + unsigned src_data[AMDGPU_IRQ_SRC_DATA_MAX_SIZE_DW]; |
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| 57 | + const uint32_t *iv_entry; |
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| 39 | 58 | }; |
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| 40 | 59 | |
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| 41 | 60 | struct amdgpu_irq_src { |
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| .. | .. |
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| 63 | 82 | bool installed; |
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| 64 | 83 | spinlock_t lock; |
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| 65 | 84 | /* interrupt sources */ |
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| 66 | | - struct amdgpu_irq_client client[AMDGPU_IH_CLIENTID_MAX]; |
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| 85 | + struct amdgpu_irq_client client[AMDGPU_IRQ_CLIENTID_MAX]; |
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| 67 | 86 | |
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| 68 | 87 | /* status, etc. */ |
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| 69 | 88 | bool msi_enabled; /* msi enabled */ |
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| 70 | 89 | |
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| 71 | | - /* interrupt ring */ |
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| 72 | | - struct amdgpu_ih_ring ih; |
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| 73 | | - const struct amdgpu_ih_funcs *ih_funcs; |
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| 90 | + /* interrupt rings */ |
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| 91 | + struct amdgpu_ih_ring ih, ih1, ih2; |
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| 92 | + const struct amdgpu_ih_funcs *ih_funcs; |
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| 93 | + struct work_struct ih1_work, ih2_work; |
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| 94 | + struct amdgpu_irq_src self_irq; |
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| 74 | 95 | |
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| 75 | 96 | /* gen irq stuff */ |
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| 76 | 97 | struct irq_domain *domain; /* GPU irq controller domain */ |
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| .. | .. |
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| 87 | 108 | unsigned client_id, unsigned src_id, |
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| 88 | 109 | struct amdgpu_irq_src *source); |
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| 89 | 110 | void amdgpu_irq_dispatch(struct amdgpu_device *adev, |
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| 90 | | - struct amdgpu_iv_entry *entry); |
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| 111 | + struct amdgpu_ih_ring *ih); |
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| 91 | 112 | int amdgpu_irq_update(struct amdgpu_device *adev, struct amdgpu_irq_src *src, |
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| 92 | 113 | unsigned type); |
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| 93 | 114 | int amdgpu_irq_get(struct amdgpu_device *adev, struct amdgpu_irq_src *src, |
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