.. | .. |
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259 | 259 | return a & ((1 << 16) - 1); |
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260 | 260 | } |
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261 | 261 | |
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262 | | -static inline u32 i5100_redmemb_ecc_locator(u32 a) |
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263 | | -{ |
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264 | | - return a & ((1 << 18) - 1); |
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265 | | -} |
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266 | | - |
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267 | 262 | static inline u32 i5100_recmema_merr(u32 a) |
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268 | 263 | { |
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269 | 264 | return i5100_nrecmema_merr(a); |
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.. | .. |
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417 | 412 | } |
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418 | 413 | |
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419 | 414 | /* convert csrow index into a rank (per channel -- 0..5) */ |
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420 | | -static int i5100_csrow_to_rank(const struct mem_ctl_info *mci, int csrow) |
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| 415 | +static unsigned int i5100_csrow_to_rank(const struct mem_ctl_info *mci, |
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| 416 | + unsigned int csrow) |
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421 | 417 | { |
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422 | 418 | const struct i5100_priv *priv = mci->pvt_info; |
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423 | 419 | |
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.. | .. |
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425 | 421 | } |
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426 | 422 | |
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427 | 423 | /* convert csrow index into a channel (0..1) */ |
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428 | | -static int i5100_csrow_to_chan(const struct mem_ctl_info *mci, int csrow) |
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| 424 | +static unsigned int i5100_csrow_to_chan(const struct mem_ctl_info *mci, |
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| 425 | + unsigned int csrow) |
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429 | 426 | { |
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430 | 427 | const struct i5100_priv *priv = mci->pvt_info; |
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431 | 428 | |
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.. | .. |
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484 | 481 | u32 dw; |
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485 | 482 | u32 dw2; |
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486 | 483 | unsigned syndrome = 0; |
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487 | | - unsigned ecc_loc = 0; |
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488 | 484 | unsigned merr; |
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489 | 485 | unsigned bank; |
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490 | 486 | unsigned rank; |
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.. | .. |
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497 | 493 | pci_read_config_dword(pdev, I5100_REDMEMA, &dw2); |
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498 | 494 | syndrome = dw2; |
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499 | 495 | pci_read_config_dword(pdev, I5100_REDMEMB, &dw2); |
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500 | | - ecc_loc = i5100_redmemb_ecc_locator(dw2); |
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501 | 496 | } |
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502 | 497 | |
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503 | 498 | if (i5100_validlog_recmemvalid(dw)) { |
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.. | .. |
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653 | 648 | return ret; |
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654 | 649 | } |
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655 | 650 | |
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656 | | -static unsigned long i5100_npages(struct mem_ctl_info *mci, int csrow) |
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| 651 | +static unsigned long i5100_npages(struct mem_ctl_info *mci, unsigned int csrow) |
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657 | 652 | { |
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658 | 653 | struct i5100_priv *priv = mci->pvt_info; |
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659 | | - const unsigned chan_rank = i5100_csrow_to_rank(mci, csrow); |
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660 | | - const unsigned chan = i5100_csrow_to_chan(mci, csrow); |
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| 654 | + const unsigned int chan_rank = i5100_csrow_to_rank(mci, csrow); |
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| 655 | + const unsigned int chan = i5100_csrow_to_chan(mci, csrow); |
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661 | 656 | unsigned addr_lines; |
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662 | 657 | |
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663 | 658 | /* dimm present? */ |
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.. | .. |
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711 | 706 | { |
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712 | 707 | struct i5100_priv *priv = mci->pvt_info; |
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713 | 708 | u16 w; |
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714 | | - unsigned long et; |
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715 | 709 | |
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716 | 710 | pci_read_config_word(priv->mc, I5100_SPDDATA, &w); |
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717 | 711 | if (i5100_spddata_busy(w)) |
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.. | .. |
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722 | 716 | 0, 0)); |
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723 | 717 | |
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724 | 718 | /* wait up to 100ms */ |
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725 | | - et = jiffies + HZ / 10; |
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726 | 719 | udelay(100); |
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727 | 720 | while (1) { |
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728 | 721 | pci_read_config_word(priv->mc, I5100_SPDDATA, &w); |
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.. | .. |
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846 | 839 | |
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847 | 840 | static void i5100_init_csrows(struct mem_ctl_info *mci) |
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848 | 841 | { |
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849 | | - int i; |
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850 | 842 | struct i5100_priv *priv = mci->pvt_info; |
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| 843 | + struct dimm_info *dimm; |
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851 | 844 | |
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852 | | - for (i = 0; i < mci->tot_dimms; i++) { |
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853 | | - struct dimm_info *dimm; |
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854 | | - const unsigned long npages = i5100_npages(mci, i); |
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855 | | - const unsigned chan = i5100_csrow_to_chan(mci, i); |
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856 | | - const unsigned rank = i5100_csrow_to_rank(mci, i); |
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| 845 | + mci_for_each_dimm(mci, dimm) { |
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| 846 | + const unsigned long npages = i5100_npages(mci, dimm->idx); |
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| 847 | + const unsigned int chan = i5100_csrow_to_chan(mci, dimm->idx); |
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| 848 | + const unsigned int rank = i5100_csrow_to_rank(mci, dimm->idx); |
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857 | 849 | |
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858 | 850 | if (!npages) |
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859 | 851 | continue; |
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860 | | - |
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861 | | - dimm = EDAC_DIMM_PTR(mci->layers, mci->dimms, mci->n_layers, |
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862 | | - chan, rank, 0); |
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863 | 852 | |
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864 | 853 | dimm->nr_pages = npages; |
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865 | 854 | dimm->grain = 32; |
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