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2024-01-05 071106ecf68c401173c58808b1cf5f68cc50d390 
 kernel/drivers/dma/dw/core.c
....@@ -1,13 +1,10 @@
1
+// SPDX-License-Identifier: GPL-2.0
12 /*
23  * Core driver for the Synopsys DesignWare DMA Controller
34  *
45  * Copyright (C) 2007-2008 Atmel Corporation
56  * Copyright (C) 2010-2011 ST Microelectronics
67  * Copyright (C) 2013 Intel Corporation
7
- *
8
- * This program is free software; you can redistribute it and/or modify
9
- * it under the terms of the GNU General Public License version 2 as
10
- * published by the Free Software Foundation.
118  */
129 
1310 #include <linux/bitops.h>
....@@ -36,27 +33,6 @@
3633  * The driver has been tested with the Atmel AT32AP7000, which does not
3734  * support descriptor writeback.
3835  */
39
-
40
-#define DWC_DEFAULT_CTLLO(_chan) ({				\
41
-		struct dw_dma_chan *_dwc = to_dw_dma_chan(_chan);	\
42
-		struct dma_slave_config	*_sconfig = &_dwc->dma_sconfig;	\
43
-		bool _is_slave = is_slave_direction(_dwc->direction);	\
44
-		u8 _smsize = _is_slave ? _sconfig->src_maxburst :	\
45
-			DW_DMA_MSIZE_16;			\
46
-		u8 _dmsize = _is_slave ? _sconfig->dst_maxburst :	\
47
-			DW_DMA_MSIZE_16;			\
48
-		u8 _dms = (_dwc->direction == DMA_MEM_TO_DEV) ?		\
49
-			_dwc->dws.p_master : _dwc->dws.m_master;	\
50
-		u8 _sms = (_dwc->direction == DMA_DEV_TO_MEM) ?		\
51
-			_dwc->dws.p_master : _dwc->dws.m_master;	\
52
-								\
53
-		(DWC_CTLL_DST_MSIZE(_dmsize)			\
54
-		 | DWC_CTLL_SRC_MSIZE(_smsize)			\
55
-		 | DWC_CTLL_LLP_D_EN				\
56
-		 | DWC_CTLL_LLP_S_EN				\
57
-		 | DWC_CTLL_DMS(_dms)				\
58
-		 | DWC_CTLL_SMS(_sms));				\
59
-	})
6036 
6137 /* The set of bus widths supported by the DMA controller */
6238 #define DW_DMA_BUSWIDTHS			  \
....@@ -138,61 +114,15 @@
138114 	dwc->descs_allocated--;
139115 }
140116 
141
-static void dwc_initialize_chan_idma32(struct dw_dma_chan *dwc)
142
-{
143
-	u32 cfghi = 0;
144
-	u32 cfglo = 0;
145
-
146
-	/* Set default burst alignment */
147
-	cfglo |= IDMA32C_CFGL_DST_BURST_ALIGN | IDMA32C_CFGL_SRC_BURST_ALIGN;
148
-
149
-	/* Low 4 bits of the request lines */
150
-	cfghi |= IDMA32C_CFGH_DST_PER(dwc->dws.dst_id & 0xf);
151
-	cfghi |= IDMA32C_CFGH_SRC_PER(dwc->dws.src_id & 0xf);
152
-
153
-	/* Request line extension (2 bits) */
154
-	cfghi |= IDMA32C_CFGH_DST_PER_EXT(dwc->dws.dst_id >> 4 & 0x3);
155
-	cfghi |= IDMA32C_CFGH_SRC_PER_EXT(dwc->dws.src_id >> 4 & 0x3);
156
-
157
-	channel_writel(dwc, CFG_LO, cfglo);
158
-	channel_writel(dwc, CFG_HI, cfghi);
159
-}
160
-
161
-static void dwc_initialize_chan_dw(struct dw_dma_chan *dwc)
162
-{
163
-	struct dw_dma *dw = to_dw_dma(dwc->chan.device);
164
-	u32 cfghi = DWC_CFGH_FIFO_MODE;
165
-	u32 cfglo = DWC_CFGL_CH_PRIOR(dwc->priority);
166
-	bool hs_polarity = dwc->dws.hs_polarity;
167
-
168
-	cfghi |= DWC_CFGH_DST_PER(dwc->dws.dst_id);
169
-	cfghi |= DWC_CFGH_SRC_PER(dwc->dws.src_id);
170
-	cfghi |= DWC_CFGH_PROTCTL(dw->pdata->protctl);
171
-
172
-	/* Set polarity of handshake interface */
173
-	cfglo |= hs_polarity ? DWC_CFGL_HS_DST_POL | DWC_CFGL_HS_SRC_POL : 0;
174
-
175
-	channel_writel(dwc, CFG_LO, cfglo);
176
-	channel_writel(dwc, CFG_HI, cfghi);
177
-}
178
-
179117 static void dwc_initialize(struct dw_dma_chan *dwc)
180118 {
181119 	struct dw_dma *dw = to_dw_dma(dwc->chan.device);
182120 
183
-	if (test_bit(DW_DMA_IS_INITIALIZED, &dwc->flags))
184
-		return;
185
-
186
-	if (dw->pdata->is_idma32)
187
-		dwc_initialize_chan_idma32(dwc);
188
-	else
189
-		dwc_initialize_chan_dw(dwc);
121
+	dw->initialize_chan(dwc);
190122 
191123 	/* Enable interrupts */
192124 	channel_set_bit(dw, MASK.XFER, dwc->mask);
193125 	channel_set_bit(dw, MASK.ERROR, dwc->mask);
194
-
195
-	set_bit(DW_DMA_IS_INITIALIZED, &dwc->flags);
196126 }
197127 
198128 /*----------------------------------------------------------------------*/
....@@ -213,37 +143,6 @@
213143 	channel_clear_bit(dw, CH_EN, dwc->mask);
214144 	while (dma_readl(dw, CH_EN) & dwc->mask)
215145 		cpu_relax();
216
-}
217
-
218
-static u32 bytes2block(struct dw_dma_chan *dwc, size_t bytes,
219
-			  unsigned int width, size_t *len)
220
-{
221
-	struct dw_dma *dw = to_dw_dma(dwc->chan.device);
222
-	u32 block;
223
-
224
-	/* Always in bytes for iDMA 32-bit */
225
-	if (dw->pdata->is_idma32)
226
-		width = 0;
227
-
228
-	if ((bytes >> width) > dwc->block_size) {
229
-		block = dwc->block_size;
230
-		*len = block << width;
231
-	} else {
232
-		block = bytes >> width;
233
-		*len = bytes;
234
-	}
235
-
236
-	return block;
237
-}
238
-
239
-static size_t block2bytes(struct dw_dma_chan *dwc, u32 block, u32 width)
240
-{
241
-	struct dw_dma *dw = to_dw_dma(dwc->chan.device);
242
-
243
-	if (dw->pdata->is_idma32)
244
-		return IDMA32C_CTLH_BLOCK_TS(block);
245
-
246
-	return DWC_CTLH_BLOCK_TS(block) << width;
247146 }
248147 
249148 /*----------------------------------------------------------------------*/
....@@ -391,10 +290,11 @@
391290 /* Returns how many bytes were already received from source */
392291 static inline u32 dwc_get_sent(struct dw_dma_chan *dwc)
393292 {
293
+	struct dw_dma *dw = to_dw_dma(dwc->chan.device);
394294 	u32 ctlhi = channel_readl(dwc, CTL_HI);
395295 	u32 ctllo = channel_readl(dwc, CTL_LO);
396296 
397
-	return block2bytes(dwc, ctlhi, ctllo >> 4 & 7);
297
+	return dw->block2bytes(dwc, ctlhi, ctllo >> 4 & 7);
398298 }
399299 
400300 static void dwc_scan_descriptors(struct dw_dma *dw, struct dw_dma_chan *dwc)
....@@ -563,9 +463,9 @@
563463 	dwc_descriptor_complete(dwc, bad_desc, true);
564464 }
565465 
566
-static void dw_dma_tasklet(unsigned long data)
466
+static void dw_dma_tasklet(struct tasklet_struct *t)
567467 {
568
-	struct dw_dma *dw = (struct dw_dma *)data;
468
+	struct dw_dma *dw = from_tasklet(dw, t, tasklet);
569469 	struct dw_dma_chan *dwc;
570470 	u32 status_xfer;
571471 	u32 status_err;
....@@ -651,7 +551,7 @@
651551 	unsigned int		src_width;
652552 	unsigned int		dst_width;
653553 	unsigned int		data_width = dw->pdata->data_width[m_master];
654
-	u32			ctllo;
554
+	u32			ctllo, ctlhi;
655555 	u8			lms = DWC_LLP_LMS(m_master);
656556 
657557 	dev_vdbg(chan2dev(chan),
....@@ -667,7 +567,7 @@
667567 
668568 	src_width = dst_width = __ffs(data_width | src | dest | len);
669569 
670
-	ctllo = DWC_DEFAULT_CTLLO(chan)
570
+	ctllo = dw->prepare_ctllo(dwc)
671571 			| DWC_CTLL_DST_WIDTH(dst_width)
672572 			| DWC_CTLL_SRC_WIDTH(src_width)
673573 			| DWC_CTLL_DST_INC
....@@ -680,10 +580,12 @@
680580 		if (!desc)
681581 			goto err_desc_get;
682582 
583
+		ctlhi = dw->bytes2block(dwc, len - offset, src_width, &xfer_count);
584
+
683585 		lli_write(desc, sar, src + offset);
684586 		lli_write(desc, dar, dest + offset);
685587 		lli_write(desc, ctllo, ctllo);
686
-		lli_write(desc, ctlhi, bytes2block(dwc, len - offset, src_width, &xfer_count));
588
+		lli_write(desc, ctlhi, ctlhi);
687589 		desc->len = xfer_count;
688590 
689591 		if (!first) {
....@@ -721,7 +623,7 @@
721623 	struct dma_slave_config	*sconfig = &dwc->dma_sconfig;
722624 	struct dw_desc		*prev;
723625 	struct dw_desc		*first;
724
-	u32			ctllo;
626
+	u32			ctllo, ctlhi;
725627 	u8			m_master = dwc->dws.m_master;
726628 	u8			lms = DWC_LLP_LMS(m_master);
727629 	dma_addr_t		reg;
....@@ -745,10 +647,10 @@
745647 	case DMA_MEM_TO_DEV:
746648 		reg_width = __ffs(sconfig->dst_addr_width);
747649 		reg = sconfig->dst_addr;
748
-		ctllo = (DWC_DEFAULT_CTLLO(chan)
650
+		ctllo = dw->prepare_ctllo(dwc)
749651 				| DWC_CTLL_DST_WIDTH(reg_width)
750652 				| DWC_CTLL_DST_FIX
751
-				| DWC_CTLL_SRC_INC);
653
+				| DWC_CTLL_SRC_INC;
752654 
753655 		ctllo |= sconfig->device_fc ? DWC_CTLL_FC(DW_DMA_FC_P_M2P) :
754656 			DWC_CTLL_FC(DW_DMA_FC_D_M2P);
....@@ -768,9 +670,11 @@
768670 			if (!desc)
769671 				goto err_desc_get;
770672 
673
+			ctlhi = dw->bytes2block(dwc, len, mem_width, &dlen);
674
+
771675 			lli_write(desc, sar, mem);
772676 			lli_write(desc, dar, reg);
773
-			lli_write(desc, ctlhi, bytes2block(dwc, len, mem_width, &dlen));
677
+			lli_write(desc, ctlhi, ctlhi);
774678 			lli_write(desc, ctllo, ctllo | DWC_CTLL_SRC_WIDTH(mem_width));
775679 			desc->len = dlen;
776680 
....@@ -793,10 +697,10 @@
793697 	case DMA_DEV_TO_MEM:
794698 		reg_width = __ffs(sconfig->src_addr_width);
795699 		reg = sconfig->src_addr;
796
-		ctllo = (DWC_DEFAULT_CTLLO(chan)
700
+		ctllo = dw->prepare_ctllo(dwc)
797701 				| DWC_CTLL_SRC_WIDTH(reg_width)
798702 				| DWC_CTLL_DST_INC
799
-				| DWC_CTLL_SRC_FIX);
703
+				| DWC_CTLL_SRC_FIX;
800704 
801705 		ctllo |= sconfig->device_fc ? DWC_CTLL_FC(DW_DMA_FC_P_P2M) :
802706 			DWC_CTLL_FC(DW_DMA_FC_D_P2M);
....@@ -814,10 +718,12 @@
814718 			if (!desc)
815719 				goto err_desc_get;
816720 
721
+			ctlhi = dw->bytes2block(dwc, len, reg_width, &dlen);
722
+
817723 			lli_write(desc, sar, reg);
818724 			lli_write(desc, dar, mem);
819
-			lli_write(desc, ctlhi, bytes2block(dwc, len, reg_width, &dlen));
820
-			mem_width = __ffs(data_width | mem | dlen);
725
+			lli_write(desc, ctlhi, ctlhi);
726
+			mem_width = __ffs(data_width | mem);
821727 			lli_write(desc, ctllo, ctllo | DWC_CTLL_DST_WIDTH(mem_width));
822728 			desc->len = dlen;
823729 
....@@ -866,6 +772,10 @@
866772 	if (dws->dma_dev != chan->device->dev)
867773 		return false;
868774 
775
+	/* permit channels in accordance with the channels mask */
776
+	if (dws->channels && !(dws->channels & dwc->mask))
777
+		return false;
778
+
869779 	/* We have to copy data since dws can be temporary storage */
870780 	memcpy(&dwc->dws, dws, sizeof(struct dw_dma_slave));
871781 
....@@ -876,27 +786,17 @@
876786 static int dwc_config(struct dma_chan *chan, struct dma_slave_config *sconfig)
877787 {
878788 	struct dw_dma_chan *dwc = to_dw_dma_chan(chan);
879
-	struct dma_slave_config *sc = &dwc->dma_sconfig;
880789 	struct dw_dma *dw = to_dw_dma(chan->device);
881
-	/*
882
-	 * Fix sconfig's burst size according to dw_dmac. We need to convert
883
-	 * them as:
884
-	 * 1 -> 0, 4 -> 1, 8 -> 2, 16 -> 3.
885
-	 *
886
-	 * NOTE: burst size 2 is not supported by DesignWare controller.
887
-	 *       iDMA 32-bit supports it.
888
-	 */
889
-	u32 s = dw->pdata->is_idma32 ? 1 : 2;
890
-
891
-	/* Check if chan will be configured for slave transfers */
892
-	if (!is_slave_direction(sconfig->direction))
893
-		return -EINVAL;
894790 
895791 	memcpy(&dwc->dma_sconfig, sconfig, sizeof(*sconfig));
896
-	dwc->direction = sconfig->direction;
897792 
898
-	sc->src_maxburst = sc->src_maxburst > 1 ? fls(sc->src_maxburst) - s : 0;
899
-	sc->dst_maxburst = sc->dst_maxburst > 1 ? fls(sc->dst_maxburst) - s : 0;
793
+	dwc->dma_sconfig.src_maxburst =
794
+		clamp(dwc->dma_sconfig.src_maxburst, 0U, dwc->max_burst);
795
+	dwc->dma_sconfig.dst_maxburst =
796
+		clamp(dwc->dma_sconfig.dst_maxburst, 0U, dwc->max_burst);
797
+
798
+	dw->encode_maxburst(dwc, &dwc->dma_sconfig.src_maxburst);
799
+	dw->encode_maxburst(dwc, &dwc->dma_sconfig.dst_maxburst);
900800 
901801 	return 0;
902802 }
....@@ -905,16 +805,9 @@
905805 {
906806 	struct dw_dma *dw = to_dw_dma(dwc->chan.device);
907807 	unsigned int		count = 20;	/* timeout iterations */
908
-	u32			cfglo;
909808 
910
-	cfglo = channel_readl(dwc, CFG_LO);
911
-	if (dw->pdata->is_idma32) {
912
-		if (drain)
913
-			cfglo |= IDMA32C_CFGL_CH_DRAIN;
914
-		else
915
-			cfglo &= ~IDMA32C_CFGL_CH_DRAIN;
916
-	}
917
-	channel_writel(dwc, CFG_LO, cfglo | DWC_CFGL_CH_SUSP);
809
+	dw->suspend_chan(dwc, drain);
810
+
918811 	while (!(channel_readl(dwc, CFG_LO) & DWC_CFGL_FIFO_EMPTY) && count--)
919812 		udelay(2);
920813 
....@@ -933,11 +826,11 @@
933826 	return 0;
934827 }
935828 
936
-static inline void dwc_chan_resume(struct dw_dma_chan *dwc)
829
+static inline void dwc_chan_resume(struct dw_dma_chan *dwc, bool drain)
937830 {
938
-	u32 cfglo = channel_readl(dwc, CFG_LO);
831
+	struct dw_dma *dw = to_dw_dma(dwc->chan.device);
939832 
940
-	channel_writel(dwc, CFG_LO, cfglo & ~DWC_CFGL_CH_SUSP);
833
+	dw->resume_chan(dwc, drain);
941834 
942835 	clear_bit(DW_DMA_IS_PAUSED, &dwc->flags);
943836 }
....@@ -950,7 +843,7 @@
950843 	spin_lock_irqsave(&dwc->lock, flags);
951844 
952845 	if (test_bit(DW_DMA_IS_PAUSED, &dwc->flags))
953
-		dwc_chan_resume(dwc);
846
+		dwc_chan_resume(dwc, false);
954847 
955848 	spin_unlock_irqrestore(&dwc->lock, flags);
956849 
....@@ -973,7 +866,7 @@
973866 
974867 	dwc_chan_disable(dw, dwc);
975868 
976
-	dwc_chan_resume(dwc);
869
+	dwc_chan_resume(dwc, true);
977870 
978871 	/* active_list entries will end up before queued entries */
979872 	list_splice_init(&dwc->queue, &list);
....@@ -1063,36 +956,8 @@
1063956 
1064957 /*----------------------------------------------------------------------*/
1065958 
1066
-/*
1067
- * Program FIFO size of channels.
1068
- *
1069
- * By default full FIFO (512 bytes) is assigned to channel 0. Here we
1070
- * slice FIFO on equal parts between channels.
1071
- */
1072
-static void idma32_fifo_partition(struct dw_dma *dw)
959
+void do_dw_dma_off(struct dw_dma *dw)
1073960 {
1074
-	u64 value = IDMA32C_FP_PSIZE_CH0(64) | IDMA32C_FP_PSIZE_CH1(64) |
1075
-		    IDMA32C_FP_UPDATE;
1076
-	u64 fifo_partition = 0;
1077
-
1078
-	if (!dw->pdata->is_idma32)
1079
-		return;
1080
-
1081
-	/* Fill FIFO_PARTITION low bits (Channels 0..1, 4..5) */
1082
-	fifo_partition |= value << 0;
1083
-
1084
-	/* Fill FIFO_PARTITION high bits (Channels 2..3, 6..7) */
1085
-	fifo_partition |= value << 32;
1086
-
1087
-	/* Program FIFO Partition registers - 64 bytes per channel */
1088
-	idma32_writeq(dw, FIFO_PARTITION1, fifo_partition);
1089
-	idma32_writeq(dw, FIFO_PARTITION0, fifo_partition);
1090
-}
1091
-
1092
-static void dw_dma_off(struct dw_dma *dw)
1093
-{
1094
-	unsigned int i;
1095
-
1096961 	dma_writel(dw, CFG, 0);
1097962 
1098963 	channel_clear_bit(dw, MASK.XFER, dw->all_chan_mask);
....@@ -1103,12 +968,9 @@
1103968 
1104969 	while (dma_readl(dw, CFG) & DW_CFG_DMA_EN)
1105970 		cpu_relax();
1106
-
1107
-	for (i = 0; i < dw->dma.chancnt; i++)
1108
-		clear_bit(DW_DMA_IS_INITIALIZED, &dw->chan[i].flags);
1109971 }
1110972 
1111
-static void dw_dma_on(struct dw_dma *dw)
973
+void do_dw_dma_on(struct dw_dma *dw)
1112974 {
1113975 	dma_writel(dw, CFG, DW_CFG_DMA_EN);
1114976 }
....@@ -1144,7 +1006,7 @@
11441006 
11451007 	/* Enable controller here if needed */
11461008 	if (!dw->in_use)
1147
-		dw_dma_on(dw);
1009
+		do_dw_dma_on(dw);
11481010 	dw->in_use |= dwc->mask;
11491011 
11501012 	return 0;
....@@ -1155,7 +1017,6 @@
11551017 	struct dw_dma_chan	*dwc = to_dw_dma_chan(chan);
11561018 	struct dw_dma		*dw = to_dw_dma(chan->device);
11571019 	unsigned long		flags;
1158
-	LIST_HEAD(list);
11591020 
11601021 	dev_dbg(chan2dev(chan), "%s: descs allocated=%u\n", __func__,
11611022 			dwc->descs_allocated);
....@@ -1170,8 +1031,6 @@
11701031 	/* Clear custom channel configuration */
11711032 	memset(&dwc->dws, 0, sizeof(struct dw_dma_slave));
11721033 
1173
-	clear_bit(DW_DMA_IS_INITIALIZED, &dwc->flags);
1174
-
11751034 	/* Disable interrupts */
11761035 	channel_clear_bit(dw, MASK.XFER, dwc->mask);
11771036 	channel_clear_bit(dw, MASK.BLOCK, dwc->mask);
....@@ -1182,30 +1041,44 @@
11821041 	/* Disable controller in case it was a last user */
11831042 	dw->in_use &= ~dwc->mask;
11841043 	if (!dw->in_use)
1185
-		dw_dma_off(dw);
1044
+		do_dw_dma_off(dw);
11861045 
11871046 	dev_vdbg(chan2dev(chan), "%s: done\n", __func__);
11881047 }
11891048 
1190
-int dw_dma_probe(struct dw_dma_chip *chip)
1049
+static void dwc_caps(struct dma_chan *chan, struct dma_slave_caps *caps)
11911050 {
1051
+	struct dw_dma_chan *dwc = to_dw_dma_chan(chan);
1052
+
1053
+	caps->max_burst = dwc->max_burst;
1054
+
1055
+	/*
1056
+	 * It might be crucial for some devices to have the hardware
1057
+	 * accelerated multi-block transfers supported, aka LLPs in DW DMAC
1058
+	 * notation. So if LLPs are supported then max_sg_burst is set to
1059
+	 * zero which means unlimited number of SG entries can be handled in a
1060
+	 * single DMA transaction, otherwise it's just one SG entry.
1061
+	 */
1062
+	if (dwc->nollp)
1063
+		caps->max_sg_burst = 1;
1064
+	else
1065
+		caps->max_sg_burst = 0;
1066
+}
1067
+
1068
+int do_dma_probe(struct dw_dma_chip *chip)
1069
+{
1070
+	struct dw_dma *dw = chip->dw;
11921071 	struct dw_dma_platform_data *pdata;
1193
-	struct dw_dma		*dw;
11941072 	bool			autocfg = false;
11951073 	unsigned int		dw_params;
11961074 	unsigned int		i;
11971075 	int			err;
1198
-
1199
-	dw = devm_kzalloc(chip->dev, sizeof(*dw), GFP_KERNEL);
1200
-	if (!dw)
1201
-		return -ENOMEM;
12021076 
12031077 	dw->pdata = devm_kzalloc(chip->dev, sizeof(*dw->pdata), GFP_KERNEL);
12041078 	if (!dw->pdata)
12051079 		return -ENOMEM;
12061080 
12071081 	dw->regs = chip->regs;
1208
-	chip->dw = dw;
12091082 
12101083 	pm_runtime_get_sync(chip->dev);
12111084 
....@@ -1232,8 +1105,6 @@
12321105 		pdata->block_size = dma_readl(dw, MAX_BLK_SIZE);
12331106 
12341107 		/* Fill platform data with the default values */
1235
-		pdata->is_private = true;
1236
-		pdata->is_memcpy = true;
12371108 		pdata->chan_allocation_order = CHAN_ALLOCATION_ASCENDING;
12381109 		pdata->chan_priority = CHAN_PRIORITY_ASCENDING;
12391110 	} else if (chip->pdata->nr_channels > DW_DMA_MAX_NR_CHANNELS) {
....@@ -1257,15 +1128,10 @@
12571128 	dw->all_chan_mask = (1 << pdata->nr_channels) - 1;
12581129 
12591130 	/* Force dma off, just in case */
1260
-	dw_dma_off(dw);
1261
-
1262
-	idma32_fifo_partition(dw);
1131
+	dw->disable(dw);
12631132 
12641133 	/* Device and instance ID for IRQ and DMA pool */
1265
-	if (pdata->is_idma32)
1266
-		snprintf(dw->name, sizeof(dw->name), "idma32:dmac%d", chip->id);
1267
-	else
1268
-		snprintf(dw->name, sizeof(dw->name), "dw:dmac%d", chip->id);
1134
+	dw->set_device_name(dw, chip->id);
12691135 
12701136 	/* Create a pool of consistent memory blocks for hardware descriptors */
12711137 	dw->desc_pool = dmam_pool_create(dw->name, chip->dev,
....@@ -1276,7 +1142,7 @@
12761142 		goto err_pdata;
12771143 	}
12781144 
1279
-	tasklet_init(&dw->tasklet, dw_dma_tasklet, (unsigned long)dw);
1145
+	tasklet_setup(&dw->tasklet, dw_dma_tasklet);
12801146 
12811147 	err = request_irq(chip->irq, dw_dma_interrupt, IRQF_SHARED,
12821148 			  dw->name, dw);
....@@ -1328,11 +1194,23 @@
13281194 			 */
13291195 			dwc->block_size =
13301196 				(4 << ((pdata->block_size >> 4 * i) & 0xf)) - 1;
1197
+
1198
+			/*
1199
+			 * According to the DW DMA databook the true scatter-
1200
+			 * gether LLPs aren't available if either multi-block
1201
+			 * config is disabled (CHx_MULTI_BLK_EN == 0) or the
1202
+			 * LLP register is hard-coded to zeros
1203
+			 * (CHx_HC_LLP == 1).
1204
+			 */
13311205 			dwc->nollp =
1332
-				(dwc_params >> DWC_PARAMS_MBLK_EN & 0x1) == 0;
1206
+				(dwc_params >> DWC_PARAMS_MBLK_EN & 0x1) == 0 ||
1207
+				(dwc_params >> DWC_PARAMS_HC_LLP & 0x1) == 1;
1208
+			dwc->max_burst =
1209
+				(0x4 << (dwc_params >> DWC_PARAMS_MSIZE & 0x7));
13331210 		} else {
13341211 			dwc->block_size = pdata->block_size;
13351212 			dwc->nollp = !pdata->multi_block[i];
1213
+			dwc->max_burst = pdata->max_burst[i] ?: DW_DMA_MAX_BURST;
13361214 		}
13371215 	}
13381216 
....@@ -1345,10 +1223,8 @@
13451223 
13461224 	/* Set capabilities */
13471225 	dma_cap_set(DMA_SLAVE, dw->dma.cap_mask);
1348
-	if (pdata->is_private)
1349
-		dma_cap_set(DMA_PRIVATE, dw->dma.cap_mask);
1350
-	if (pdata->is_memcpy)
1351
-		dma_cap_set(DMA_MEMCPY, dw->dma.cap_mask);
1226
+	dma_cap_set(DMA_PRIVATE, dw->dma.cap_mask);
1227
+	dma_cap_set(DMA_MEMCPY, dw->dma.cap_mask);
13521228 
13531229 	dw->dma.dev = chip->dev;
13541230 	dw->dma.device_alloc_chan_resources = dwc_alloc_chan_resources;
....@@ -1357,6 +1233,7 @@
13571233 	dw->dma.device_prep_dma_memcpy = dwc_prep_dma_memcpy;
13581234 	dw->dma.device_prep_slave_sg = dwc_prep_slave_sg;
13591235 
1236
+	dw->dma.device_caps = dwc_caps;
13601237 	dw->dma.device_config = dwc_config;
13611238 	dw->dma.device_pause = dwc_pause;
13621239 	dw->dma.device_resume = dwc_resume;
....@@ -1366,11 +1243,20 @@
13661243 	dw->dma.device_issue_pending = dwc_issue_pending;
13671244 
13681245 	/* DMA capabilities */
1246
+	dw->dma.min_burst = DW_DMA_MIN_BURST;
1247
+	dw->dma.max_burst = DW_DMA_MAX_BURST;
13691248 	dw->dma.src_addr_widths = DW_DMA_BUSWIDTHS;
13701249 	dw->dma.dst_addr_widths = DW_DMA_BUSWIDTHS;
13711250 	dw->dma.directions = BIT(DMA_DEV_TO_MEM) | BIT(DMA_MEM_TO_DEV) |
13721251 			     BIT(DMA_MEM_TO_MEM);
13731252 	dw->dma.residue_granularity = DMA_RESIDUE_GRANULARITY_BURST;
1253
+
1254
+	/*
1255
+	 * For now there is no hardware with non uniform maximum block size
1256
+	 * across all of the device channels, so we set the maximum segment
1257
+	 * size as the block size found for the very first channel.
1258
+	 */
1259
+	dma_set_max_seg_size(dw->dma.dev, dw->chan[0].block_size);
13741260 
13751261 	err = dma_async_device_register(&dw->dma);
13761262 	if (err)
....@@ -1389,16 +1275,15 @@
13891275 	pm_runtime_put_sync_suspend(chip->dev);
13901276 	return err;
13911277 }
1392
-EXPORT_SYMBOL_GPL(dw_dma_probe);
13931278 
1394
-int dw_dma_remove(struct dw_dma_chip *chip)
1279
+int do_dma_remove(struct dw_dma_chip *chip)
13951280 {
13961281 	struct dw_dma		*dw = chip->dw;
13971282 	struct dw_dma_chan	*dwc, *_dwc;
13981283 
13991284 	pm_runtime_get_sync(chip->dev);
14001285 
1401
-	dw_dma_off(dw);
1286
+	do_dw_dma_off(dw);
14021287 	dma_async_device_unregister(&dw->dma);
14031288 
14041289 	free_irq(chip->irq, dw);
....@@ -1413,27 +1298,24 @@
14131298 	pm_runtime_put_sync_suspend(chip->dev);
14141299 	return 0;
14151300 }
1416
-EXPORT_SYMBOL_GPL(dw_dma_remove);
14171301 
1418
-int dw_dma_disable(struct dw_dma_chip *chip)
1302
+int do_dw_dma_disable(struct dw_dma_chip *chip)
14191303 {
14201304 	struct dw_dma *dw = chip->dw;
14211305 
1422
-	dw_dma_off(dw);
1306
+	dw->disable(dw);
14231307 	return 0;
14241308 }
1425
-EXPORT_SYMBOL_GPL(dw_dma_disable);
1309
+EXPORT_SYMBOL_GPL(do_dw_dma_disable);
14261310 
1427
-int dw_dma_enable(struct dw_dma_chip *chip)
1311
+int do_dw_dma_enable(struct dw_dma_chip *chip)
14281312 {
14291313 	struct dw_dma *dw = chip->dw;
14301314 
1431
-	idma32_fifo_partition(dw);
1432
-
1433
-	dw_dma_on(dw);
1315
+	dw->enable(dw);
14341316 	return 0;
14351317 }
1436
-EXPORT_SYMBOL_GPL(dw_dma_enable);
1318
+EXPORT_SYMBOL_GPL(do_dw_dma_enable);
14371319 
14381320 MODULE_LICENSE("GPL v2");
14391321 MODULE_DESCRIPTION("Synopsys DesignWare DMA Controller core driver");