| .. | .. |
|---|
| 32 | 32 | #define NPCM7XX_Tx_INTEN BIT(29) |
|---|
| 33 | 33 | #define NPCM7XX_Tx_COUNTEN BIT(30) |
|---|
| 34 | 34 | #define NPCM7XX_Tx_ONESHOT 0x0 |
|---|
| 35 | | -#define NPCM7XX_Tx_OPER GENMASK(3, 27) |
|---|
| 35 | +#define NPCM7XX_Tx_OPER GENMASK(28, 27) |
|---|
| 36 | 36 | #define NPCM7XX_Tx_MIN_PRESCALE 0x1 |
|---|
| 37 | 37 | #define NPCM7XX_Tx_TDR_MASK_BITS 24 |
|---|
| 38 | 38 | #define NPCM7XX_Tx_MAX_CNT 0xFFFFFF |
|---|
| .. | .. |
|---|
| 84 | 84 | |
|---|
| 85 | 85 | val = readl(timer_of_base(to) + NPCM7XX_REG_TCSR0); |
|---|
| 86 | 86 | val &= ~NPCM7XX_Tx_OPER; |
|---|
| 87 | | - |
|---|
| 88 | | - val = readl(timer_of_base(to) + NPCM7XX_REG_TCSR0); |
|---|
| 89 | 87 | val |= NPCM7XX_START_ONESHOT_Tx; |
|---|
| 90 | 88 | writel(val, timer_of_base(to) + NPCM7XX_REG_TCSR0); |
|---|
| 91 | 89 | |
|---|
| .. | .. |
|---|
| 97 | 95 | struct timer_of *to = to_timer_of(evt); |
|---|
| 98 | 96 | u32 val; |
|---|
| 99 | 97 | |
|---|
| 98 | + writel(timer_of_period(to), timer_of_base(to) + NPCM7XX_REG_TICR0); |
|---|
| 99 | + |
|---|
| 100 | 100 | val = readl(timer_of_base(to) + NPCM7XX_REG_TCSR0); |
|---|
| 101 | 101 | val &= ~NPCM7XX_Tx_OPER; |
|---|
| 102 | | - |
|---|
| 103 | | - writel(timer_of_period(to), timer_of_base(to) + NPCM7XX_REG_TICR0); |
|---|
| 104 | 102 | val |= NPCM7XX_START_PERIODIC_Tx; |
|---|
| 105 | | - |
|---|
| 106 | 103 | writel(val, timer_of_base(to) + NPCM7XX_REG_TCSR0); |
|---|
| 107 | 104 | |
|---|
| 108 | 105 | return 0; |
|---|