.. | .. |
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20 | 20 | #include "owl-gate.h" |
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21 | 21 | #include "owl-mux.h" |
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22 | 22 | #include "owl-pll.h" |
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| 23 | +#include "owl-reset.h" |
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23 | 24 | |
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24 | 25 | #include <dt-bindings/clock/actions,s700-cmu.h> |
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| 26 | +#include <dt-bindings/reset/actions,s700-reset.h> |
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25 | 27 | |
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26 | 28 | #define CMU_COREPLL (0x0000) |
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27 | 29 | #define CMU_DEVPLL (0x0004) |
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.. | .. |
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160 | 162 | |
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161 | 163 | static struct clk_div_table rmii_div_table[] = { |
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162 | 164 | {0, 4}, {1, 10}, |
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| 165 | + {0, 0} |
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163 | 166 | }; |
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164 | 167 | |
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165 | 168 | /* divider clocks */ |
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.. | .. |
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569 | 572 | .num = CLK_NR_CLKS, |
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570 | 573 | }; |
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571 | 574 | |
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572 | | -static const struct owl_clk_desc s700_clk_desc = { |
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| 575 | +static const struct owl_reset_map s700_resets[] = { |
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| 576 | + [RESET_DE] = { CMU_DEVRST0, BIT(0) }, |
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| 577 | + [RESET_LCD0] = { CMU_DEVRST0, BIT(1) }, |
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| 578 | + [RESET_DSI] = { CMU_DEVRST0, BIT(2) }, |
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| 579 | + [RESET_CSI] = { CMU_DEVRST0, BIT(13) }, |
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| 580 | + [RESET_SI] = { CMU_DEVRST0, BIT(14) }, |
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| 581 | + [RESET_I2C0] = { CMU_DEVRST1, BIT(0) }, |
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| 582 | + [RESET_I2C1] = { CMU_DEVRST1, BIT(1) }, |
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| 583 | + [RESET_I2C2] = { CMU_DEVRST1, BIT(2) }, |
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| 584 | + [RESET_I2C3] = { CMU_DEVRST1, BIT(3) }, |
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| 585 | + [RESET_SPI0] = { CMU_DEVRST1, BIT(4) }, |
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| 586 | + [RESET_SPI1] = { CMU_DEVRST1, BIT(5) }, |
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| 587 | + [RESET_SPI2] = { CMU_DEVRST1, BIT(6) }, |
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| 588 | + [RESET_SPI3] = { CMU_DEVRST1, BIT(7) }, |
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| 589 | + [RESET_UART0] = { CMU_DEVRST1, BIT(8) }, |
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| 590 | + [RESET_UART1] = { CMU_DEVRST1, BIT(9) }, |
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| 591 | + [RESET_UART2] = { CMU_DEVRST1, BIT(10) }, |
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| 592 | + [RESET_UART3] = { CMU_DEVRST1, BIT(11) }, |
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| 593 | + [RESET_UART4] = { CMU_DEVRST1, BIT(12) }, |
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| 594 | + [RESET_UART5] = { CMU_DEVRST1, BIT(13) }, |
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| 595 | + [RESET_UART6] = { CMU_DEVRST1, BIT(14) }, |
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| 596 | + [RESET_KEY] = { CMU_DEVRST1, BIT(24) }, |
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| 597 | + [RESET_GPIO] = { CMU_DEVRST1, BIT(25) }, |
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| 598 | + [RESET_AUDIO] = { CMU_DEVRST1, BIT(29) }, |
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| 599 | +}; |
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| 600 | + |
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| 601 | +static struct owl_clk_desc s700_clk_desc = { |
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573 | 602 | .clks = s700_clks, |
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574 | 603 | .num_clks = ARRAY_SIZE(s700_clks), |
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575 | 604 | |
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576 | 605 | .hw_clks = &s700_hw_clks, |
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| 606 | + |
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| 607 | + .resets = s700_resets, |
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| 608 | + .num_resets = ARRAY_SIZE(s700_resets), |
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577 | 609 | }; |
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578 | 610 | |
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579 | 611 | static int s700_clk_probe(struct platform_device *pdev) |
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580 | 612 | { |
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581 | | - const struct owl_clk_desc *desc; |
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| 613 | + struct owl_clk_desc *desc; |
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| 614 | + struct owl_reset *reset; |
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| 615 | + int ret; |
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582 | 616 | |
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583 | 617 | desc = &s700_clk_desc; |
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584 | 618 | owl_clk_regmap_init(pdev, desc); |
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585 | 619 | |
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| 620 | + /* |
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| 621 | + * FIXME: Reset controller registration should be moved to |
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| 622 | + * common code, once all SoCs of Owl family supports it. |
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| 623 | + */ |
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| 624 | + reset = devm_kzalloc(&pdev->dev, sizeof(*reset), GFP_KERNEL); |
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| 625 | + if (!reset) |
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| 626 | + return -ENOMEM; |
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| 627 | + |
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| 628 | + reset->rcdev.of_node = pdev->dev.of_node; |
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| 629 | + reset->rcdev.ops = &owl_reset_ops; |
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| 630 | + reset->rcdev.nr_resets = desc->num_resets; |
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| 631 | + reset->reset_map = desc->resets; |
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| 632 | + reset->regmap = desc->regmap; |
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| 633 | + |
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| 634 | + ret = devm_reset_controller_register(&pdev->dev, &reset->rcdev); |
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| 635 | + if (ret) |
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| 636 | + dev_err(&pdev->dev, "Failed to register reset controller\n"); |
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| 637 | + |
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586 | 638 | return owl_clk_probe(&pdev->dev, desc->hw_clks); |
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587 | 639 | } |
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588 | 640 | |
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