hc
2024-01-05 071106ecf68c401173c58808b1cf5f68cc50d390
kernel/drivers/clk/actions/owl-s700.c
....@@ -20,8 +20,10 @@
2020 #include "owl-gate.h"
2121 #include "owl-mux.h"
2222 #include "owl-pll.h"
23
+#include "owl-reset.h"
2324
2425 #include <dt-bindings/clock/actions,s700-cmu.h>
26
+#include <dt-bindings/reset/actions,s700-reset.h>
2527
2628 #define CMU_COREPLL (0x0000)
2729 #define CMU_DEVPLL (0x0004)
....@@ -160,6 +162,7 @@
160162
161163 static struct clk_div_table rmii_div_table[] = {
162164 {0, 4}, {1, 10},
165
+ {0, 0}
163166 };
164167
165168 /* divider clocks */
....@@ -569,20 +572,69 @@
569572 .num = CLK_NR_CLKS,
570573 };
571574
572
-static const struct owl_clk_desc s700_clk_desc = {
575
+static const struct owl_reset_map s700_resets[] = {
576
+ [RESET_DE] = { CMU_DEVRST0, BIT(0) },
577
+ [RESET_LCD0] = { CMU_DEVRST0, BIT(1) },
578
+ [RESET_DSI] = { CMU_DEVRST0, BIT(2) },
579
+ [RESET_CSI] = { CMU_DEVRST0, BIT(13) },
580
+ [RESET_SI] = { CMU_DEVRST0, BIT(14) },
581
+ [RESET_I2C0] = { CMU_DEVRST1, BIT(0) },
582
+ [RESET_I2C1] = { CMU_DEVRST1, BIT(1) },
583
+ [RESET_I2C2] = { CMU_DEVRST1, BIT(2) },
584
+ [RESET_I2C3] = { CMU_DEVRST1, BIT(3) },
585
+ [RESET_SPI0] = { CMU_DEVRST1, BIT(4) },
586
+ [RESET_SPI1] = { CMU_DEVRST1, BIT(5) },
587
+ [RESET_SPI2] = { CMU_DEVRST1, BIT(6) },
588
+ [RESET_SPI3] = { CMU_DEVRST1, BIT(7) },
589
+ [RESET_UART0] = { CMU_DEVRST1, BIT(8) },
590
+ [RESET_UART1] = { CMU_DEVRST1, BIT(9) },
591
+ [RESET_UART2] = { CMU_DEVRST1, BIT(10) },
592
+ [RESET_UART3] = { CMU_DEVRST1, BIT(11) },
593
+ [RESET_UART4] = { CMU_DEVRST1, BIT(12) },
594
+ [RESET_UART5] = { CMU_DEVRST1, BIT(13) },
595
+ [RESET_UART6] = { CMU_DEVRST1, BIT(14) },
596
+ [RESET_KEY] = { CMU_DEVRST1, BIT(24) },
597
+ [RESET_GPIO] = { CMU_DEVRST1, BIT(25) },
598
+ [RESET_AUDIO] = { CMU_DEVRST1, BIT(29) },
599
+};
600
+
601
+static struct owl_clk_desc s700_clk_desc = {
573602 .clks = s700_clks,
574603 .num_clks = ARRAY_SIZE(s700_clks),
575604
576605 .hw_clks = &s700_hw_clks,
606
+
607
+ .resets = s700_resets,
608
+ .num_resets = ARRAY_SIZE(s700_resets),
577609 };
578610
579611 static int s700_clk_probe(struct platform_device *pdev)
580612 {
581
- const struct owl_clk_desc *desc;
613
+ struct owl_clk_desc *desc;
614
+ struct owl_reset *reset;
615
+ int ret;
582616
583617 desc = &s700_clk_desc;
584618 owl_clk_regmap_init(pdev, desc);
585619
620
+ /*
621
+ * FIXME: Reset controller registration should be moved to
622
+ * common code, once all SoCs of Owl family supports it.
623
+ */
624
+ reset = devm_kzalloc(&pdev->dev, sizeof(*reset), GFP_KERNEL);
625
+ if (!reset)
626
+ return -ENOMEM;
627
+
628
+ reset->rcdev.of_node = pdev->dev.of_node;
629
+ reset->rcdev.ops = &owl_reset_ops;
630
+ reset->rcdev.nr_resets = desc->num_resets;
631
+ reset->reset_map = desc->resets;
632
+ reset->regmap = desc->regmap;
633
+
634
+ ret = devm_reset_controller_register(&pdev->dev, &reset->rcdev);
635
+ if (ret)
636
+ dev_err(&pdev->dev, "Failed to register reset controller\n");
637
+
586638 return owl_clk_probe(&pdev->dev, desc->hw_clks);
587639 }
588640