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| 1 | +// SPDX-License-Identifier: GPL-2.0-only |
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1 | 2 | /* |
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2 | 3 | * Copyright (C) 2016 Broadcom |
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3 | 4 | * Author: Jayachandran C <jchandra@broadcom.com> |
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4 | 5 | * Copyright (C) 2016 Semihalf |
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5 | 6 | * Author: Tomasz Nowicki <tn@semihalf.com> |
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6 | | - * |
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7 | | - * This program is free software; you can redistribute it and/or modify |
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8 | | - * it under the terms of the GNU General Public License, version 2, as |
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9 | | - * published by the Free Software Foundation (the "GPL"). |
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10 | | - * |
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11 | | - * This program is distributed in the hope that it will be useful, but |
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12 | | - * WITHOUT ANY WARRANTY; without even the implied warranty of |
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13 | | - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU |
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14 | | - * General Public License version 2 (GPLv2) for more details. |
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15 | | - * |
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16 | | - * You should have received a copy of the GNU General Public License |
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17 | | - * version 2 (GPLv2) along with this source code. |
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18 | 7 | */ |
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19 | 8 | |
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20 | 9 | #define pr_fmt(fmt) "ACPI: " fmt |
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.. | .. |
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40 | 29 | u32 oem_revision; |
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41 | 30 | u16 segment; |
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42 | 31 | struct resource bus_range; |
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43 | | - struct pci_ecam_ops *ops; |
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| 32 | + const struct pci_ecam_ops *ops; |
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44 | 33 | struct resource cfgres; |
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45 | 34 | }; |
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46 | 35 | |
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.. | .. |
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51 | 40 | |
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52 | 41 | static struct mcfg_fixup mcfg_quirks[] = { |
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53 | 42 | /* { OEM_ID, OEM_TABLE_ID, REV, SEGMENT, BUS_RANGE, ops, cfgres }, */ |
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| 43 | + |
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| 44 | +#ifdef CONFIG_ARM64 |
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| 45 | + |
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| 46 | +#define AL_ECAM(table_id, rev, seg, ops) \ |
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| 47 | + { "AMAZON", table_id, rev, seg, MCFG_BUS_ANY, ops } |
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| 48 | + |
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| 49 | + AL_ECAM("GRAVITON", 0, 0, &al_pcie_ops), |
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| 50 | + AL_ECAM("GRAVITON", 0, 1, &al_pcie_ops), |
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| 51 | + AL_ECAM("GRAVITON", 0, 2, &al_pcie_ops), |
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| 52 | + AL_ECAM("GRAVITON", 0, 3, &al_pcie_ops), |
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| 53 | + AL_ECAM("GRAVITON", 0, 4, &al_pcie_ops), |
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| 54 | + AL_ECAM("GRAVITON", 0, 5, &al_pcie_ops), |
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| 55 | + AL_ECAM("GRAVITON", 0, 6, &al_pcie_ops), |
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| 56 | + AL_ECAM("GRAVITON", 0, 7, &al_pcie_ops), |
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54 | 57 | |
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55 | 58 | #define QCOM_ECAM32(seg) \ |
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56 | 59 | { "QCOM ", "QDF2432 ", 1, seg, MCFG_BUS_ANY, &pci_32b_ops } |
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.. | .. |
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63 | 66 | QCOM_ECAM32(5), |
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64 | 67 | QCOM_ECAM32(6), |
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65 | 68 | QCOM_ECAM32(7), |
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| 69 | + |
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| 70 | +#define RKCP_ECAM(seg, table_id, ops) \ |
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| 71 | + { "RKCP ", table_id, 0x0000, seg, MCFG_BUS_ANY, ops } |
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| 72 | + |
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| 73 | + RKCP_ECAM(0, "RK3588 ", &rk_pcie_ecam_ops), /* pcie3x4: Name (_SEG, Zero) */ |
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66 | 74 | |
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67 | 75 | #define HISI_QUAD_DOM(table_id, seg, ops) \ |
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68 | 76 | { "HISI ", table_id, 0, (seg) + 0, MCFG_BUS_ANY, ops }, \ |
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.. | .. |
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141 | 149 | XGENE_V2_ECAM_MCFG(4, 0), |
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142 | 150 | XGENE_V2_ECAM_MCFG(4, 1), |
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143 | 151 | XGENE_V2_ECAM_MCFG(4, 2), |
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| 152 | + |
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| 153 | +#define ALTRA_ECAM_QUIRK(rev, seg) \ |
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| 154 | + { "Ampere", "Altra ", rev, seg, MCFG_BUS_ANY, &pci_32b_read_ops } |
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| 155 | + |
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| 156 | + ALTRA_ECAM_QUIRK(1, 0), |
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| 157 | + ALTRA_ECAM_QUIRK(1, 1), |
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| 158 | + ALTRA_ECAM_QUIRK(1, 2), |
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| 159 | + ALTRA_ECAM_QUIRK(1, 3), |
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| 160 | + ALTRA_ECAM_QUIRK(1, 4), |
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| 161 | + ALTRA_ECAM_QUIRK(1, 5), |
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| 162 | + ALTRA_ECAM_QUIRK(1, 6), |
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| 163 | + ALTRA_ECAM_QUIRK(1, 7), |
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| 164 | + ALTRA_ECAM_QUIRK(1, 8), |
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| 165 | + ALTRA_ECAM_QUIRK(1, 9), |
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| 166 | + ALTRA_ECAM_QUIRK(1, 10), |
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| 167 | + ALTRA_ECAM_QUIRK(1, 11), |
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| 168 | + ALTRA_ECAM_QUIRK(1, 12), |
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| 169 | + ALTRA_ECAM_QUIRK(1, 13), |
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| 170 | + ALTRA_ECAM_QUIRK(1, 14), |
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| 171 | + ALTRA_ECAM_QUIRK(1, 15), |
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| 172 | +#endif /* ARM64 */ |
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144 | 173 | }; |
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145 | 174 | |
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146 | 175 | static char mcfg_oem_id[ACPI_OEM_ID_SIZE]; |
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.. | .. |
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152 | 181 | { |
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153 | 182 | if (!memcmp(f->oem_id, mcfg_oem_id, ACPI_OEM_ID_SIZE) && |
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154 | 183 | !memcmp(f->oem_table_id, mcfg_oem_table_id, |
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155 | | - ACPI_OEM_TABLE_ID_SIZE) && |
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| 184 | + ACPI_OEM_TABLE_ID_SIZE) && |
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156 | 185 | f->oem_revision == mcfg_oem_revision && |
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157 | 186 | f->segment == segment && |
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158 | 187 | resource_contains(&f->bus_range, bus_range)) |
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.. | .. |
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164 | 193 | |
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165 | 194 | static void pci_mcfg_apply_quirks(struct acpi_pci_root *root, |
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166 | 195 | struct resource *cfgres, |
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167 | | - struct pci_ecam_ops **ecam_ops) |
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| 196 | + const struct pci_ecam_ops **ecam_ops) |
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168 | 197 | { |
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169 | 198 | #ifdef CONFIG_PCI_QUIRKS |
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170 | 199 | u16 segment = root->segment; |
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.. | .. |
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190 | 219 | static LIST_HEAD(pci_mcfg_list); |
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191 | 220 | |
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192 | 221 | int pci_mcfg_lookup(struct acpi_pci_root *root, struct resource *cfgres, |
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193 | | - struct pci_ecam_ops **ecam_ops) |
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| 222 | + const struct pci_ecam_ops **ecam_ops) |
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194 | 223 | { |
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195 | | - struct pci_ecam_ops *ops = &pci_generic_ecam_ops; |
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| 224 | + const struct pci_ecam_ops *ops = &pci_generic_ecam_ops; |
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196 | 225 | struct resource *bus_res = &root->secondary; |
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197 | 226 | u16 seg = root->segment; |
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198 | 227 | struct mcfg_entry *e; |
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.. | .. |
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279 | 308 | { |
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280 | 309 | int err = acpi_table_parse(ACPI_SIG_MCFG, pci_mcfg_parse); |
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281 | 310 | if (err) |
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282 | | - pr_err("Failed to parse MCFG (%d)\n", err); |
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| 311 | + pr_debug("Failed to parse MCFG (%d)\n", err); |
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283 | 312 | } |
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