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12 | 12 | #ifndef _XTENSA_COPROCESSOR_H |
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13 | 13 | #define _XTENSA_COPROCESSOR_H |
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14 | 14 | |
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15 | | -#include <linux/stringify.h> |
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16 | | -#include <variant/core.h> |
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17 | 15 | #include <variant/tie.h> |
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| 16 | +#include <asm/core.h> |
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18 | 17 | #include <asm/types.h> |
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19 | 18 | |
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20 | 19 | #ifdef __ASSEMBLY__ |
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.. | .. |
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90 | 89 | |
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91 | 90 | #ifndef __ASSEMBLY__ |
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92 | 91 | |
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93 | | - |
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94 | | -#if XCHAL_HAVE_CP |
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95 | | - |
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96 | | -#define RSR_CPENABLE(x) do { \ |
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97 | | - __asm__ __volatile__("rsr %0, cpenable" : "=a" (x)); \ |
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98 | | - } while(0); |
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99 | | -#define WSR_CPENABLE(x) do { \ |
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100 | | - __asm__ __volatile__("wsr %0, cpenable; rsync" :: "a" (x)); \ |
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101 | | - } while(0); |
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102 | | - |
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103 | | -#endif /* XCHAL_HAVE_CP */ |
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104 | | - |
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105 | | - |
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106 | 92 | /* |
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107 | 93 | * Additional registers. |
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108 | 94 | * We define three types of additional registers: |
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.. | .. |
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157 | 143 | __attribute__ ((aligned (XCHAL_CP7_SA_ALIGN))); |
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158 | 144 | |
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159 | 145 | extern struct thread_info* coprocessor_owner[XCHAL_CP_MAX]; |
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160 | | -extern void coprocessor_save(void*, int); |
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161 | | -extern void coprocessor_load(void*, int); |
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162 | 146 | extern void coprocessor_flush(struct thread_info*, int); |
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163 | | -extern void coprocessor_restore(struct thread_info*, int); |
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164 | 147 | |
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165 | 148 | extern void coprocessor_release_all(struct thread_info*); |
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166 | 149 | extern void coprocessor_flush_all(struct thread_info*); |
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167 | | - |
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168 | | -static inline void coprocessor_clear_cpenable(void) |
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169 | | -{ |
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170 | | - unsigned long i = 0; |
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171 | | - WSR_CPENABLE(i); |
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172 | | -} |
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173 | 150 | |
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174 | 151 | #endif /* XTENSA_HAVE_COPROCESSORS */ |
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175 | 152 | |
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