hc
2024-01-05 071106ecf68c401173c58808b1cf5f68cc50d390
kernel/arch/xtensa/include/asm/coprocessor.h
....@@ -12,9 +12,8 @@
1212 #ifndef _XTENSA_COPROCESSOR_H
1313 #define _XTENSA_COPROCESSOR_H
1414
15
-#include <linux/stringify.h>
16
-#include <variant/core.h>
1715 #include <variant/tie.h>
16
+#include <asm/core.h>
1817 #include <asm/types.h>
1918
2019 #ifdef __ASSEMBLY__
....@@ -90,19 +89,6 @@
9089
9190 #ifndef __ASSEMBLY__
9291
93
-
94
-#if XCHAL_HAVE_CP
95
-
96
-#define RSR_CPENABLE(x) do { \
97
- __asm__ __volatile__("rsr %0, cpenable" : "=a" (x)); \
98
- } while(0);
99
-#define WSR_CPENABLE(x) do { \
100
- __asm__ __volatile__("wsr %0, cpenable; rsync" :: "a" (x)); \
101
- } while(0);
102
-
103
-#endif /* XCHAL_HAVE_CP */
104
-
105
-
10692 /*
10793 * Additional registers.
10894 * We define three types of additional registers:
....@@ -157,19 +143,10 @@
157143 __attribute__ ((aligned (XCHAL_CP7_SA_ALIGN)));
158144
159145 extern struct thread_info* coprocessor_owner[XCHAL_CP_MAX];
160
-extern void coprocessor_save(void*, int);
161
-extern void coprocessor_load(void*, int);
162146 extern void coprocessor_flush(struct thread_info*, int);
163
-extern void coprocessor_restore(struct thread_info*, int);
164147
165148 extern void coprocessor_release_all(struct thread_info*);
166149 extern void coprocessor_flush_all(struct thread_info*);
167
-
168
-static inline void coprocessor_clear_cpenable(void)
169
-{
170
- unsigned long i = 0;
171
- WSR_CPENABLE(i);
172
-}
173150
174151 #endif /* XTENSA_HAVE_COPROCESSORS */
175152