| .. | .. |
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| 1392 | 1392 | |
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| 1393 | 1393 | if (sd->current_vmcb != svm->vmcb) { |
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| 1394 | 1394 | sd->current_vmcb = svm->vmcb; |
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| 1395 | | - indirect_branch_prediction_barrier(); |
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| 1395 | + |
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| 1396 | + if (!cpu_feature_enabled(X86_FEATURE_IBPB_ON_VMEXIT)) |
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| 1397 | + indirect_branch_prediction_barrier(); |
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| 1396 | 1398 | } |
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| 1397 | 1399 | avic_vcpu_load(vcpu, cpu); |
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| 1398 | 1400 | } |
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| .. | .. |
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| 3374 | 3376 | |
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| 3375 | 3377 | static void svm_prepare_guest_switch(struct kvm_vcpu *vcpu) |
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| 3376 | 3378 | { |
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| 3379 | + amd_clear_divider(); |
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| 3377 | 3380 | } |
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| 3378 | 3381 | |
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| 3379 | 3382 | static inline void sync_cr8_to_lapic(struct kvm_vcpu *vcpu) |
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| .. | .. |
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| 3480 | 3483 | |
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| 3481 | 3484 | static fastpath_t svm_exit_handlers_fastpath(struct kvm_vcpu *vcpu) |
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| 3482 | 3485 | { |
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| 3483 | | - if (to_svm(vcpu)->vmcb->control.exit_code == SVM_EXIT_MSR && |
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| 3484 | | - to_svm(vcpu)->vmcb->control.exit_info_1) |
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| 3486 | + struct vmcb_control_area *control = &to_svm(vcpu)->vmcb->control; |
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| 3487 | + |
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| 3488 | + /* |
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| 3489 | + * Note, the next RIP must be provided as SRCU isn't held, i.e. KVM |
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| 3490 | + * can't read guest memory (dereference memslots) to decode the WRMSR. |
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| 3491 | + */ |
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| 3492 | + if (control->exit_code == SVM_EXIT_MSR && control->exit_info_1 && |
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| 3493 | + nrips && control->next_rip) |
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| 3485 | 3494 | return handle_fastpath_set_msr_irqoff(vcpu); |
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| 3486 | 3495 | |
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| 3487 | 3496 | return EXIT_FASTPATH_NONE; |
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| .. | .. |
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| 3977 | 3986 | |
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| 3978 | 3987 | static void svm_handle_exit_irqoff(struct kvm_vcpu *vcpu) |
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| 3979 | 3988 | { |
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| 3989 | + if (to_svm(vcpu)->vmcb->control.exit_code == SVM_EXIT_INTR) |
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| 3990 | + vcpu->arch.at_instruction_boundary = true; |
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| 3980 | 3991 | } |
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| 3981 | 3992 | |
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| 3982 | 3993 | static void svm_sched_in(struct kvm_vcpu *vcpu, int cpu) |
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