| .. | .. |
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| 7 | 7 | #include <linux/irq.h> |
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| 8 | 8 | |
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| 9 | 9 | #include <asm/hpet.h> |
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| 10 | +#include <asm/setup.h> |
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| 11 | +#include <asm/mce.h> |
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| 10 | 12 | |
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| 11 | 13 | #if defined(CONFIG_X86_IO_APIC) && defined(CONFIG_SMP) && defined(CONFIG_PCI) |
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| 12 | 14 | |
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| .. | .. |
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| 89 | 91 | BUG(); |
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| 90 | 92 | else |
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| 91 | 93 | printk(KERN_DEBUG "Force enabled HPET at resume\n"); |
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| 92 | | - |
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| 93 | | - return; |
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| 94 | 94 | } |
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| 95 | 95 | |
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| 96 | 96 | static void ich_force_enable_hpet(struct pci_dev *dev) |
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| 97 | 97 | { |
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| 98 | 98 | u32 val; |
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| 99 | | - u32 uninitialized_var(rcba); |
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| 99 | + u32 rcba; |
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| 100 | 100 | int err = 0; |
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| 101 | 101 | |
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| 102 | 102 | if (hpet_address || force_hpet_address) |
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| .. | .. |
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| 111 | 111 | } |
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| 112 | 112 | |
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| 113 | 113 | /* use bits 31:14, 16 kB aligned */ |
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| 114 | | - rcba_base = ioremap_nocache(rcba, 0x4000); |
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| 114 | + rcba_base = ioremap(rcba, 0x4000); |
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| 115 | 115 | if (rcba_base == NULL) { |
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| 116 | 116 | dev_printk(KERN_DEBUG, &dev->dev, "ioremap failed; " |
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| 117 | 117 | "cannot force enable HPET\n"); |
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| .. | .. |
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| 186 | 186 | static void old_ich_force_hpet_resume(void) |
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| 187 | 187 | { |
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| 188 | 188 | u32 val; |
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| 189 | | - u32 uninitialized_var(gen_cntl); |
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| 189 | + u32 gen_cntl; |
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| 190 | 190 | |
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| 191 | 191 | if (!force_hpet_address || !cached_dev) |
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| 192 | 192 | return; |
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| .. | .. |
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| 208 | 208 | static void old_ich_force_enable_hpet(struct pci_dev *dev) |
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| 209 | 209 | { |
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| 210 | 210 | u32 val; |
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| 211 | | - u32 uninitialized_var(gen_cntl); |
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| 211 | + u32 gen_cntl; |
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| 212 | 212 | |
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| 213 | 213 | if (hpet_address || force_hpet_address) |
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| 214 | 214 | return; |
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| .. | .. |
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| 299 | 299 | |
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| 300 | 300 | static void vt8237_force_enable_hpet(struct pci_dev *dev) |
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| 301 | 301 | { |
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| 302 | | - u32 uninitialized_var(val); |
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| 302 | + u32 val; |
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| 303 | 303 | |
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| 304 | 304 | if (hpet_address || force_hpet_address) |
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| 305 | 305 | return; |
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| .. | .. |
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| 430 | 430 | |
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| 431 | 431 | static void nvidia_force_enable_hpet(struct pci_dev *dev) |
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| 432 | 432 | { |
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| 433 | | - u32 uninitialized_var(val); |
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| 433 | + u32 val; |
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| 434 | 434 | |
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| 435 | 435 | if (hpet_address || force_hpet_address) |
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| 436 | 436 | return; |
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| .. | .. |
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| 447 | 447 | dev_printk(KERN_DEBUG, &dev->dev, "Force enabled HPET at 0x%lx\n", |
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| 448 | 448 | force_hpet_address); |
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| 449 | 449 | cached_dev = dev; |
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| 450 | | - return; |
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| 451 | 450 | } |
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| 452 | 451 | |
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| 453 | 452 | /* ISA Bridges */ |
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| .. | .. |
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| 512 | 511 | force_hpet_resume_type = NONE_FORCE_HPET_RESUME; |
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| 513 | 512 | dev_printk(KERN_DEBUG, &dev->dev, "Force enabled HPET at " |
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| 514 | 513 | "0x%lx\n", force_hpet_address); |
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| 515 | | - return; |
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| 516 | 514 | } |
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| 517 | 515 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_E6XX_CU, |
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| 518 | 516 | e6xx_force_enable_hpet); |
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| .. | .. |
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| 627 | 625 | DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_16H_NB_F3, |
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| 628 | 626 | amd_disable_seq_and_redirect_scrub); |
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| 629 | 627 | |
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| 630 | | -#if defined(CONFIG_X86_64) && defined(CONFIG_X86_MCE) |
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| 631 | | -#include <linux/jump_label.h> |
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| 632 | | -#include <asm/string_64.h> |
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| 633 | | - |
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| 634 | 628 | /* Ivy Bridge, Haswell, Broadwell */ |
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| 635 | 629 | static void quirk_intel_brickland_xeon_ras_cap(struct pci_dev *pdev) |
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| 636 | 630 | { |
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| .. | .. |
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| 639 | 633 | pci_read_config_dword(pdev, 0x84, &capid0); |
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| 640 | 634 | |
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| 641 | 635 | if (capid0 & 0x10) |
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| 642 | | - static_branch_inc(&mcsafe_key); |
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| 636 | + enable_copy_mc_fragile(); |
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| 643 | 637 | } |
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| 644 | 638 | |
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| 645 | 639 | /* Skylake */ |
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| .. | .. |
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| 656 | 650 | * enabled, so memory machine check recovery is also enabled. |
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| 657 | 651 | */ |
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| 658 | 652 | if ((capid0 & 0xc0) == 0xc0 || (capid5 & 0x1e0)) |
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| 659 | | - static_branch_inc(&mcsafe_key); |
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| 653 | + enable_copy_mc_fragile(); |
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| 660 | 654 | |
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| 661 | 655 | } |
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| 662 | 656 | DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL, 0x0ec3, quirk_intel_brickland_xeon_ras_cap); |
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| 663 | 657 | DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL, 0x2fc0, quirk_intel_brickland_xeon_ras_cap); |
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| 664 | 658 | DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL, 0x6fc0, quirk_intel_brickland_xeon_ras_cap); |
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| 665 | 659 | DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL, 0x2083, quirk_intel_purley_xeon_ras_cap); |
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| 666 | | -#endif |
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| 667 | 660 | #endif |
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| 668 | 661 | |
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| 669 | 662 | bool x86_apple_machine; |
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