forked from ~ljy/RK356X_SDK_RELEASE
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hc
2024-01-05 071106ecf68c401173c58808b1cf5f68cc50d390 
 kernel/arch/x86/kernel/apic/io_apic.c
....@@ -47,7 +47,7 @@
4747 #include <linux/kthread.h>
4848 #include <linux/jiffies.h>	/* time_after() */
4949 #include <linux/slab.h>
50
-#include <linux/bootmem.h>
50
+#include <linux/memblock.h>
5151 
5252 #include <asm/irqdomain.h>
5353 #include <asm/io.h>
....@@ -58,6 +58,7 @@
5858 #include <asm/acpi.h>
5959 #include <asm/dma.h>
6060 #include <asm/timer.h>
61
+#include <asm/time.h>
6162 #include <asm/i8259.h>
6263 #include <asm/setup.h>
6364 #include <asm/irq_remapping.h>
....@@ -151,19 +152,6 @@
151152 static inline bool mp_is_legacy_irq(int irq)
152153 {
153154 	return irq >= 0 && irq < nr_legacy_irqs();
154
-}
155
-
156
-/*
157
- * Initialize all legacy IRQs and all pins on the first IOAPIC
158
- * if we have legacy interrupt controller. Kernel boot option "pirq="
159
- * may rely on non-legacy pins on the first IOAPIC.
160
- */
161
-static inline int mp_init_irq_at_boot(int ioapic, int irq)
162
-{
163
-	if (!nr_legacy_irqs())
164
-		return 0;
165
-
166
-	return ioapic == 0 || mp_is_legacy_irq(irq);
167155 }
168156 
169157 static inline struct irq_domain *mp_ioapic_irqdomain(int ioapic)
....@@ -812,6 +800,7 @@
812800 		return IOAPIC_POL_HIGH;
813801 	case MP_IRQPOL_RESERVED:
814802 		pr_warn("IOAPIC: Invalid polarity: 2, defaulting to low\n");
803
+		fallthrough;
815804 	case MP_IRQPOL_ACTIVE_LOW:
816805 	default: /* Pointless default required due to do gcc stupidity */
817806 		return IOAPIC_POL_LOW;
....@@ -859,6 +848,7 @@
859848 		return IOAPIC_EDGE;
860849 	case MP_IRQTRIG_RESERVED:
861850 		pr_warn("IOAPIC: Invalid trigger mode 2 defaulting to level\n");
851
+		fallthrough;
862852 	case MP_IRQTRIG_LEVEL:
863853 	default: /* Pointless default required due to do gcc stupidity */
864854 		return IOAPIC_LEVEL;
....@@ -870,10 +860,10 @@
870860 {
871861 	init_irq_alloc_info(info, NULL);
872862 	info->type = X86_IRQ_ALLOC_TYPE_IOAPIC;
873
-	info->ioapic_node = node;
874
-	info->ioapic_trigger = trigger;
875
-	info->ioapic_polarity = polarity;
876
-	info->ioapic_valid = 1;
863
+	info->ioapic.node = node;
864
+	info->ioapic.trigger = trigger;
865
+	info->ioapic.polarity = polarity;
866
+	info->ioapic.valid = 1;
877867 }
878868 
879869 #ifndef CONFIG_ACPI
....@@ -888,32 +878,32 @@
888878 
889879 	copy_irq_alloc_info(dst, src);
890880 	dst->type = X86_IRQ_ALLOC_TYPE_IOAPIC;
891
-	dst->ioapic_id = mpc_ioapic_id(ioapic_idx);
892
-	dst->ioapic_pin = pin;
893
-	dst->ioapic_valid = 1;
894
-	if (src && src->ioapic_valid) {
895
-		dst->ioapic_node = src->ioapic_node;
896
-		dst->ioapic_trigger = src->ioapic_trigger;
897
-		dst->ioapic_polarity = src->ioapic_polarity;
881
+	dst->devid = mpc_ioapic_id(ioapic_idx);
882
+	dst->ioapic.pin = pin;
883
+	dst->ioapic.valid = 1;
884
+	if (src && src->ioapic.valid) {
885
+		dst->ioapic.node = src->ioapic.node;
886
+		dst->ioapic.trigger = src->ioapic.trigger;
887
+		dst->ioapic.polarity = src->ioapic.polarity;
898888 	} else {
899
-		dst->ioapic_node = NUMA_NO_NODE;
889
+		dst->ioapic.node = NUMA_NO_NODE;
900890 		if (acpi_get_override_irq(gsi, &trigger, &polarity) >= 0) {
901
-			dst->ioapic_trigger = trigger;
902
-			dst->ioapic_polarity = polarity;
891
+			dst->ioapic.trigger = trigger;
892
+			dst->ioapic.polarity = polarity;
903893 		} else {
904894 			/*
905895 			 * PCI interrupts are always active low level
906896 			 * triggered.
907897 			 */
908
-			dst->ioapic_trigger = IOAPIC_LEVEL;
909
-			dst->ioapic_polarity = IOAPIC_POL_LOW;
898
+			dst->ioapic.trigger = IOAPIC_LEVEL;
899
+			dst->ioapic.polarity = IOAPIC_POL_LOW;
910900 		}
911901 	}
912902 }
913903 
914904 static int ioapic_alloc_attr_node(struct irq_alloc_info *info)
915905 {
916
-	return (info && info->ioapic_valid) ? info->ioapic_node : NUMA_NO_NODE;
906
+	return (info && info->ioapic.valid) ? info->ioapic.node : NUMA_NO_NODE;
917907 }
918908 
919909 static void mp_register_handler(unsigned int irq, unsigned long trigger)
....@@ -943,14 +933,14 @@
943933 	 * pin with real trigger and polarity attributes.
944934 	 */
945935 	if (irq < nr_legacy_irqs() && data->count == 1) {
946
-		if (info->ioapic_trigger != data->trigger)
947
-			mp_register_handler(irq, info->ioapic_trigger);
948
-		data->entry.trigger = data->trigger = info->ioapic_trigger;
949
-		data->entry.polarity = data->polarity = info->ioapic_polarity;
936
+		if (info->ioapic.trigger != data->trigger)
937
+			mp_register_handler(irq, info->ioapic.trigger);
938
+		data->entry.trigger = data->trigger = info->ioapic.trigger;
939
+		data->entry.polarity = data->polarity = info->ioapic.polarity;
950940 	}
951941 
952
-	return data->trigger == info->ioapic_trigger &&
953
-	       data->polarity == info->ioapic_polarity;
942
+	return data->trigger == info->ioapic.trigger &&
943
+	       data->polarity == info->ioapic.polarity;
954944 }
955945 
956946 static int alloc_irq_from_domain(struct irq_domain *domain, int ioapic, u32 gsi,
....@@ -1012,7 +1002,7 @@
10121002 		if (!mp_check_pin_attr(irq, info))
10131003 			return -EBUSY;
10141004 		if (__add_pin_to_irq_node(irq_data->chip_data, node, ioapic,
1015
-					  info->ioapic_pin))
1005
+					  info->ioapic.pin))
10161006 			return -ENOMEM;
10171007 	} else {
10181008 		info->flags |= X86_IRQ_ALLOC_LEGACY;
....@@ -1732,7 +1722,7 @@
17321722 	return false;
17331723 }
17341724 
1735
-static inline bool ioapic_irqd_mask(struct irq_data *data)
1725
+static inline bool ioapic_prepare_move(struct irq_data *data)
17361726 {
17371727 	/* If we are moving the IRQ we need to mask it */
17381728 	if (unlikely(irqd_is_setaffinity_pending(data))) {
....@@ -1743,9 +1733,9 @@
17431733 	return false;
17441734 }
17451735 
1746
-static inline void ioapic_irqd_unmask(struct irq_data *data, bool masked)
1736
+static inline void ioapic_finish_move(struct irq_data *data, bool moveit)
17471737 {
1748
-	if (unlikely(masked)) {
1738
+	if (unlikely(moveit)) {
17491739 		/* Only migrate the irq if the ack has been received.
17501740 		 *
17511741 		 * On rare occasions the broadcast level triggered ack gets
....@@ -1780,11 +1770,11 @@
17801770 	}
17811771 }
17821772 #else
1783
-static inline bool ioapic_irqd_mask(struct irq_data *data)
1773
+static inline bool ioapic_prepare_move(struct irq_data *data)
17841774 {
17851775 	return false;
17861776 }
1787
-static inline void ioapic_irqd_unmask(struct irq_data *data, bool masked)
1777
+static inline void ioapic_finish_move(struct irq_data *data, bool moveit)
17881778 {
17891779 }
17901780 #endif
....@@ -1793,11 +1783,11 @@
17931783 {
17941784 	struct irq_cfg *cfg = irqd_cfg(irq_data);
17951785 	unsigned long v;
1796
-	bool masked;
1786
+	bool moveit;
17971787 	int i;
17981788 
17991789 	irq_complete_move(cfg);
1800
-	masked = ioapic_irqd_mask(irq_data);
1790
+	moveit = ioapic_prepare_move(irq_data);
18011791 
18021792 	/*
18031793 	 * It appears there is an erratum which affects at least version 0x11
....@@ -1852,7 +1842,7 @@
18521842 		eoi_ioapic_pin(cfg->vector, irq_data->chip_data);
18531843 	}
18541844 
1855
-	ioapic_irqd_unmask(irq_data, masked);
1845
+	ioapic_finish_move(irq_data, moveit);
18561846 }
18571847 
18581848 static void ioapic_ir_ack_level(struct irq_data *irq_data)
....@@ -2114,8 +2104,8 @@
21142104 		struct irq_alloc_info info;
21152105 
21162106 		ioapic_set_alloc_attr(&info, NUMA_NO_NODE, 0, 0);
2117
-		info.ioapic_id = mpc_ioapic_id(ioapic);
2118
-		info.ioapic_pin = pin;
2107
+		info.devid = mpc_ioapic_id(ioapic);
2108
+		info.ioapic.pin = pin;
21192109 		mutex_lock(&ioapic_mutex);
21202110 		irq = alloc_isa_irq_from_domain(domain, 0, ioapic, pin, &info);
21212111 		mutex_unlock(&ioapic_mutex);
....@@ -2141,6 +2131,9 @@
21412131 	int apic1, pin1, apic2, pin2;
21422132 	unsigned long flags;
21432133 	int no_pin1 = 0;
2134
+
2135
+	if (!global_clock_event)
2136
+		return;
21442137 
21452138 	local_irq_save(flags);
21462139 
....@@ -2316,9 +2309,9 @@
23162309 		return 0;
23172310 
23182311 	init_irq_alloc_info(&info, NULL);
2319
-	info.type = X86_IRQ_ALLOC_TYPE_IOAPIC;
2320
-	info.ioapic_id = mpc_ioapic_id(ioapic);
2321
-	parent = irq_remapping_get_ir_irq_domain(&info);
2312
+	info.type = X86_IRQ_ALLOC_TYPE_IOAPIC_GET_PARENT;
2313
+	info.devid = mpc_ioapic_id(ioapic);
2314
+	parent = irq_remapping_get_irq_domain(&info);
23222315 	if (!parent)
23232316 		parent = x86_vector_domain;
23242317 	else
....@@ -2449,17 +2442,21 @@
24492442 
24502443 unsigned int arch_dynirq_lower_bound(unsigned int from)
24512444 {
2445
+	unsigned int ret;
2446
+
24522447 	/*
24532448 	 * dmar_alloc_hwirq() may be called before setup_IO_APIC(), so use
24542449 	 * gsi_top if ioapic_dynirq_base hasn't been initialized yet.
24552450 	 */
2456
-	if (!ioapic_initialized)
2457
-		return gsi_top;
2451
+	ret = ioapic_dynirq_base ? : gsi_top;
2452
+
24582453 	/*
2459
-	 * For DT enabled machines ioapic_dynirq_base is irrelevant and not
2460
-	 * updated. So simply return @from if ioapic_dynirq_base == 0.
2454
+	 * For DT enabled machines ioapic_dynirq_base is irrelevant and
2455
+	 * always 0. gsi_top can be 0 if there is no IO/APIC registered.
2456
+	 * 0 is an invalid interrupt number for dynamic allocations. Return
2457
+	 * @from instead.
24612458 	 */
2462
-	return ioapic_dynirq_base ? : from;
2459
+	return ret ? : from;
24632460 }
24642461 
24652462 #ifdef CONFIG_X86_32
....@@ -2651,7 +2648,9 @@
26512648 	n = IOAPIC_RESOURCE_NAME_SIZE + sizeof(struct resource);
26522649 	n *= nr_ioapics;
26532650 
2654
-	mem = alloc_bootmem(n);
2651
+	mem = memblock_alloc(n, SMP_CACHE_BYTES);
2652
+	if (!mem)
2653
+		panic("%s: Failed to allocate %lu bytes\n", __func__, n);
26552654 	res = (void *)mem;
26562655 
26572656 	mem += sizeof(struct resource) * nr_ioapics;
....@@ -2694,7 +2693,11 @@
26942693 #ifdef CONFIG_X86_32
26952694 fake_ioapic_page:
26962695 #endif
2697
-			ioapic_phys = (unsigned long)alloc_bootmem_pages(PAGE_SIZE);
2696
+			ioapic_phys = (unsigned long)memblock_alloc(PAGE_SIZE,
2697
+								    PAGE_SIZE);
2698
+			if (!ioapic_phys)
2699
+				panic("%s: Failed to allocate %lu bytes align=0x%lx\n",
2700
+				      __func__, PAGE_SIZE, PAGE_SIZE);
26982701 			ioapic_phys = __pa(ioapic_phys);
26992702 		}
27002703 		set_fixmap_nocache(idx, ioapic_phys);
....@@ -2946,9 +2949,9 @@
29462949 static void mp_irqdomain_get_attr(u32 gsi, struct mp_chip_data *data,
29472950 				  struct irq_alloc_info *info)
29482951 {
2949
-	if (info && info->ioapic_valid) {
2950
-		data->trigger = info->ioapic_trigger;
2951
-		data->polarity = info->ioapic_polarity;
2952
+	if (info && info->ioapic.valid) {
2953
+		data->trigger = info->ioapic.trigger;
2954
+		data->polarity = info->ioapic.polarity;
29522955 	} else if (acpi_get_override_irq(gsi, &data->trigger,
29532956 					 &data->polarity) < 0) {
29542957 		/* PCI interrupts are always active low level triggered. */
....@@ -2994,7 +2997,7 @@
29942997 		return -EINVAL;
29952998 
29962999 	ioapic = mp_irqdomain_ioapic_idx(domain);
2997
-	pin = info->ioapic_pin;
3000
+	pin = info->ioapic.pin;
29983001 	if (irq_find_mapping(domain, (irq_hw_number_t)pin) > 0)
29993002 		return -EEXIST;
30003003 
....@@ -3002,7 +3005,7 @@
30023005 	if (!data)
30033006 		return -ENOMEM;
30043007 
3005
-	info->ioapic_entry = &data->entry;
3008
+	info->ioapic.entry = &data->entry;
30063009 	ret = irq_domain_alloc_irqs_parent(domain, virq, nr_irqs, info);
30073010 	if (ret < 0) {
30083011 		kfree(data);
....@@ -3010,7 +3013,7 @@
30103013 	}
30113014 
30123015 	INIT_LIST_HEAD(&data->irq_2_pin);
3013
-	irq_data->hwirq = info->ioapic_pin;
3016
+	irq_data->hwirq = info->ioapic.pin;
30143017 	irq_data->chip = (domain->parent == x86_vector_domain) ?
30153018 			  &ioapic_chip : &ioapic_ir_chip;
30163019 	irq_data->chip_data = data;
....@@ -3020,8 +3023,8 @@
30203023 	add_pin_to_irq_node(data, ioapic_alloc_attr_node(info), ioapic, pin);
30213024 
30223025 	local_irq_save(flags);
3023
-	if (info->ioapic_entry)
3024
-		mp_setup_entry(cfg, data, info->ioapic_entry);
3026
+	if (info->ioapic.entry)
3027
+		mp_setup_entry(cfg, data, info->ioapic.entry);
30253028 	mp_register_handler(virq, data->trigger);
30263029 	if (virq < nr_legacy_irqs())
30273030 		legacy_pic->mask(virq);