| .. | .. |
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| 12 | 12 | u8 dev_limit; |
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| 13 | 13 | }; |
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| 14 | 14 | |
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| 15 | | -extern const struct pci_device_id amd_nb_misc_ids[]; |
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| 16 | 15 | extern const struct amd_nb_bus_dev_range amd_nb_bus_dev_ranges[]; |
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| 17 | 16 | |
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| 18 | 17 | extern bool early_is_amd_nb(u32 value); |
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| .. | .. |
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| 58 | 57 | |
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| 59 | 58 | /* initialized to the number of CPUs on the node sharing this bank */ |
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| 60 | 59 | refcount_t cpus; |
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| 60 | + unsigned int shared; |
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| 61 | 61 | }; |
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| 62 | 62 | |
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| 63 | 63 | struct amd_northbridge { |
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| .. | .. |
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| 103 | 103 | |
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| 104 | 104 | static inline bool amd_gart_present(void) |
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| 105 | 105 | { |
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| 106 | + if (boot_cpu_data.x86_vendor != X86_VENDOR_AMD) |
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| 107 | + return false; |
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| 108 | + |
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| 106 | 109 | /* GART present only on Fam15h, upto model 0fh */ |
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| 107 | 110 | if (boot_cpu_data.x86 == 0xf || boot_cpu_data.x86 == 0x10 || |
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| 108 | 111 | (boot_cpu_data.x86 == 0x15 && boot_cpu_data.x86_model < 0x10)) |
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