| .. | .. |
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| 8 | 8 | #ifndef __ASM_SH_MMU_CONTEXT_H |
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| 9 | 9 | #define __ASM_SH_MMU_CONTEXT_H |
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| 10 | 10 | |
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| 11 | | -#ifdef __KERNEL__ |
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| 12 | 11 | #include <cpu/mmu_context.h> |
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| 13 | 12 | #include <asm/tlbflush.h> |
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| 14 | 13 | #include <linux/uaccess.h> |
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| .. | .. |
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| 48 | 47 | */ |
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| 49 | 48 | #define MMU_VPN_MASK 0xfffff000 |
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| 50 | 49 | |
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| 51 | | -#if defined(CONFIG_SUPERH32) |
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| 52 | 50 | #include <asm/mmu_context_32.h> |
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| 53 | | -#else |
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| 54 | | -#include <asm/mmu_context_64.h> |
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| 55 | | -#endif |
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| 56 | 51 | |
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| 57 | 52 | /* |
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| 58 | 53 | * Get MMU context if needed. |
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| .. | .. |
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| 73 | 68 | * Flush all TLB and start new cycle. |
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| 74 | 69 | */ |
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| 75 | 70 | local_flush_tlb_all(); |
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| 76 | | - |
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| 77 | | -#ifdef CONFIG_SUPERH64 |
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| 78 | | - /* |
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| 79 | | - * The SH-5 cache uses the ASIDs, requiring both the I and D |
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| 80 | | - * cache to be flushed when the ASID is exhausted. Weak. |
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| 81 | | - */ |
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| 82 | | - flush_cache_all(); |
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| 83 | | -#endif |
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| 84 | 71 | |
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| 85 | 72 | /* |
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| 86 | 73 | * Fix version; Note that we avoid version #0 |
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| .. | .. |
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| 189 | 176 | #define disable_mmu() do { } while (0) |
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| 190 | 177 | #endif |
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| 191 | 178 | |
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| 192 | | -#endif /* __KERNEL__ */ |
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| 193 | 179 | #endif /* __ASM_SH_MMU_CONTEXT_H */ |
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