change wifi driver to cypress

hc

2024-01-05 071106ecf68c401173c58808b1cf5f68cc50d390

 kernel/arch/s390/kernel/perf_cpum_cf_events.c
..
..
@@ -6,6 +6,7 @@
6
6
 
7
7
 #include <linux/slab.h>
8
8
 #include <linux/perf_event.h>
9
+#include <asm/cpu_mf.h>
9
10
 
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11
 
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12
 /* BEGIN: CPUM_CF COUNTER DEFINITIONS =================================== */
..
..
@@ -30,22 +31,26 @@
30
31
 CPUMF_EVENT_ATTR(cf_fvn3, PROBLEM_STATE_INSTRUCTIONS, 0x0021);
31
32
 CPUMF_EVENT_ATTR(cf_fvn3, L1D_DIR_WRITES, 0x0004);
32
33
 CPUMF_EVENT_ATTR(cf_fvn3, L1D_PENALTY_CYCLES, 0x0005);
33
-CPUMF_EVENT_ATTR(cf_svn_generic, PRNG_FUNCTIONS, 0x0040);
34
-CPUMF_EVENT_ATTR(cf_svn_generic, PRNG_CYCLES, 0x0041);
35
-CPUMF_EVENT_ATTR(cf_svn_generic, PRNG_BLOCKED_FUNCTIONS, 0x0042);
36
-CPUMF_EVENT_ATTR(cf_svn_generic, PRNG_BLOCKED_CYCLES, 0x0043);
37
-CPUMF_EVENT_ATTR(cf_svn_generic, SHA_FUNCTIONS, 0x0044);
38
-CPUMF_EVENT_ATTR(cf_svn_generic, SHA_CYCLES, 0x0045);
39
-CPUMF_EVENT_ATTR(cf_svn_generic, SHA_BLOCKED_FUNCTIONS, 0x0046);
40
-CPUMF_EVENT_ATTR(cf_svn_generic, SHA_BLOCKED_CYCLES, 0x0047);
41
-CPUMF_EVENT_ATTR(cf_svn_generic, DEA_FUNCTIONS, 0x0048);
42
-CPUMF_EVENT_ATTR(cf_svn_generic, DEA_CYCLES, 0x0049);
43
-CPUMF_EVENT_ATTR(cf_svn_generic, DEA_BLOCKED_FUNCTIONS, 0x004a);
44
-CPUMF_EVENT_ATTR(cf_svn_generic, DEA_BLOCKED_CYCLES, 0x004b);
45
-CPUMF_EVENT_ATTR(cf_svn_generic, AES_FUNCTIONS, 0x004c);
46
-CPUMF_EVENT_ATTR(cf_svn_generic, AES_CYCLES, 0x004d);
47
-CPUMF_EVENT_ATTR(cf_svn_generic, AES_BLOCKED_FUNCTIONS, 0x004e);
48
-CPUMF_EVENT_ATTR(cf_svn_generic, AES_BLOCKED_CYCLES, 0x004f);
34
+CPUMF_EVENT_ATTR(cf_svn_12345, PRNG_FUNCTIONS, 0x0040);
35
+CPUMF_EVENT_ATTR(cf_svn_12345, PRNG_CYCLES, 0x0041);
36
+CPUMF_EVENT_ATTR(cf_svn_12345, PRNG_BLOCKED_FUNCTIONS, 0x0042);
37
+CPUMF_EVENT_ATTR(cf_svn_12345, PRNG_BLOCKED_CYCLES, 0x0043);
38
+CPUMF_EVENT_ATTR(cf_svn_12345, SHA_FUNCTIONS, 0x0044);
39
+CPUMF_EVENT_ATTR(cf_svn_12345, SHA_CYCLES, 0x0045);
40
+CPUMF_EVENT_ATTR(cf_svn_12345, SHA_BLOCKED_FUNCTIONS, 0x0046);
41
+CPUMF_EVENT_ATTR(cf_svn_12345, SHA_BLOCKED_CYCLES, 0x0047);
42
+CPUMF_EVENT_ATTR(cf_svn_12345, DEA_FUNCTIONS, 0x0048);
43
+CPUMF_EVENT_ATTR(cf_svn_12345, DEA_CYCLES, 0x0049);
44
+CPUMF_EVENT_ATTR(cf_svn_12345, DEA_BLOCKED_FUNCTIONS, 0x004a);
45
+CPUMF_EVENT_ATTR(cf_svn_12345, DEA_BLOCKED_CYCLES, 0x004b);
46
+CPUMF_EVENT_ATTR(cf_svn_12345, AES_FUNCTIONS, 0x004c);
47
+CPUMF_EVENT_ATTR(cf_svn_12345, AES_CYCLES, 0x004d);
48
+CPUMF_EVENT_ATTR(cf_svn_12345, AES_BLOCKED_FUNCTIONS, 0x004e);
49
+CPUMF_EVENT_ATTR(cf_svn_12345, AES_BLOCKED_CYCLES, 0x004f);
50
+CPUMF_EVENT_ATTR(cf_svn_6, ECC_FUNCTION_COUNT, 0x0050);
51
+CPUMF_EVENT_ATTR(cf_svn_6, ECC_CYCLES_COUNT, 0x0051);
52
+CPUMF_EVENT_ATTR(cf_svn_6, ECC_BLOCKED_FUNCTION_COUNT, 0x0052);
53
+CPUMF_EVENT_ATTR(cf_svn_6, ECC_BLOCKED_CYCLES_COUNT, 0x0053);
49
54
 CPUMF_EVENT_ATTR(cf_z10, L1I_L2_SOURCED_WRITES, 0x0080);
50
55
 CPUMF_EVENT_ATTR(cf_z10, L1D_L2_SOURCED_WRITES, 0x0081);
51
56
 CPUMF_EVENT_ATTR(cf_z10, L1I_L3_LOCAL_WRITES, 0x0082);
..
..
@@ -233,6 +238,64 @@
233
238
 CPUMF_EVENT_ATTR(cf_z14, MT_DIAG_CYCLES_ONE_THR_ACTIVE, 0x01c0);
234
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 CPUMF_EVENT_ATTR(cf_z14, MT_DIAG_CYCLES_TWO_THR_ACTIVE, 0x01c1);
235
240
 
241
+CPUMF_EVENT_ATTR(cf_z15, L1D_RO_EXCL_WRITES, 0x0080);
242
+CPUMF_EVENT_ATTR(cf_z15, DTLB2_WRITES, 0x0081);
243
+CPUMF_EVENT_ATTR(cf_z15, DTLB2_MISSES, 0x0082);
244
+CPUMF_EVENT_ATTR(cf_z15, DTLB2_HPAGE_WRITES, 0x0083);
245
+CPUMF_EVENT_ATTR(cf_z15, DTLB2_GPAGE_WRITES, 0x0084);
246
+CPUMF_EVENT_ATTR(cf_z15, L1D_L2D_SOURCED_WRITES, 0x0085);
247
+CPUMF_EVENT_ATTR(cf_z15, ITLB2_WRITES, 0x0086);
248
+CPUMF_EVENT_ATTR(cf_z15, ITLB2_MISSES, 0x0087);
249
+CPUMF_EVENT_ATTR(cf_z15, L1I_L2I_SOURCED_WRITES, 0x0088);
250
+CPUMF_EVENT_ATTR(cf_z15, TLB2_PTE_WRITES, 0x0089);
251
+CPUMF_EVENT_ATTR(cf_z15, TLB2_CRSTE_WRITES, 0x008a);
252
+CPUMF_EVENT_ATTR(cf_z15, TLB2_ENGINES_BUSY, 0x008b);
253
+CPUMF_EVENT_ATTR(cf_z15, TX_C_TEND, 0x008c);
254
+CPUMF_EVENT_ATTR(cf_z15, TX_NC_TEND, 0x008d);
255
+CPUMF_EVENT_ATTR(cf_z15, L1C_TLB2_MISSES, 0x008f);
256
+CPUMF_EVENT_ATTR(cf_z15, L1D_ONCHIP_L3_SOURCED_WRITES, 0x0090);
257
+CPUMF_EVENT_ATTR(cf_z15, L1D_ONCHIP_MEMORY_SOURCED_WRITES, 0x0091);
258
+CPUMF_EVENT_ATTR(cf_z15, L1D_ONCHIP_L3_SOURCED_WRITES_IV, 0x0092);
259
+CPUMF_EVENT_ATTR(cf_z15, L1D_ONCLUSTER_L3_SOURCED_WRITES, 0x0093);
260
+CPUMF_EVENT_ATTR(cf_z15, L1D_ONCLUSTER_MEMORY_SOURCED_WRITES, 0x0094);
261
+CPUMF_EVENT_ATTR(cf_z15, L1D_ONCLUSTER_L3_SOURCED_WRITES_IV, 0x0095);
262
+CPUMF_EVENT_ATTR(cf_z15, L1D_OFFCLUSTER_L3_SOURCED_WRITES, 0x0096);
263
+CPUMF_EVENT_ATTR(cf_z15, L1D_OFFCLUSTER_MEMORY_SOURCED_WRITES, 0x0097);
264
+CPUMF_EVENT_ATTR(cf_z15, L1D_OFFCLUSTER_L3_SOURCED_WRITES_IV, 0x0098);
265
+CPUMF_EVENT_ATTR(cf_z15, L1D_OFFDRAWER_L3_SOURCED_WRITES, 0x0099);
266
+CPUMF_EVENT_ATTR(cf_z15, L1D_OFFDRAWER_MEMORY_SOURCED_WRITES, 0x009a);
267
+CPUMF_EVENT_ATTR(cf_z15, L1D_OFFDRAWER_L3_SOURCED_WRITES_IV, 0x009b);
268
+CPUMF_EVENT_ATTR(cf_z15, L1D_ONDRAWER_L4_SOURCED_WRITES, 0x009c);
269
+CPUMF_EVENT_ATTR(cf_z15, L1D_OFFDRAWER_L4_SOURCED_WRITES, 0x009d);
270
+CPUMF_EVENT_ATTR(cf_z15, L1D_ONCHIP_L3_SOURCED_WRITES_RO, 0x009e);
271
+CPUMF_EVENT_ATTR(cf_z15, L1I_ONCHIP_L3_SOURCED_WRITES, 0x00a2);
272
+CPUMF_EVENT_ATTR(cf_z15, L1I_ONCHIP_MEMORY_SOURCED_WRITES, 0x00a3);
273
+CPUMF_EVENT_ATTR(cf_z15, L1I_ONCHIP_L3_SOURCED_WRITES_IV, 0x00a4);
274
+CPUMF_EVENT_ATTR(cf_z15, L1I_ONCLUSTER_L3_SOURCED_WRITES, 0x00a5);
275
+CPUMF_EVENT_ATTR(cf_z15, L1I_ONCLUSTER_MEMORY_SOURCED_WRITES, 0x00a6);
276
+CPUMF_EVENT_ATTR(cf_z15, L1I_ONCLUSTER_L3_SOURCED_WRITES_IV, 0x00a7);
277
+CPUMF_EVENT_ATTR(cf_z15, L1I_OFFCLUSTER_L3_SOURCED_WRITES, 0x00a8);
278
+CPUMF_EVENT_ATTR(cf_z15, L1I_OFFCLUSTER_MEMORY_SOURCED_WRITES, 0x00a9);
279
+CPUMF_EVENT_ATTR(cf_z15, L1I_OFFCLUSTER_L3_SOURCED_WRITES_IV, 0x00aa);
280
+CPUMF_EVENT_ATTR(cf_z15, L1I_OFFDRAWER_L3_SOURCED_WRITES, 0x00ab);
281
+CPUMF_EVENT_ATTR(cf_z15, L1I_OFFDRAWER_MEMORY_SOURCED_WRITES, 0x00ac);
282
+CPUMF_EVENT_ATTR(cf_z15, L1I_OFFDRAWER_L3_SOURCED_WRITES_IV, 0x00ad);
283
+CPUMF_EVENT_ATTR(cf_z15, L1I_ONDRAWER_L4_SOURCED_WRITES, 0x00ae);
284
+CPUMF_EVENT_ATTR(cf_z15, L1I_OFFDRAWER_L4_SOURCED_WRITES, 0x00af);
285
+CPUMF_EVENT_ATTR(cf_z15, BCD_DFP_EXECUTION_SLOTS, 0x00e0);
286
+CPUMF_EVENT_ATTR(cf_z15, VX_BCD_EXECUTION_SLOTS, 0x00e1);
287
+CPUMF_EVENT_ATTR(cf_z15, DECIMAL_INSTRUCTIONS, 0x00e2);
288
+CPUMF_EVENT_ATTR(cf_z15, LAST_HOST_TRANSLATIONS, 0x00e8);
289
+CPUMF_EVENT_ATTR(cf_z15, TX_NC_TABORT, 0x00f3);
290
+CPUMF_EVENT_ATTR(cf_z15, TX_C_TABORT_NO_SPECIAL, 0x00f4);
291
+CPUMF_EVENT_ATTR(cf_z15, TX_C_TABORT_SPECIAL, 0x00f5);
292
+CPUMF_EVENT_ATTR(cf_z15, DFLT_ACCESS, 0x00f7);
293
+CPUMF_EVENT_ATTR(cf_z15, DFLT_CYCLES, 0x00fc);
294
+CPUMF_EVENT_ATTR(cf_z15, DFLT_CC, 0x00108);
295
+CPUMF_EVENT_ATTR(cf_z15, DFLT_CCFINISH, 0x00109);
296
+CPUMF_EVENT_ATTR(cf_z15, MT_DIAG_CYCLES_ONE_THR_ACTIVE, 0x01c0);
297
+CPUMF_EVENT_ATTR(cf_z15, MT_DIAG_CYCLES_TWO_THR_ACTIVE, 0x01c1);
298
+
236
299
 static struct attribute *cpumcf_fvn1_pmu_event_attr[] __initdata = {
237
300
 	CPUMF_EVENT_PTR(cf_fvn1, CPU_CYCLES),
238
301
 	CPUMF_EVENT_PTR(cf_fvn1, INSTRUCTIONS),
..
..
@@ -261,23 +324,47 @@
261
324
 	NULL,
262
325
 };
263
326
 
264
-static struct attribute *cpumcf_svn_generic_pmu_event_attr[] __initdata = {
265
-	CPUMF_EVENT_PTR(cf_svn_generic, PRNG_FUNCTIONS),
266
-	CPUMF_EVENT_PTR(cf_svn_generic, PRNG_CYCLES),
267
-	CPUMF_EVENT_PTR(cf_svn_generic, PRNG_BLOCKED_FUNCTIONS),
268
-	CPUMF_EVENT_PTR(cf_svn_generic, PRNG_BLOCKED_CYCLES),
269
-	CPUMF_EVENT_PTR(cf_svn_generic, SHA_FUNCTIONS),
270
-	CPUMF_EVENT_PTR(cf_svn_generic, SHA_CYCLES),
271
-	CPUMF_EVENT_PTR(cf_svn_generic, SHA_BLOCKED_FUNCTIONS),
272
-	CPUMF_EVENT_PTR(cf_svn_generic, SHA_BLOCKED_CYCLES),
273
-	CPUMF_EVENT_PTR(cf_svn_generic, DEA_FUNCTIONS),
274
-	CPUMF_EVENT_PTR(cf_svn_generic, DEA_CYCLES),
275
-	CPUMF_EVENT_PTR(cf_svn_generic, DEA_BLOCKED_FUNCTIONS),
276
-	CPUMF_EVENT_PTR(cf_svn_generic, DEA_BLOCKED_CYCLES),
277
-	CPUMF_EVENT_PTR(cf_svn_generic, AES_FUNCTIONS),
278
-	CPUMF_EVENT_PTR(cf_svn_generic, AES_CYCLES),
279
-	CPUMF_EVENT_PTR(cf_svn_generic, AES_BLOCKED_FUNCTIONS),
280
-	CPUMF_EVENT_PTR(cf_svn_generic, AES_BLOCKED_CYCLES),
327
+static struct attribute *cpumcf_svn_12345_pmu_event_attr[] __initdata = {
328
+	CPUMF_EVENT_PTR(cf_svn_12345, PRNG_FUNCTIONS),
329
+	CPUMF_EVENT_PTR(cf_svn_12345, PRNG_CYCLES),
330
+	CPUMF_EVENT_PTR(cf_svn_12345, PRNG_BLOCKED_FUNCTIONS),
331
+	CPUMF_EVENT_PTR(cf_svn_12345, PRNG_BLOCKED_CYCLES),
332
+	CPUMF_EVENT_PTR(cf_svn_12345, SHA_FUNCTIONS),
333
+	CPUMF_EVENT_PTR(cf_svn_12345, SHA_CYCLES),
334
+	CPUMF_EVENT_PTR(cf_svn_12345, SHA_BLOCKED_FUNCTIONS),
335
+	CPUMF_EVENT_PTR(cf_svn_12345, SHA_BLOCKED_CYCLES),
336
+	CPUMF_EVENT_PTR(cf_svn_12345, DEA_FUNCTIONS),
337
+	CPUMF_EVENT_PTR(cf_svn_12345, DEA_CYCLES),
338
+	CPUMF_EVENT_PTR(cf_svn_12345, DEA_BLOCKED_FUNCTIONS),
339
+	CPUMF_EVENT_PTR(cf_svn_12345, DEA_BLOCKED_CYCLES),
340
+	CPUMF_EVENT_PTR(cf_svn_12345, AES_FUNCTIONS),
341
+	CPUMF_EVENT_PTR(cf_svn_12345, AES_CYCLES),
342
+	CPUMF_EVENT_PTR(cf_svn_12345, AES_BLOCKED_FUNCTIONS),
343
+	CPUMF_EVENT_PTR(cf_svn_12345, AES_BLOCKED_CYCLES),
344
+	NULL,
345
+};
346
+
347
+static struct attribute *cpumcf_svn_6_pmu_event_attr[] __initdata = {
348
+	CPUMF_EVENT_PTR(cf_svn_12345, PRNG_FUNCTIONS),
349
+	CPUMF_EVENT_PTR(cf_svn_12345, PRNG_CYCLES),
350
+	CPUMF_EVENT_PTR(cf_svn_12345, PRNG_BLOCKED_FUNCTIONS),
351
+	CPUMF_EVENT_PTR(cf_svn_12345, PRNG_BLOCKED_CYCLES),
352
+	CPUMF_EVENT_PTR(cf_svn_12345, SHA_FUNCTIONS),
353
+	CPUMF_EVENT_PTR(cf_svn_12345, SHA_CYCLES),
354
+	CPUMF_EVENT_PTR(cf_svn_12345, SHA_BLOCKED_FUNCTIONS),
355
+	CPUMF_EVENT_PTR(cf_svn_12345, SHA_BLOCKED_CYCLES),
356
+	CPUMF_EVENT_PTR(cf_svn_12345, DEA_FUNCTIONS),
357
+	CPUMF_EVENT_PTR(cf_svn_12345, DEA_CYCLES),
358
+	CPUMF_EVENT_PTR(cf_svn_12345, DEA_BLOCKED_FUNCTIONS),
359
+	CPUMF_EVENT_PTR(cf_svn_12345, DEA_BLOCKED_CYCLES),
360
+	CPUMF_EVENT_PTR(cf_svn_12345, AES_FUNCTIONS),
361
+	CPUMF_EVENT_PTR(cf_svn_12345, AES_CYCLES),
362
+	CPUMF_EVENT_PTR(cf_svn_12345, AES_BLOCKED_FUNCTIONS),
363
+	CPUMF_EVENT_PTR(cf_svn_12345, AES_BLOCKED_CYCLES),
364
+	CPUMF_EVENT_PTR(cf_svn_6, ECC_FUNCTION_COUNT),
365
+	CPUMF_EVENT_PTR(cf_svn_6, ECC_CYCLES_COUNT),
366
+	CPUMF_EVENT_PTR(cf_svn_6, ECC_BLOCKED_FUNCTION_COUNT),
367
+	CPUMF_EVENT_PTR(cf_svn_6, ECC_BLOCKED_CYCLES_COUNT),
281
368
 	NULL,
282
369
 };
283
370
 
..
..
@@ -487,6 +574,67 @@
487
574
 	NULL,
488
575
 };
489
576
 
577
+static struct attribute *cpumcf_z15_pmu_event_attr[] __initdata = {
578
+	CPUMF_EVENT_PTR(cf_z15, L1D_RO_EXCL_WRITES),
579
+	CPUMF_EVENT_PTR(cf_z15, DTLB2_WRITES),
580
+	CPUMF_EVENT_PTR(cf_z15, DTLB2_MISSES),
581
+	CPUMF_EVENT_PTR(cf_z15, DTLB2_HPAGE_WRITES),
582
+	CPUMF_EVENT_PTR(cf_z15, DTLB2_GPAGE_WRITES),
583
+	CPUMF_EVENT_PTR(cf_z15, L1D_L2D_SOURCED_WRITES),
584
+	CPUMF_EVENT_PTR(cf_z15, ITLB2_WRITES),
585
+	CPUMF_EVENT_PTR(cf_z15, ITLB2_MISSES),
586
+	CPUMF_EVENT_PTR(cf_z15, L1I_L2I_SOURCED_WRITES),
587
+	CPUMF_EVENT_PTR(cf_z15, TLB2_PTE_WRITES),
588
+	CPUMF_EVENT_PTR(cf_z15, TLB2_CRSTE_WRITES),
589
+	CPUMF_EVENT_PTR(cf_z15, TLB2_ENGINES_BUSY),
590
+	CPUMF_EVENT_PTR(cf_z15, TX_C_TEND),
591
+	CPUMF_EVENT_PTR(cf_z15, TX_NC_TEND),
592
+	CPUMF_EVENT_PTR(cf_z15, L1C_TLB2_MISSES),
593
+	CPUMF_EVENT_PTR(cf_z15, L1D_ONCHIP_L3_SOURCED_WRITES),
594
+	CPUMF_EVENT_PTR(cf_z15, L1D_ONCHIP_MEMORY_SOURCED_WRITES),
595
+	CPUMF_EVENT_PTR(cf_z15, L1D_ONCHIP_L3_SOURCED_WRITES_IV),
596
+	CPUMF_EVENT_PTR(cf_z15, L1D_ONCLUSTER_L3_SOURCED_WRITES),
597
+	CPUMF_EVENT_PTR(cf_z15, L1D_ONCLUSTER_MEMORY_SOURCED_WRITES),
598
+	CPUMF_EVENT_PTR(cf_z15, L1D_ONCLUSTER_L3_SOURCED_WRITES_IV),
599
+	CPUMF_EVENT_PTR(cf_z15, L1D_OFFCLUSTER_L3_SOURCED_WRITES),
600
+	CPUMF_EVENT_PTR(cf_z15, L1D_OFFCLUSTER_MEMORY_SOURCED_WRITES),
601
+	CPUMF_EVENT_PTR(cf_z15, L1D_OFFCLUSTER_L3_SOURCED_WRITES_IV),
602
+	CPUMF_EVENT_PTR(cf_z15, L1D_OFFDRAWER_L3_SOURCED_WRITES),
603
+	CPUMF_EVENT_PTR(cf_z15, L1D_OFFDRAWER_MEMORY_SOURCED_WRITES),
604
+	CPUMF_EVENT_PTR(cf_z15, L1D_OFFDRAWER_L3_SOURCED_WRITES_IV),
605
+	CPUMF_EVENT_PTR(cf_z15, L1D_ONDRAWER_L4_SOURCED_WRITES),
606
+	CPUMF_EVENT_PTR(cf_z15, L1D_OFFDRAWER_L4_SOURCED_WRITES),
607
+	CPUMF_EVENT_PTR(cf_z15, L1D_ONCHIP_L3_SOURCED_WRITES_RO),
608
+	CPUMF_EVENT_PTR(cf_z15, L1I_ONCHIP_L3_SOURCED_WRITES),
609
+	CPUMF_EVENT_PTR(cf_z15, L1I_ONCHIP_MEMORY_SOURCED_WRITES),
610
+	CPUMF_EVENT_PTR(cf_z15, L1I_ONCHIP_L3_SOURCED_WRITES_IV),
611
+	CPUMF_EVENT_PTR(cf_z15, L1I_ONCLUSTER_L3_SOURCED_WRITES),
612
+	CPUMF_EVENT_PTR(cf_z15, L1I_ONCLUSTER_MEMORY_SOURCED_WRITES),
613
+	CPUMF_EVENT_PTR(cf_z15, L1I_ONCLUSTER_L3_SOURCED_WRITES_IV),
614
+	CPUMF_EVENT_PTR(cf_z15, L1I_OFFCLUSTER_L3_SOURCED_WRITES),
615
+	CPUMF_EVENT_PTR(cf_z15, L1I_OFFCLUSTER_MEMORY_SOURCED_WRITES),
616
+	CPUMF_EVENT_PTR(cf_z15, L1I_OFFCLUSTER_L3_SOURCED_WRITES_IV),
617
+	CPUMF_EVENT_PTR(cf_z15, L1I_OFFDRAWER_L3_SOURCED_WRITES),
618
+	CPUMF_EVENT_PTR(cf_z15, L1I_OFFDRAWER_MEMORY_SOURCED_WRITES),
619
+	CPUMF_EVENT_PTR(cf_z15, L1I_OFFDRAWER_L3_SOURCED_WRITES_IV),
620
+	CPUMF_EVENT_PTR(cf_z15, L1I_ONDRAWER_L4_SOURCED_WRITES),
621
+	CPUMF_EVENT_PTR(cf_z15, L1I_OFFDRAWER_L4_SOURCED_WRITES),
622
+	CPUMF_EVENT_PTR(cf_z15, BCD_DFP_EXECUTION_SLOTS),
623
+	CPUMF_EVENT_PTR(cf_z15, VX_BCD_EXECUTION_SLOTS),
624
+	CPUMF_EVENT_PTR(cf_z15, DECIMAL_INSTRUCTIONS),
625
+	CPUMF_EVENT_PTR(cf_z15, LAST_HOST_TRANSLATIONS),
626
+	CPUMF_EVENT_PTR(cf_z15, TX_NC_TABORT),
627
+	CPUMF_EVENT_PTR(cf_z15, TX_C_TABORT_NO_SPECIAL),
628
+	CPUMF_EVENT_PTR(cf_z15, TX_C_TABORT_SPECIAL),
629
+	CPUMF_EVENT_PTR(cf_z15, DFLT_ACCESS),
630
+	CPUMF_EVENT_PTR(cf_z15, DFLT_CYCLES),
631
+	CPUMF_EVENT_PTR(cf_z15, DFLT_CC),
632
+	CPUMF_EVENT_PTR(cf_z15, DFLT_CCFINISH),
633
+	CPUMF_EVENT_PTR(cf_z15, MT_DIAG_CYCLES_ONE_THR_ACTIVE),
634
+	CPUMF_EVENT_PTR(cf_z15, MT_DIAG_CYCLES_TWO_THR_ACTIVE),
635
+	NULL,
636
+};
637
+
490
638
 /* END: CPUM_CF COUNTER DEFINITIONS ===================================== */
491
639
 
492
640
 static struct attribute_group cpumcf_pmu_events_group = {
..
..
@@ -561,7 +709,18 @@
561
709
 	default:
562
710
 		cfvn = none;
563
711
 	}
564
-	csvn = cpumcf_svn_generic_pmu_event_attr;
712
+
713
+	/* Determine version specific crypto set */
714
+	switch (ci.csvn) {
715
+	case 1 ... 5:
716
+		csvn = cpumcf_svn_12345_pmu_event_attr;
717
+		break;
718
+	case 6:
719
+		csvn = cpumcf_svn_6_pmu_event_attr;
720
+		break;
721
+	default:
722
+		csvn = none;
723
+	}
565
724
 
566
725
 	/* Determine model-specific counter set(s) */
567
726
 	get_cpu_id(&cpu_id);
..
..
@@ -586,6 +745,10 @@
586
745
 	case 0x3907:
587
746
 		model = cpumcf_z14_pmu_event_attr;
588
747
 		break;
748
+	case 0x8561:
749
+	case 0x8562:
750
+		model = cpumcf_z15_pmu_event_attr;
751
+		break;
589
752
 	default:
590
753
 		model = none;
591
754
 		break;