| .. | .. |
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| 1 | +// SPDX-License-Identifier: GPL-2.0-or-later |
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| 1 | 2 | /* |
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| 2 | 3 | * Performance event support - Freescale Embedded Performance Monitor |
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| 3 | 4 | * |
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| 4 | 5 | * Copyright 2008-2009 Paul Mackerras, IBM Corporation. |
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| 5 | 6 | * Copyright 2010 Freescale Semiconductor, Inc. |
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| 6 | | - * |
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| 7 | | - * This program is free software; you can redistribute it and/or |
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| 8 | | - * modify it under the terms of the GNU General Public License |
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| 9 | | - * as published by the Free Software Foundation; either version |
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| 10 | | - * 2 of the License, or (at your option) any later version. |
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| 11 | 7 | */ |
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| 12 | 8 | #include <linux/kernel.h> |
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| 13 | 9 | #include <linux/sched.h> |
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| .. | .. |
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| 34 | 30 | static atomic_t num_events; |
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| 35 | 31 | /* Used to avoid races in calling reserve/release_pmc_hardware */ |
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| 36 | 32 | static DEFINE_MUTEX(pmc_reserve_mutex); |
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| 37 | | - |
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| 38 | | -/* |
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| 39 | | - * If interrupts were soft-disabled when a PMU interrupt occurs, treat |
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| 40 | | - * it as an NMI. |
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| 41 | | - */ |
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| 42 | | -static inline int perf_intr_is_nmi(struct pt_regs *regs) |
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| 43 | | -{ |
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| 44 | | -#ifdef __powerpc64__ |
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| 45 | | - return (regs->softe & IRQS_DISABLED); |
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| 46 | | -#else |
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| 47 | | - return 0; |
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| 48 | | -#endif |
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| 49 | | -} |
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| 50 | 33 | |
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| 51 | 34 | static void perf_event_interrupt(struct pt_regs *regs); |
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| 52 | 35 | |
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| .. | .. |
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| 662 | 645 | struct cpu_hw_events *cpuhw = this_cpu_ptr(&cpu_hw_events); |
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| 663 | 646 | struct perf_event *event; |
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| 664 | 647 | unsigned long val; |
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| 665 | | - int found = 0; |
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| 666 | | - int nmi; |
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| 667 | | - |
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| 668 | | - nmi = perf_intr_is_nmi(regs); |
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| 669 | | - if (nmi) |
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| 670 | | - nmi_enter(); |
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| 671 | | - else |
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| 672 | | - irq_enter(); |
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| 673 | 648 | |
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| 674 | 649 | for (i = 0; i < ppmu->n_counter; ++i) { |
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| 675 | 650 | event = cpuhw->event[i]; |
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| .. | .. |
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| 678 | 653 | if ((int)val < 0) { |
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| 679 | 654 | if (event) { |
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| 680 | 655 | /* event has overflowed */ |
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| 681 | | - found = 1; |
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| 682 | 656 | record_and_restart(event, val, regs); |
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| 683 | 657 | } else { |
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| 684 | 658 | /* |
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| .. | .. |
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| 694 | 668 | mtmsr(mfmsr() | MSR_PMM); |
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| 695 | 669 | mtpmr(PMRN_PMGC0, PMGC0_PMIE | PMGC0_FCECE); |
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| 696 | 670 | isync(); |
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| 697 | | - |
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| 698 | | - if (nmi) |
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| 699 | | - nmi_exit(); |
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| 700 | | - else |
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| 701 | | - irq_exit(); |
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| 702 | 671 | } |
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| 703 | 672 | |
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| 704 | | -void hw_perf_event_setup(int cpu) |
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| 673 | +static int fsl_emb_pmu_prepare_cpu(unsigned int cpu) |
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| 705 | 674 | { |
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| 706 | 675 | struct cpu_hw_events *cpuhw = &per_cpu(cpu_hw_events, cpu); |
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| 707 | 676 | |
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| 708 | 677 | memset(cpuhw, 0, sizeof(*cpuhw)); |
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| 678 | + |
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| 679 | + return 0; |
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| 709 | 680 | } |
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| 710 | 681 | |
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| 711 | 682 | int register_fsl_emb_pmu(struct fsl_emb_pmu *pmu) |
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| .. | .. |
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| 718 | 689 | pmu->name); |
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| 719 | 690 | |
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| 720 | 691 | perf_pmu_register(&fsl_emb_pmu, "cpu", PERF_TYPE_RAW); |
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| 692 | + cpuhp_setup_state(CPUHP_PERF_POWER, "perf/powerpc:prepare", |
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| 693 | + fsl_emb_pmu_prepare_cpu, NULL); |
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| 721 | 694 | |
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| 722 | 695 | return 0; |
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| 723 | 696 | } |
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