~hc/RK356X_SDK_RELEASE.git

..	..	@@ -1,3 +1,4 @@
	1	+// SPDX-License-Identifier: GPL-2.0-only
1	2	#include <linux/device.h>
2	3	#include <linux/cpu.h>
3	4	#include <linux/smp.h>
..	..	@@ -18,6 +19,8 @@
18	19	#include <asm/smp.h>
19	20	#include <asm/pmc.h>
20	21	#include <asm/firmware.h>
	22	+#include <asm/idle.h>
	23	+#include <asm/svm.h>
21	24
22	25	#include "cacheinfo.h"
23	26	#include "setup.h"
..	..	@@ -75,6 +78,154 @@
75	78	}
76	79	__setup("smt-snooze-delay=", setup_smt_snooze_delay);
77	80
	81	+#endif /* CONFIG_PPC64 */
	82	+
	83	+#define __SYSFS_SPRSETUP_READ_WRITE(NAME, ADDRESS, EXTRA) \
	84	+static void read_##NAME(void *val) \
	85	+{ \
	86	+ (unsigned long )val = mfspr(ADDRESS); \
	87	+} \
	88	+static void write_##NAME(void *val) \
	89	+{ \
	90	+ EXTRA; \
	91	+ mtspr(ADDRESS, (unsigned long )val); \
	92	+}
	93	+
	94	+#define __SYSFS_SPRSETUP_SHOW_STORE(NAME) \
	95	+static ssize_t show_##NAME(struct device *dev, \
	96	+ struct device_attribute *attr, \
	97	+ char *buf) \
	98	+{ \
	99	+ struct cpu *cpu = container_of(dev, struct cpu, dev); \
	100	+ unsigned long val; \
	101	+ smp_call_function_single(cpu->dev.id, read_##NAME, &val, 1); \
	102	+ return sprintf(buf, "%lx\n", val); \
	103	+} \
	104	+static ssize_t __used \
	105	+ store_##NAME(struct device dev, struct device_attribute attr, \
	106	+ const char *buf, size_t count) \
	107	+{ \
	108	+ struct cpu *cpu = container_of(dev, struct cpu, dev); \
	109	+ unsigned long val; \
	110	+ int ret = sscanf(buf, "%lx", &val); \
	111	+ if (ret != 1) \
	112	+ return -EINVAL; \
	113	+ smp_call_function_single(cpu->dev.id, write_##NAME, &val, 1); \
	114	+ return count; \
	115	+}
	116	+
	117	+#define SYSFS_PMCSETUP(NAME, ADDRESS) \
	118	+ __SYSFS_SPRSETUP_READ_WRITE(NAME, ADDRESS, ppc_enable_pmcs()) \
	119	+ __SYSFS_SPRSETUP_SHOW_STORE(NAME)
	120	+#define SYSFS_SPRSETUP(NAME, ADDRESS) \
	121	+ __SYSFS_SPRSETUP_READ_WRITE(NAME, ADDRESS, ) \
	122	+ __SYSFS_SPRSETUP_SHOW_STORE(NAME)
	123	+
	124	+#define SYSFS_SPRSETUP_SHOW_STORE(NAME) \
	125	+ __SYSFS_SPRSETUP_SHOW_STORE(NAME)
	126	+
	127	+#ifdef CONFIG_PPC64
	128	+
	129	+/*
	130	+ * This is the system wide DSCR register default value. Any
	131	+ * change to this default value through the sysfs interface
	132	+ * will update all per cpu DSCR default values across the
	133	+ * system stored in their respective PACA structures.
	134	+ */
	135	+static unsigned long dscr_default;
	136	+
	137	+/**
	138	+ * read_dscr() - Fetch the cpu specific DSCR default
	139	+ * @val: Returned cpu specific DSCR default value
	140	+ *
	141	+ * This function returns the per cpu DSCR default value
	142	+ * for any cpu which is contained in it's PACA structure.
	143	+ */
	144	+static void read_dscr(void *val)
	145	+{
	146	+ (unsigned long )val = get_paca()->dscr_default;
	147	+}
	148	+
	149	+
	150	+/**
	151	+ * write_dscr() - Update the cpu specific DSCR default
	152	+ * @val: New cpu specific DSCR default value to update
	153	+ *
	154	+ * This function updates the per cpu DSCR default value
	155	+ * for any cpu which is contained in it's PACA structure.
	156	+ */
	157	+static void write_dscr(void *val)
	158	+{
	159	+ get_paca()->dscr_default = (unsigned long )val;
	160	+ if (!current->thread.dscr_inherit) {
	161	+ current->thread.dscr = (unsigned long )val;
	162	+ mtspr(SPRN_DSCR, (unsigned long )val);
	163	+ }
	164	+}
	165	+
	166	+SYSFS_SPRSETUP_SHOW_STORE(dscr);
	167	+static DEVICE_ATTR(dscr, 0600, show_dscr, store_dscr);
	168	+
	169	+static void add_write_permission_dev_attr(struct device_attribute *attr)
	170	+{
	171	+ attr->attr.mode \|= 0200;
	172	+}
	173	+
	174	+/**
	175	+ * show_dscr_default() - Fetch the system wide DSCR default
	176	+ * @dev: Device structure
	177	+ * @attr: Device attribute structure
	178	+ * @buf: Interface buffer
	179	+ *
	180	+ * This function returns the system wide DSCR default value.
	181	+ */
	182	+static ssize_t show_dscr_default(struct device *dev,
	183	+ struct device_attribute attr, char buf)
	184	+{
	185	+ return sprintf(buf, "%lx\n", dscr_default);
	186	+}
	187	+
	188	+/**
	189	+ * store_dscr_default() - Update the system wide DSCR default
	190	+ * @dev: Device structure
	191	+ * @attr: Device attribute structure
	192	+ * @buf: Interface buffer
	193	+ * @count: Size of the update
	194	+ *
	195	+ * This function updates the system wide DSCR default value.
	196	+ */
	197	+static ssize_t __used store_dscr_default(struct device *dev,
	198	+ struct device_attribute attr, const char buf,
	199	+ size_t count)
	200	+{
	201	+ unsigned long val;
	202	+ int ret = 0;
	203	+
	204	+ ret = sscanf(buf, "%lx", &val);
	205	+ if (ret != 1)
	206	+ return -EINVAL;
	207	+ dscr_default = val;
	208	+
	209	+ on_each_cpu(write_dscr, &val, 1);
	210	+
	211	+ return count;
	212	+}
	213	+
	214	+static DEVICE_ATTR(dscr_default, 0600,
	215	+ show_dscr_default, store_dscr_default);
	216	+
	217	+static void sysfs_create_dscr_default(void)
	218	+{
	219	+ if (cpu_has_feature(CPU_FTR_DSCR)) {
	220	+ int cpu;
	221	+
	222	+ dscr_default = spr_default_dscr;
	223	+ for_each_possible_cpu(cpu)
	224	+ paca_ptrs[cpu]->dscr_default = dscr_default;
	225	+
	226	+ device_create_file(cpu_subsys.dev_root, &dev_attr_dscr_default);
	227	+ }
	228	+}
78	229	#endif /* CONFIG_PPC64 */
79	230
80	231	#ifdef CONFIG_PPC_FSL_BOOK3E
..	..	@@ -397,84 +548,35 @@
397	548	}
398	549	EXPORT_SYMBOL(ppc_enable_pmcs);
399	550
400		-#define __SYSFS_SPRSETUP_READ_WRITE(NAME, ADDRESS, EXTRA) \
401		-static void read_##NAME(void *val) \
402		-{ \
403		- (unsigned long )val = mfspr(ADDRESS); \
404		-} \
405		-static void write_##NAME(void *val) \
406		-{ \
407		- EXTRA; \
408		- mtspr(ADDRESS, (unsigned long )val); \
409		-}
410	551
411		-#define __SYSFS_SPRSETUP_SHOW_STORE(NAME) \
412		-static ssize_t show_##NAME(struct device *dev, \
413		- struct device_attribute *attr, \
414		- char *buf) \
415		-{ \
416		- struct cpu *cpu = container_of(dev, struct cpu, dev); \
417		- unsigned long val; \
418		- smp_call_function_single(cpu->dev.id, read_##NAME, &val, 1); \
419		- return sprintf(buf, "%lx\n", val); \
420		-} \
421		-static ssize_t __used \
422		- store_##NAME(struct device dev, struct device_attribute attr, \
423		- const char *buf, size_t count) \
424		-{ \
425		- struct cpu *cpu = container_of(dev, struct cpu, dev); \
426		- unsigned long val; \
427		- int ret = sscanf(buf, "%lx", &val); \
428		- if (ret != 1) \
429		- return -EINVAL; \
430		- smp_call_function_single(cpu->dev.id, write_##NAME, &val, 1); \
431		- return count; \
432		-}
433		-
434		-#define SYSFS_PMCSETUP(NAME, ADDRESS) \
435		- __SYSFS_SPRSETUP_READ_WRITE(NAME, ADDRESS, ppc_enable_pmcs()) \
436		- __SYSFS_SPRSETUP_SHOW_STORE(NAME)
437		-#define SYSFS_SPRSETUP(NAME, ADDRESS) \
438		- __SYSFS_SPRSETUP_READ_WRITE(NAME, ADDRESS, ) \
439		- __SYSFS_SPRSETUP_SHOW_STORE(NAME)
440		-
441		-#define SYSFS_SPRSETUP_SHOW_STORE(NAME) \
442		- __SYSFS_SPRSETUP_SHOW_STORE(NAME)
443	552
444	553	/* Let's define all possible registers, we'll only hook up the ones
445	554	* that are implemented on the current processor
446	555	*/
447	556
448		-#if defined(CONFIG_PPC64)
	557	+#ifdef CONFIG_PMU_SYSFS
	558	+#if defined(CONFIG_PPC64) \|\| defined(CONFIG_PPC_BOOK3S_32)
449	559	#define HAS_PPC_PMC_CLASSIC 1
450	560	#define HAS_PPC_PMC_IBM 1
451		-#define HAS_PPC_PMC_PA6T 1
452		-#elif defined(CONFIG_6xx)
453		-#define HAS_PPC_PMC_CLASSIC 1
454		-#define HAS_PPC_PMC_IBM 1
455		-#define HAS_PPC_PMC_G4 1
456		-#endif
457		-
458		-
459		-#ifdef HAS_PPC_PMC_CLASSIC
460		-SYSFS_PMCSETUP(mmcr0, SPRN_MMCR0);
461		-SYSFS_PMCSETUP(mmcr1, SPRN_MMCR1);
462		-SYSFS_PMCSETUP(pmc1, SPRN_PMC1);
463		-SYSFS_PMCSETUP(pmc2, SPRN_PMC2);
464		-SYSFS_PMCSETUP(pmc3, SPRN_PMC3);
465		-SYSFS_PMCSETUP(pmc4, SPRN_PMC4);
466		-SYSFS_PMCSETUP(pmc5, SPRN_PMC5);
467		-SYSFS_PMCSETUP(pmc6, SPRN_PMC6);
468		-
469		-#ifdef HAS_PPC_PMC_G4
470		-SYSFS_PMCSETUP(mmcr2, SPRN_MMCR2);
471	561	#endif
472	562
473	563	#ifdef CONFIG_PPC64
474		-SYSFS_PMCSETUP(pmc7, SPRN_PMC7);
475		-SYSFS_PMCSETUP(pmc8, SPRN_PMC8);
	564	+#define HAS_PPC_PMC_PA6T 1
	565	+#define HAS_PPC_PMC56 1
	566	+#endif
476	567
477		-SYSFS_PMCSETUP(mmcra, SPRN_MMCRA);
	568	+#ifdef CONFIG_PPC_BOOK3S_32
	569	+#define HAS_PPC_PMC_G4 1
	570	+#endif
	571	+#endif /* CONFIG_PMU_SYSFS */
	572	+
	573	+#if defined(CONFIG_PPC64) && defined(CONFIG_DEBUG_MISC)
	574	+#define HAS_PPC_PA6T
	575	+#endif
	576	+/*
	577	+ * SPRs which are not related to PMU.
	578	+ */
	579	+#ifdef CONFIG_PPC64
478	580	SYSFS_SPRSETUP(purr, SPRN_PURR);
479	581	SYSFS_SPRSETUP(spurr, SPRN_SPURR);
480	582	SYSFS_SPRSETUP(pir, SPRN_PIR);
..	..	@@ -485,115 +587,40 @@
485	587	enable write when needed with a separate function.
486	588	Lets be conservative and default to pseries.
487	589	*/
488		-static DEVICE_ATTR(mmcra, 0600, show_mmcra, store_mmcra);
489	590	static DEVICE_ATTR(spurr, 0400, show_spurr, NULL);
490	591	static DEVICE_ATTR(purr, 0400, show_purr, store_purr);
491	592	static DEVICE_ATTR(pir, 0400, show_pir, NULL);
492	593	static DEVICE_ATTR(tscr, 0600, show_tscr, store_tscr);
493		-
494		-/*
495		- * This is the system wide DSCR register default value. Any
496		- * change to this default value through the sysfs interface
497		- * will update all per cpu DSCR default values across the
498		- * system stored in their respective PACA structures.
499		- */
500		-static unsigned long dscr_default;
501		-
502		-/**
503		- * read_dscr() - Fetch the cpu specific DSCR default
504		- * @val: Returned cpu specific DSCR default value
505		- *
506		- * This function returns the per cpu DSCR default value
507		- * for any cpu which is contained in it's PACA structure.
508		- */
509		-static void read_dscr(void *val)
510		-{
511		- (unsigned long )val = get_paca()->dscr_default;
512		-}
513		-
514		-
515		-/**
516		- * write_dscr() - Update the cpu specific DSCR default
517		- * @val: New cpu specific DSCR default value to update
518		- *
519		- * This function updates the per cpu DSCR default value
520		- * for any cpu which is contained in it's PACA structure.
521		- */
522		-static void write_dscr(void *val)
523		-{
524		- get_paca()->dscr_default = (unsigned long )val;
525		- if (!current->thread.dscr_inherit) {
526		- current->thread.dscr = (unsigned long )val;
527		- mtspr(SPRN_DSCR, (unsigned long )val);
528		- }
529		-}
530		-
531		-SYSFS_SPRSETUP_SHOW_STORE(dscr);
532		-static DEVICE_ATTR(dscr, 0600, show_dscr, store_dscr);
533		-
534		-static void add_write_permission_dev_attr(struct device_attribute *attr)
535		-{
536		- attr->attr.mode \|= 0200;
537		-}
538		-
539		-/**
540		- * show_dscr_default() - Fetch the system wide DSCR default
541		- * @dev: Device structure
542		- * @attr: Device attribute structure
543		- * @buf: Interface buffer
544		- *
545		- * This function returns the system wide DSCR default value.
546		- */
547		-static ssize_t show_dscr_default(struct device *dev,
548		- struct device_attribute attr, char buf)
549		-{
550		- return sprintf(buf, "%lx\n", dscr_default);
551		-}
552		-
553		-/**
554		- * store_dscr_default() - Update the system wide DSCR default
555		- * @dev: Device structure
556		- * @attr: Device attribute structure
557		- * @buf: Interface buffer
558		- * @count: Size of the update
559		- *
560		- * This function updates the system wide DSCR default value.
561		- */
562		-static ssize_t __used store_dscr_default(struct device *dev,
563		- struct device_attribute attr, const char buf,
564		- size_t count)
565		-{
566		- unsigned long val;
567		- int ret = 0;
568		-
569		- ret = sscanf(buf, "%lx", &val);
570		- if (ret != 1)
571		- return -EINVAL;
572		- dscr_default = val;
573		-
574		- on_each_cpu(write_dscr, &val, 1);
575		-
576		- return count;
577		-}
578		-
579		-static DEVICE_ATTR(dscr_default, 0600,
580		- show_dscr_default, store_dscr_default);
581		-
582		-static void sysfs_create_dscr_default(void)
583		-{
584		- if (cpu_has_feature(CPU_FTR_DSCR)) {
585		- int err = 0;
586		- int cpu;
587		-
588		- dscr_default = spr_default_dscr;
589		- for_each_possible_cpu(cpu)
590		- paca_ptrs[cpu]->dscr_default = dscr_default;
591		-
592		- err = device_create_file(cpu_subsys.dev_root, &dev_attr_dscr_default);
593		- }
594		-}
595		-
596	594	#endif /* CONFIG_PPC64 */
	595	+
	596	+#ifdef HAS_PPC_PMC_CLASSIC
	597	+SYSFS_PMCSETUP(mmcr0, SPRN_MMCR0);
	598	+SYSFS_PMCSETUP(mmcr1, SPRN_MMCR1);
	599	+SYSFS_PMCSETUP(pmc1, SPRN_PMC1);
	600	+SYSFS_PMCSETUP(pmc2, SPRN_PMC2);
	601	+SYSFS_PMCSETUP(pmc3, SPRN_PMC3);
	602	+SYSFS_PMCSETUP(pmc4, SPRN_PMC4);
	603	+SYSFS_PMCSETUP(pmc5, SPRN_PMC5);
	604	+SYSFS_PMCSETUP(pmc6, SPRN_PMC6);
	605	+#endif
	606	+
	607	+#ifdef HAS_PPC_PMC_G4
	608	+SYSFS_PMCSETUP(mmcr2, SPRN_MMCR2);
	609	+#endif
	610	+
	611	+#ifdef HAS_PPC_PMC56
	612	+SYSFS_PMCSETUP(pmc7, SPRN_PMC7);
	613	+SYSFS_PMCSETUP(pmc8, SPRN_PMC8);
	614	+
	615	+SYSFS_PMCSETUP(mmcra, SPRN_MMCRA);
	616	+SYSFS_PMCSETUP(mmcr3, SPRN_MMCR3);
	617	+
	618	+static DEVICE_ATTR(mmcra, 0600, show_mmcra, store_mmcra);
	619	+static DEVICE_ATTR(mmcr3, 0600, show_mmcr3, store_mmcr3);
	620	+#endif /* HAS_PPC_PMC56 */
	621	+
	622	+
	623	+
597	624
598	625	#ifdef HAS_PPC_PMC_PA6T
599	626	SYSFS_PMCSETUP(pa6t_pmc0, SPRN_PA6T_PMC0);
..	..	@@ -602,7 +629,9 @@
602	629	SYSFS_PMCSETUP(pa6t_pmc3, SPRN_PA6T_PMC3);
603	630	SYSFS_PMCSETUP(pa6t_pmc4, SPRN_PA6T_PMC4);
604	631	SYSFS_PMCSETUP(pa6t_pmc5, SPRN_PA6T_PMC5);
605		-#ifdef CONFIG_DEBUG_KERNEL
	632	+#endif
	633	+
	634	+#ifdef HAS_PPC_PA6T
606	635	SYSFS_SPRSETUP(hid0, SPRN_HID0);
607	636	SYSFS_SPRSETUP(hid1, SPRN_HID1);
608	637	SYSFS_SPRSETUP(hid4, SPRN_HID4);
..	..	@@ -631,15 +660,14 @@
631	660	SYSFS_SPRSETUP(tsr1, SPRN_PA6T_TSR1);
632	661	SYSFS_SPRSETUP(tsr2, SPRN_PA6T_TSR2);
633	662	SYSFS_SPRSETUP(tsr3, SPRN_PA6T_TSR3);
634		-#endif /* CONFIG_DEBUG_KERNEL */
635		-#endif /* HAS_PPC_PMC_PA6T */
	663	+#endif /* HAS_PPC_PA6T */
636	664
637	665	#ifdef HAS_PPC_PMC_IBM
638	666	static struct device_attribute ibm_common_attrs[] = {
639	667	__ATTR(mmcr0, 0600, show_mmcr0, store_mmcr0),
640	668	__ATTR(mmcr1, 0600, show_mmcr1, store_mmcr1),
641	669	};
642		-#endif /* HAS_PPC_PMC_G4 */
	670	+#endif /* HAS_PPC_PMC_IBM */
643	671
644	672	#ifdef HAS_PPC_PMC_G4
645	673	static struct device_attribute g4_common_attrs[] = {
..	..	@@ -649,6 +677,7 @@
649	677	};
650	678	#endif /* HAS_PPC_PMC_G4 */
651	679
	680	+#ifdef HAS_PPC_PMC_CLASSIC
652	681	static struct device_attribute classic_pmc_attrs[] = {
653	682	__ATTR(pmc1, 0600, show_pmc1, store_pmc1),
654	683	__ATTR(pmc2, 0600, show_pmc2, store_pmc2),
..	..	@@ -656,14 +685,16 @@
656	685	__ATTR(pmc4, 0600, show_pmc4, store_pmc4),
657	686	__ATTR(pmc5, 0600, show_pmc5, store_pmc5),
658	687	__ATTR(pmc6, 0600, show_pmc6, store_pmc6),
659		-#ifdef CONFIG_PPC64
	688	+#ifdef HAS_PPC_PMC56
660	689	__ATTR(pmc7, 0600, show_pmc7, store_pmc7),
661	690	__ATTR(pmc8, 0600, show_pmc8, store_pmc8),
662	691	#endif
663	692	};
	693	+#endif
664	694
665		-#ifdef HAS_PPC_PMC_PA6T
	695	+#if defined(HAS_PPC_PMC_PA6T) \|\| defined(HAS_PPC_PA6T)
666	696	static struct device_attribute pa6t_attrs[] = {
	697	+#ifdef HAS_PPC_PMC_PA6T
667	698	__ATTR(mmcr0, 0600, show_mmcr0, store_mmcr0),
668	699	__ATTR(mmcr1, 0600, show_mmcr1, store_mmcr1),
669	700	__ATTR(pmc0, 0600, show_pa6t_pmc0, store_pa6t_pmc0),
..	..	@@ -672,7 +703,8 @@
672	703	__ATTR(pmc3, 0600, show_pa6t_pmc3, store_pa6t_pmc3),
673	704	__ATTR(pmc4, 0600, show_pa6t_pmc4, store_pa6t_pmc4),
674	705	__ATTR(pmc5, 0600, show_pa6t_pmc5, store_pa6t_pmc5),
675		-#ifdef CONFIG_DEBUG_KERNEL
	706	+#endif
	707	+#ifdef HAS_PPC_PA6T
676	708	__ATTR(hid0, 0600, show_hid0, store_hid0),
677	709	__ATTR(hid1, 0600, show_hid1, store_hid1),
678	710	__ATTR(hid4, 0600, show_hid4, store_hid4),
..	..	@@ -701,10 +733,94 @@
701	733	__ATTR(tsr1, 0600, show_tsr1, store_tsr1),
702	734	__ATTR(tsr2, 0600, show_tsr2, store_tsr2),
703	735	__ATTR(tsr3, 0600, show_tsr3, store_tsr3),
704		-#endif /* CONFIG_DEBUG_KERNEL */
	736	+#endif /* HAS_PPC_PA6T */
705	737	};
706		-#endif /* HAS_PPC_PMC_PA6T */
707		-#endif /* HAS_PPC_PMC_CLASSIC */
	738	+#endif
	739	+
	740	+#ifdef CONFIG_PPC_SVM
	741	+static ssize_t show_svm(struct device dev, struct device_attribute attr, char *buf)
	742	+{
	743	+ return sprintf(buf, "%u\n", is_secure_guest());
	744	+}
	745	+static DEVICE_ATTR(svm, 0444, show_svm, NULL);
	746	+
	747	+static void create_svm_file(void)
	748	+{
	749	+ device_create_file(cpu_subsys.dev_root, &dev_attr_svm);
	750	+}
	751	+#else
	752	+static void create_svm_file(void)
	753	+{
	754	+}
	755	+#endif /* CONFIG_PPC_SVM */
	756	+
	757	+#ifdef CONFIG_PPC_PSERIES
	758	+static void read_idle_purr(void *val)
	759	+{
	760	+ u64 *ret = val;
	761	+
	762	+ *ret = read_this_idle_purr();
	763	+}
	764	+
	765	+static ssize_t idle_purr_show(struct device *dev,
	766	+ struct device_attribute attr, char buf)
	767	+{
	768	+ struct cpu *cpu = container_of(dev, struct cpu, dev);
	769	+ u64 val;
	770	+
	771	+ smp_call_function_single(cpu->dev.id, read_idle_purr, &val, 1);
	772	+ return sprintf(buf, "%llx\n", val);
	773	+}
	774	+static DEVICE_ATTR(idle_purr, 0400, idle_purr_show, NULL);
	775	+
	776	+static void create_idle_purr_file(struct device *s)
	777	+{
	778	+ if (firmware_has_feature(FW_FEATURE_LPAR))
	779	+ device_create_file(s, &dev_attr_idle_purr);
	780	+}
	781	+
	782	+static void remove_idle_purr_file(struct device *s)
	783	+{
	784	+ if (firmware_has_feature(FW_FEATURE_LPAR))
	785	+ device_remove_file(s, &dev_attr_idle_purr);
	786	+}
	787	+
	788	+static void read_idle_spurr(void *val)
	789	+{
	790	+ u64 *ret = val;
	791	+
	792	+ *ret = read_this_idle_spurr();
	793	+}
	794	+
	795	+static ssize_t idle_spurr_show(struct device *dev,
	796	+ struct device_attribute attr, char buf)
	797	+{
	798	+ struct cpu *cpu = container_of(dev, struct cpu, dev);
	799	+ u64 val;
	800	+
	801	+ smp_call_function_single(cpu->dev.id, read_idle_spurr, &val, 1);
	802	+ return sprintf(buf, "%llx\n", val);
	803	+}
	804	+static DEVICE_ATTR(idle_spurr, 0400, idle_spurr_show, NULL);
	805	+
	806	+static void create_idle_spurr_file(struct device *s)
	807	+{
	808	+ if (firmware_has_feature(FW_FEATURE_LPAR))
	809	+ device_create_file(s, &dev_attr_idle_spurr);
	810	+}
	811	+
	812	+static void remove_idle_spurr_file(struct device *s)
	813	+{
	814	+ if (firmware_has_feature(FW_FEATURE_LPAR))
	815	+ device_remove_file(s, &dev_attr_idle_spurr);
	816	+}
	817	+
	818	+#else /* CONFIG_PPC_PSERIES */
	819	+#define create_idle_purr_file(s)
	820	+#define remove_idle_purr_file(s)
	821	+#define create_idle_spurr_file(s)
	822	+#define remove_idle_spurr_file(s)
	823	+#endif /* CONFIG_PPC_PSERIES */
708	824
709	825	static int register_cpu_online(unsigned int cpu)
710	826	{
..	..	@@ -738,14 +854,14 @@
738	854	pmc_attrs = classic_pmc_attrs;
739	855	break;
740	856	#endif /* HAS_PPC_PMC_G4 */
741		-#ifdef HAS_PPC_PMC_PA6T
	857	+#if defined(HAS_PPC_PMC_PA6T) \|\| defined(HAS_PPC_PA6T)
742	858	case PPC_PMC_PA6T:
743	859	/* PA Semi starts counting at PMC0 */
744	860	attrs = pa6t_attrs;
745	861	nattrs = sizeof(pa6t_attrs) / sizeof(struct device_attribute);
746	862	pmc_attrs = NULL;
747	863	break;
748		-#endif /* HAS_PPC_PMC_PA6T */
	864	+#endif
749	865	default:
750	866	attrs = NULL;
751	867	nattrs = 0;
..	..	@@ -760,17 +876,25 @@
760	876	device_create_file(s, &pmc_attrs[i]);
761	877
762	878	#ifdef CONFIG_PPC64
	879	+#ifdef CONFIG_PMU_SYSFS
763	880	if (cpu_has_feature(CPU_FTR_MMCRA))
764	881	device_create_file(s, &dev_attr_mmcra);
	882	+
	883	+ if (cpu_has_feature(CPU_FTR_ARCH_31))
	884	+ device_create_file(s, &dev_attr_mmcr3);
	885	+#endif /* CONFIG_PMU_SYSFS */
765	886
766	887	if (cpu_has_feature(CPU_FTR_PURR)) {
767	888	if (!firmware_has_feature(FW_FEATURE_LPAR))
768	889	add_write_permission_dev_attr(&dev_attr_purr);
769	890	device_create_file(s, &dev_attr_purr);
	891	+ create_idle_purr_file(s);
770	892	}
771	893
772		- if (cpu_has_feature(CPU_FTR_SPURR))
	894	+ if (cpu_has_feature(CPU_FTR_SPURR)) {
773	895	device_create_file(s, &dev_attr_spurr);
	896	+ create_idle_spurr_file(s);
	897	+ }
774	898
775	899	if (cpu_has_feature(CPU_FTR_DSCR))
776	900	device_create_file(s, &dev_attr_dscr);
..	..	@@ -827,14 +951,14 @@
827	951	pmc_attrs = classic_pmc_attrs;
828	952	break;
829	953	#endif /* HAS_PPC_PMC_G4 */
830		-#ifdef HAS_PPC_PMC_PA6T
	954	+#if defined(HAS_PPC_PMC_PA6T) \|\| defined(HAS_PPC_PA6T)
831	955	case PPC_PMC_PA6T:
832	956	/* PA Semi starts counting at PMC0 */
833	957	attrs = pa6t_attrs;
834	958	nattrs = sizeof(pa6t_attrs) / sizeof(struct device_attribute);
835	959	pmc_attrs = NULL;
836	960	break;
837		-#endif /* HAS_PPC_PMC_PA6T */
	961	+#endif
838	962	default:
839	963	attrs = NULL;
840	964	nattrs = 0;
..	..	@@ -849,14 +973,23 @@
849	973	device_remove_file(s, &pmc_attrs[i]);
850	974
851	975	#ifdef CONFIG_PPC64
	976	+#ifdef CONFIG_PMU_SYSFS
852	977	if (cpu_has_feature(CPU_FTR_MMCRA))
853	978	device_remove_file(s, &dev_attr_mmcra);
854	979
855		- if (cpu_has_feature(CPU_FTR_PURR))
856		- device_remove_file(s, &dev_attr_purr);
	980	+ if (cpu_has_feature(CPU_FTR_ARCH_31))
	981	+ device_remove_file(s, &dev_attr_mmcr3);
	982	+#endif /* CONFIG_PMU_SYSFS */
857	983
858		- if (cpu_has_feature(CPU_FTR_SPURR))
	984	+ if (cpu_has_feature(CPU_FTR_PURR)) {
	985	+ device_remove_file(s, &dev_attr_purr);
	986	+ remove_idle_purr_file(s);
	987	+ }
	988	+
	989	+ if (cpu_has_feature(CPU_FTR_SPURR)) {
859	990	device_remove_file(s, &dev_attr_spurr);
	991	+ remove_idle_spurr_file(s);
	992	+ }
860	993
861	994	if (cpu_has_feature(CPU_FTR_DSCR))
862	995	device_remove_file(s, &dev_attr_dscr);
..	..	@@ -1026,6 +1159,7 @@
1026	1159	for_each_possible_cpu(cpu) {
1027	1160	struct cpu *c = &per_cpu(cpu_devices, cpu);
1028	1161
	1162	+#ifdef CONFIG_HOTPLUG_CPU
1029	1163	/*
1030	1164	* For now, we just see if the system supports making
1031	1165	* the RTAS calls for CPU hotplug. But, there may be a
..	..	@@ -1033,8 +1167,9 @@
1033	1167	* CPU. For instance, the boot cpu might never be valid
1034	1168	* for hotplugging.
1035	1169	*/
1036		- if (ppc_md.cpu_die)
	1170	+ if (smp_ops && smp_ops->cpu_offline_self)
1037	1171	c->hotpluggable = 1;
	1172	+#endif
1038	1173
1039	1174	if (cpu_online(cpu) \|\| c->hotpluggable) {
1040	1175	register_cpu(c, cpu);
..	..	@@ -1049,6 +1184,8 @@
1049	1184	sysfs_create_dscr_default();
1050	1185	#endif /* CONFIG_PPC64 */
1051	1186
	1187	+ create_svm_file();
	1188	+
1052	1189	return 0;
1053	1190	}
1054	1191	subsys_initcall(topology_init);