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| 1 | +/* SPDX-License-Identifier: GPL-2.0-or-later */ |
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| 1 | 2 | /* |
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| 2 | 3 | * Copyright 2016,2017 IBM Corporation. |
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| 3 | | - * |
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| 4 | | - * This program is free software; you can redistribute it and/or |
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| 5 | | - * modify it under the terms of the GNU General Public License |
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| 6 | | - * as published by the Free Software Foundation; either version |
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| 7 | | - * 2 of the License, or (at your option) any later version. |
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| 8 | 4 | */ |
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| 9 | 5 | #ifndef _ASM_POWERPC_XIVE_REGS_H |
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| 10 | 6 | #define _ASM_POWERPC_XIVE_REGS_H |
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| .. | .. |
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| 41 | 37 | #define XIVE_ESB_SET_PQ_10 0xe00 /* Load */ |
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| 42 | 38 | #define XIVE_ESB_SET_PQ_11 0xf00 /* Load */ |
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| 43 | 39 | |
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| 40 | +/* |
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| 41 | + * Load-after-store ordering |
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| 42 | + * |
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| 43 | + * Adding this offset to the load address will enforce |
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| 44 | + * load-after-store ordering. This is required to use StoreEOI. |
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| 45 | + */ |
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| 46 | +#define XIVE_ESB_LD_ST_MO 0x40 /* Load-after-store ordering */ |
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| 47 | + |
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| 44 | 48 | #define XIVE_ESB_VAL_P 0x2 |
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| 45 | 49 | #define XIVE_ESB_VAL_Q 0x1 |
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| 50 | +#define XIVE_ESB_INVALID 0xFF |
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| 46 | 51 | |
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| 47 | 52 | /* |
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| 48 | 53 | * Thread Management (aka "TM") registers |
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