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| 3 | 3 | #define _ASM_POWERPC_SYNCH_H |
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| 4 | 4 | #ifdef __KERNEL__ |
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| 5 | 5 | |
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| 6 | +#include <asm/cputable.h> |
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| 6 | 7 | #include <asm/feature-fixups.h> |
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| 7 | | -#include <asm/asm-const.h> |
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| 8 | +#include <asm/ppc-opcode.h> |
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| 8 | 9 | |
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| 9 | 10 | #ifndef __ASSEMBLY__ |
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| 10 | 11 | extern unsigned int __start___lwsync_fixup, __stop___lwsync_fixup; |
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| .. | .. |
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| 20 | 21 | { |
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| 21 | 22 | __asm__ __volatile__ ("isync" : : : "memory"); |
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| 22 | 23 | } |
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| 24 | + |
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| 25 | +static inline void ppc_after_tlbiel_barrier(void) |
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| 26 | +{ |
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| 27 | + asm volatile("ptesync": : :"memory"); |
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| 28 | + /* |
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| 29 | + * POWER9, POWER10 need a cp_abort after tlbiel to ensure the copy is |
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| 30 | + * invalidated correctly. If this is not done, the paste can take data |
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| 31 | + * from the physical address that was translated at copy time. |
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| 32 | + * |
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| 33 | + * POWER9 in practice does not need this, because address spaces with |
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| 34 | + * accelerators mapped will use tlbie (which does invalidate the copy) |
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| 35 | + * to invalidate translations. It's not possible to limit POWER10 this |
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| 36 | + * way due to local copy-paste. |
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| 37 | + */ |
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| 38 | + asm volatile(ASM_FTR_IFSET(PPC_CP_ABORT, "", %0) : : "i" (CPU_FTR_ARCH_31) : "memory"); |
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| 39 | +} |
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| 23 | 40 | #endif /* __ASSEMBLY__ */ |
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| 24 | 41 | |
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| 25 | 42 | #if defined(__powerpc64__) |
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