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2024-01-05 071106ecf68c401173c58808b1cf5f68cc50d390 
 kernel/arch/powerpc/include/asm/reg_booke.h
....@@ -1,13 +1,10 @@
1
+/* SPDX-License-Identifier: GPL-2.0-only */
12 /*
23  * Contains register definitions common to the Book E PowerPC
34  * specification.  Notice that while the IBM-40x series of CPUs
45  * are not true Book E PowerPCs, they borrowed a number of features
56  * before Book E was finalized, and are included here as well.  Unfortunately,
67  * they sometimes used different locations than true Book E CPUs did.
7
- *
8
- * This program is free software; you can redistribute it and/or
9
- * modify it under the terms of the GNU General Public License version 2
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- * as published by the Free Software Foundation.
118  *
129  * Copyright 2009-2010 Freescale Semiconductor, Inc.
1310  */
....@@ -177,7 +174,6 @@
177174 #define SPRN_L1CSR1	0x3F3	/* L1 Cache Control and Status Register 1 */
178175 #define SPRN_MMUCSR0	0x3F4	/* MMU Control and Status Register 0 */
179176 #define SPRN_MMUCFG	0x3F7	/* MMU Configuration Register */
180
-#define SPRN_PIT	0x3DB	/* Programmable Interval Timer */
181177 #define SPRN_BUCSR	0x3F5	/* Branch Unit Control and Status */
182178 #define SPRN_L2CSR0	0x3F9	/* L2 Data Cache Control and Status Register 0 */
183179 #define SPRN_L2CSR1	0x3FA	/* L2 Data Cache Control and Status Register 1 */
....@@ -665,60 +661,6 @@
665661 #define EPC_ELPID_SHIFT	16
666662 #define EPC_EPID	0x00003fff
667663 #define EPC_EPID_SHIFT	0
668
-
669
-/*
670
- * The IBM-403 is an even more odd special case, as it is much
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- * older than the IBM-405 series.  We put these down here incase someone
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- * wishes to support these machines again.
673
- */
674
-#ifdef CONFIG_403GCX
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-/* Special Purpose Registers (SPRNs)*/
676
-#define SPRN_TBHU	0x3CC	/* Time Base High User-mode */
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-#define SPRN_TBLU	0x3CD	/* Time Base Low User-mode */
678
-#define SPRN_CDBCR	0x3D7	/* Cache Debug Control Register */
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-#define SPRN_TBHI	0x3DC	/* Time Base High */
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-#define SPRN_TBLO	0x3DD	/* Time Base Low */
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-#define SPRN_DBCR	0x3F2	/* Debug Control Register */
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-#define SPRN_PBL1	0x3FC	/* Protection Bound Lower 1 */
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-#define SPRN_PBL2	0x3FE	/* Protection Bound Lower 2 */
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-#define SPRN_PBU1	0x3FD	/* Protection Bound Upper 1 */
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-#define SPRN_PBU2	0x3FF	/* Protection Bound Upper 2 */
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-
687
-
688
-/* Bit definitions for the DBCR. */
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-#define DBCR_EDM	DBCR0_EDM
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-#define DBCR_IDM	DBCR0_IDM
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-#define DBCR_RST(x)	(((x) & 0x3) << 28)
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-#define DBCR_RST_NONE	0
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-#define DBCR_RST_CORE	1
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-#define DBCR_RST_CHIP	2
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-#define DBCR_RST_SYSTEM	3
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-#define DBCR_IC		DBCR0_IC	/* Instruction Completion Debug Evnt */
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-#define DBCR_BT		DBCR0_BT	/* Branch Taken Debug Event */
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-#define DBCR_EDE	DBCR0_EDE	/* Exception Debug Event */
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-#define DBCR_TDE	DBCR0_TDE	/* TRAP Debug Event */
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-#define DBCR_FER	0x00F80000	/* First Events Remaining Mask */
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-#define DBCR_FT		0x00040000	/* Freeze Timers on Debug Event */
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-#define DBCR_IA1	0x00020000	/* Instr. Addr. Compare 1 Enable */
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-#define DBCR_IA2	0x00010000	/* Instr. Addr. Compare 2 Enable */
704
-#define DBCR_D1R	0x00008000	/* Data Addr. Compare 1 Read Enable */
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-#define DBCR_D1W	0x00004000	/* Data Addr. Compare 1 Write Enable */
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-#define DBCR_D1S(x)	(((x) & 0x3) << 12)	/* Data Adrr. Compare 1 Size */
707
-#define DAC_BYTE	0
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-#define DAC_HALF	1
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-#define DAC_WORD	2
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-#define DAC_QUAD	3
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-#define DBCR_D2R	0x00000800	/* Data Addr. Compare 2 Read Enable */
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-#define DBCR_D2W	0x00000400	/* Data Addr. Compare 2 Write Enable */
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-#define DBCR_D2S(x)	(((x) & 0x3) << 8)	/* Data Addr. Compare 2 Size */
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-#define DBCR_SBT	0x00000040	/* Second Branch Taken Debug Event */
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-#define DBCR_SED	0x00000020	/* Second Exception Debug Event */
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-#define DBCR_STD	0x00000010	/* Second Trap Debug Event */
717
-#define DBCR_SIA	0x00000008	/* Second IAC Enable */
718
-#define DBCR_SDA	0x00000004	/* Second DAC Enable */
719
-#define DBCR_JOI	0x00000002	/* JTAG Serial Outbound Int. Enable */
720
-#define DBCR_JII	0x00000001	/* JTAG Serial Inbound Int. Enable */
721
-#endif /* 403GCX */
722664 
723665 /* Some 476 specific registers */
724666 #define SPRN_SSPCR		830