| .. | .. |
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| 5 | 5 | #ifndef _ASM_POWERPC_REG_8xx_H |
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| 6 | 6 | #define _ASM_POWERPC_REG_8xx_H |
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| 7 | 7 | |
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| 8 | | -#include <asm/mmu.h> |
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| 9 | | - |
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| 10 | 8 | /* Cache control on the MPC8xx is provided through some additional |
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| 11 | 9 | * special purpose registers. |
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| 12 | 10 | */ |
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| .. | .. |
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| 37 | 35 | #define SPRN_CMPE 152 |
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| 38 | 36 | #define SPRN_CMPF 153 |
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| 39 | 37 | #define SPRN_LCTRL1 156 |
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| 38 | +#define LCTRL1_CTE_GT 0xc0000000 |
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| 39 | +#define LCTRL1_CTF_LT 0x14000000 |
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| 40 | +#define LCTRL1_CRWE_RW 0x00000000 |
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| 41 | +#define LCTRL1_CRWE_RO 0x00040000 |
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| 42 | +#define LCTRL1_CRWE_WO 0x000c0000 |
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| 43 | +#define LCTRL1_CRWF_RW 0x00000000 |
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| 44 | +#define LCTRL1_CRWF_RO 0x00010000 |
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| 45 | +#define LCTRL1_CRWF_WO 0x00030000 |
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| 40 | 46 | #define SPRN_LCTRL2 157 |
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| 47 | +#define LCTRL2_LW0EN 0x80000000 |
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| 48 | +#define LCTRL2_LW0LA_E 0x00000000 |
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| 49 | +#define LCTRL2_LW0LA_F 0x04000000 |
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| 50 | +#define LCTRL2_LW0LA_EandF 0x08000000 |
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| 51 | +#define LCTRL2_LW0LADC 0x02000000 |
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| 52 | +#define LCTRL2_SLW0EN 0x00000002 |
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| 53 | +#ifdef CONFIG_PPC_8xx |
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| 41 | 54 | #define SPRN_ICTRL 158 |
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| 55 | +#endif |
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| 42 | 56 | #define SPRN_BAR 159 |
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| 43 | 57 | |
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| 44 | 58 | /* Commands. Only the first few are available to the instruction cache. |
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