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hc
2024-01-05 071106ecf68c401173c58808b1cf5f68cc50d390 
 kernel/arch/powerpc/include/asm/cputable.h
....@@ -145,12 +145,10 @@
145145 
146146 /* Definitions for features that only exist on 32-bit chips */
147147 #ifdef CONFIG_PPC32
148
-#define CPU_FTR_601			ASM_CONST(0x00001000)
149148 #define CPU_FTR_L2CR			ASM_CONST(0x00002000)
150149 #define CPU_FTR_SPEC7450		ASM_CONST(0x00004000)
151150 #define CPU_FTR_TAU			ASM_CONST(0x00008000)
152151 #define CPU_FTR_CAN_DOZE		ASM_CONST(0x00010000)
153
-#define CPU_FTR_USE_RTC			ASM_CONST(0x00020000)
154152 #define CPU_FTR_L3CR			ASM_CONST(0x00040000)
155153 #define CPU_FTR_L3_DISABLE_NAP		ASM_CONST(0x00080000)
156154 #define CPU_FTR_NAP_DISABLE_L2_PR	ASM_CONST(0x00100000)
....@@ -160,15 +158,14 @@
160158 #define CPU_FTR_NEED_COHERENT		ASM_CONST(0x01000000)
161159 #define CPU_FTR_NO_BTIC			ASM_CONST(0x02000000)
162160 #define CPU_FTR_PPC_LE			ASM_CONST(0x04000000)
163
-#define CPU_FTR_UNIFIED_ID_CACHE	ASM_CONST(0x08000000)
164161 #define CPU_FTR_SPE			ASM_CONST(0x10000000)
165162 #define CPU_FTR_NEED_PAIRED_STWCX	ASM_CONST(0x20000000)
166163 #define CPU_FTR_INDEXED_DCR		ASM_CONST(0x40000000)
167164 
168165 #else	/* CONFIG_PPC32 */
169166 /* Define these to 0 for the sake of tests in common code */
170
-#define CPU_FTR_601			(0)
171167 #define CPU_FTR_PPC_LE			(0)
168
+#define CPU_FTR_SPE			(0)
172169 #endif
173170 
174171 /*
....@@ -202,7 +199,7 @@
202199 #define CPU_FTR_STCX_CHECKS_ADDRESS	LONG_ASM_CONST(0x0000000080000000)
203200 #define CPU_FTR_POPCNTB			LONG_ASM_CONST(0x0000000100000000)
204201 #define CPU_FTR_POPCNTD			LONG_ASM_CONST(0x0000000200000000)
205
-#define CPU_FTR_PKEY			LONG_ASM_CONST(0x0000000400000000)
202
+/* LONG_ASM_CONST(0x0000000400000000) Free */
206203 #define CPU_FTR_VMX_COPY		LONG_ASM_CONST(0x0000000800000000)
207204 #define CPU_FTR_TM			LONG_ASM_CONST(0x0000001000000000)
208205 #define CPU_FTR_CFAR			LONG_ASM_CONST(0x0000002000000000)
....@@ -216,6 +213,9 @@
216213 #define CPU_FTR_P9_TLBIE_STQ_BUG	LONG_ASM_CONST(0x0000400000000000)
217214 #define CPU_FTR_P9_TIDR			LONG_ASM_CONST(0x0000800000000000)
218215 #define CPU_FTR_P9_TLBIE_ERAT_BUG	LONG_ASM_CONST(0x0001000000000000)
216
+#define CPU_FTR_P9_RADIX_PREFETCH_BUG	LONG_ASM_CONST(0x0002000000000000)
217
+#define CPU_FTR_ARCH_31			LONG_ASM_CONST(0x0004000000000000)
218
+#define CPU_FTR_DAWR1			LONG_ASM_CONST(0x0008000000000000)
219219 
220220 #ifndef __ASSEMBLY__
221221 
....@@ -295,10 +295,8 @@
295295 #define CPU_FTR_MAYBE_CAN_NAP	0
296296 #endif
297297 
298
-#define CPU_FTRS_PPC601	(CPU_FTR_COMMON | CPU_FTR_601 | \
299
-	CPU_FTR_COHERENT_ICACHE | CPU_FTR_UNIFIED_ID_CACHE | CPU_FTR_USE_RTC)
300298 #define CPU_FTRS_603	(CPU_FTR_COMMON | CPU_FTR_MAYBE_CAN_DOZE | \
301
-	    CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_PPC_LE)
299
+	    CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_PPC_LE | CPU_FTR_NOEXECUTE)
302300 #define CPU_FTRS_604	(CPU_FTR_COMMON | CPU_FTR_PPC_LE)
303301 #define CPU_FTRS_740_NOTAU	(CPU_FTR_COMMON | \
304302 	    CPU_FTR_MAYBE_CAN_DOZE | CPU_FTR_L2CR | \
....@@ -369,15 +367,15 @@
369367 	    CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_L2CR | CPU_FTR_ALTIVEC_COMP | \
370368 	    CPU_FTR_SPEC7450 | CPU_FTR_NAP_DISABLE_L2_PR | \
371369 	    CPU_FTR_PPC_LE | CPU_FTR_NEED_PAIRED_STWCX)
372
-#define CPU_FTRS_82XX	(CPU_FTR_COMMON | CPU_FTR_MAYBE_CAN_DOZE)
370
+#define CPU_FTRS_82XX	(CPU_FTR_COMMON | CPU_FTR_MAYBE_CAN_DOZE | CPU_FTR_NOEXECUTE)
373371 #define CPU_FTRS_G2_LE	(CPU_FTR_COMMON | CPU_FTR_MAYBE_CAN_DOZE | \
374
-	    CPU_FTR_MAYBE_CAN_NAP)
372
+	    CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_NOEXECUTE)
375373 #define CPU_FTRS_E300	(CPU_FTR_MAYBE_CAN_DOZE | \
376374 	    CPU_FTR_MAYBE_CAN_NAP | \
377
-	    CPU_FTR_COMMON)
375
+	    CPU_FTR_COMMON  | CPU_FTR_NOEXECUTE)
378376 #define CPU_FTRS_E300C2	(CPU_FTR_MAYBE_CAN_DOZE | \
379377 	    CPU_FTR_MAYBE_CAN_NAP | \
380
-	    CPU_FTR_COMMON | CPU_FTR_FPU_UNAVAILABLE)
378
+	    CPU_FTR_COMMON | CPU_FTR_FPU_UNAVAILABLE  | CPU_FTR_NOEXECUTE)
381379 #define CPU_FTRS_CLASSIC32	(CPU_FTR_COMMON)
382380 #define CPU_FTRS_8XX	(CPU_FTR_NOEXECUTE)
383381 #define CPU_FTRS_40X	(CPU_FTR_NODSISRALIGN | CPU_FTR_NOEXECUTE)
....@@ -387,7 +385,7 @@
387385 #define CPU_FTRS_47X	(CPU_FTRS_440x6)
388386 #define CPU_FTRS_E200	(CPU_FTR_SPE_COMP | \
389387 	    CPU_FTR_NODSISRALIGN | CPU_FTR_COHERENT_ICACHE | \
390
-	    CPU_FTR_UNIFIED_ID_CACHE | CPU_FTR_NOEXECUTE | \
388
+	    CPU_FTR_NOEXECUTE | \
391389 	    CPU_FTR_DEBUG_LVL_EXC)
392390 #define CPU_FTRS_E500	(CPU_FTR_MAYBE_CAN_DOZE | \
393391 	    CPU_FTR_SPE_COMP | CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_NODSISRALIGN | \
....@@ -439,7 +437,7 @@
439437 	    CPU_FTR_DSCR | CPU_FTR_SAO  | CPU_FTR_ASYM_SMT | \
440438 	    CPU_FTR_STCX_CHECKS_ADDRESS | CPU_FTR_POPCNTB | CPU_FTR_POPCNTD | \
441439 	    CPU_FTR_CFAR | CPU_FTR_HVMODE | \
442
-	    CPU_FTR_VMX_COPY | CPU_FTR_HAS_PPR | CPU_FTR_DABRX | CPU_FTR_PKEY)
440
+	    CPU_FTR_VMX_COPY | CPU_FTR_HAS_PPR | CPU_FTR_DABRX )
443441 #define CPU_FTRS_POWER8 (CPU_FTR_LWSYNC | \
444442 	    CPU_FTR_PPCAS_ARCH_V2 | CPU_FTR_CTRL | CPU_FTR_ARCH_206 |\
445443 	    CPU_FTR_MMCRA | CPU_FTR_SMT | \
....@@ -449,7 +447,7 @@
449447 	    CPU_FTR_STCX_CHECKS_ADDRESS | CPU_FTR_POPCNTB | CPU_FTR_POPCNTD | \
450448 	    CPU_FTR_CFAR | CPU_FTR_HVMODE | CPU_FTR_VMX_COPY | \
451449 	    CPU_FTR_DBELL | CPU_FTR_HAS_PPR | CPU_FTR_DAWR | \
452
-	    CPU_FTR_ARCH_207S | CPU_FTR_TM_COMP | CPU_FTR_PKEY)
450
+	    CPU_FTR_ARCH_207S | CPU_FTR_TM_COMP )
453451 #define CPU_FTRS_POWER8E (CPU_FTRS_POWER8 | CPU_FTR_PMAO_BUG)
454452 #define CPU_FTRS_POWER9 (CPU_FTR_LWSYNC | \
455453 	    CPU_FTR_PPCAS_ARCH_V2 | CPU_FTR_CTRL | CPU_FTR_ARCH_206 |\
....@@ -460,13 +458,26 @@
460458 	    CPU_FTR_STCX_CHECKS_ADDRESS | CPU_FTR_POPCNTB | CPU_FTR_POPCNTD | \
461459 	    CPU_FTR_CFAR | CPU_FTR_HVMODE | CPU_FTR_VMX_COPY | \
462460 	    CPU_FTR_DBELL | CPU_FTR_HAS_PPR | CPU_FTR_ARCH_207S | \
463
-	    CPU_FTR_TM_COMP | CPU_FTR_ARCH_300 | CPU_FTR_PKEY | \
464
-	    CPU_FTR_P9_TLBIE_STQ_BUG | CPU_FTR_P9_TLBIE_ERAT_BUG | CPU_FTR_P9_TIDR)
465
-#define CPU_FTRS_POWER9_DD2_0 CPU_FTRS_POWER9
466
-#define CPU_FTRS_POWER9_DD2_1 (CPU_FTRS_POWER9 | CPU_FTR_POWER9_DD2_1)
461
+	    CPU_FTR_TM_COMP | CPU_FTR_ARCH_300 | CPU_FTR_P9_TLBIE_STQ_BUG | \
462
+	    CPU_FTR_P9_TLBIE_ERAT_BUG | CPU_FTR_P9_TIDR)
463
+#define CPU_FTRS_POWER9_DD2_0 (CPU_FTRS_POWER9 | CPU_FTR_P9_RADIX_PREFETCH_BUG)
464
+#define CPU_FTRS_POWER9_DD2_1 (CPU_FTRS_POWER9 | \
465
+			       CPU_FTR_P9_RADIX_PREFETCH_BUG | \
466
+			       CPU_FTR_POWER9_DD2_1)
467467 #define CPU_FTRS_POWER9_DD2_2 (CPU_FTRS_POWER9 | CPU_FTR_POWER9_DD2_1 | \
468468 			       CPU_FTR_P9_TM_HV_ASSIST | \
469469 			       CPU_FTR_P9_TM_XER_SO_BUG)
470
+#define CPU_FTRS_POWER10 (CPU_FTR_LWSYNC | \
471
+	    CPU_FTR_PPCAS_ARCH_V2 | CPU_FTR_CTRL | CPU_FTR_ARCH_206 |\
472
+	    CPU_FTR_MMCRA | CPU_FTR_SMT | \
473
+	    CPU_FTR_COHERENT_ICACHE | \
474
+	    CPU_FTR_PURR | CPU_FTR_SPURR | CPU_FTR_REAL_LE | \
475
+	    CPU_FTR_DSCR | CPU_FTR_SAO  | \
476
+	    CPU_FTR_STCX_CHECKS_ADDRESS | CPU_FTR_POPCNTB | CPU_FTR_POPCNTD | \
477
+	    CPU_FTR_CFAR | CPU_FTR_HVMODE | CPU_FTR_VMX_COPY | \
478
+	    CPU_FTR_DBELL | CPU_FTR_HAS_PPR | CPU_FTR_ARCH_207S | \
479
+	    CPU_FTR_ARCH_300 | CPU_FTR_ARCH_31 | \
480
+	    CPU_FTR_DAWR | CPU_FTR_DAWR1)
470481 #define CPU_FTRS_CELL	(CPU_FTR_LWSYNC | \
471482 	    CPU_FTR_PPCAS_ARCH_V2 | CPU_FTR_CTRL | \
472483 	    CPU_FTR_ALTIVEC_COMP | CPU_FTR_MMCRA | CPU_FTR_SMT | \
....@@ -485,21 +496,21 @@
485496 #define CPU_FTRS_POSSIBLE	\
486497 	    (CPU_FTRS_POWER7 | CPU_FTRS_POWER8E | CPU_FTRS_POWER8 | \
487498 	     CPU_FTR_ALTIVEC_COMP | CPU_FTR_VSX_COMP | CPU_FTRS_POWER9 | \
488
-	     CPU_FTRS_POWER9_DD2_1 | CPU_FTRS_POWER9_DD2_2)
499
+	     CPU_FTRS_POWER9_DD2_1 | CPU_FTRS_POWER9_DD2_2 | CPU_FTRS_POWER10)
489500 #else
490501 #define CPU_FTRS_POSSIBLE	\
491502 	    (CPU_FTRS_PPC970 | CPU_FTRS_POWER5 | \
492503 	     CPU_FTRS_POWER6 | CPU_FTRS_POWER7 | CPU_FTRS_POWER8E | \
493504 	     CPU_FTRS_POWER8 | CPU_FTRS_CELL | CPU_FTRS_PA6T | \
494505 	     CPU_FTR_VSX_COMP | CPU_FTR_ALTIVEC_COMP | CPU_FTRS_POWER9 | \
495
-	     CPU_FTRS_POWER9_DD2_1 | CPU_FTRS_POWER9_DD2_2)
506
+	     CPU_FTRS_POWER9_DD2_1 | CPU_FTRS_POWER9_DD2_2 | CPU_FTRS_POWER10)
496507 #endif /* CONFIG_CPU_LITTLE_ENDIAN */
497508 #endif
498509 #else
499510 enum {
500511 	CPU_FTRS_POSSIBLE =
501512 #ifdef CONFIG_PPC_BOOK3S_32
502
-	    CPU_FTRS_PPC601 | CPU_FTRS_603 | CPU_FTRS_604 | CPU_FTRS_740_NOTAU |
513
+	    CPU_FTRS_603 | CPU_FTRS_604 | CPU_FTRS_740_NOTAU |
503514 	    CPU_FTRS_740 | CPU_FTRS_750 | CPU_FTRS_750FX1 |
504515 	    CPU_FTRS_750FX2 | CPU_FTRS_750FX | CPU_FTRS_750GX |
505516 	    CPU_FTRS_7400_NOTAU | CPU_FTRS_7400 | CPU_FTRS_7450_20 |
....@@ -573,7 +584,7 @@
573584 enum {
574585 	CPU_FTRS_ALWAYS =
575586 #ifdef CONFIG_PPC_BOOK3S_32
576
-	    CPU_FTRS_PPC601 & CPU_FTRS_603 & CPU_FTRS_604 & CPU_FTRS_740_NOTAU &
587
+	    CPU_FTRS_603 & CPU_FTRS_604 & CPU_FTRS_740_NOTAU &
577588 	    CPU_FTRS_740 & CPU_FTRS_750 & CPU_FTRS_750FX1 &
578589 	    CPU_FTRS_750FX2 & CPU_FTRS_750FX & CPU_FTRS_750GX &
579590 	    CPU_FTRS_7400_NOTAU & CPU_FTRS_7400 & CPU_FTRS_7450_20 &
....@@ -606,7 +617,12 @@
606617 };
607618 #endif /* __powerpc64__ */
608619 
609
-#define HBP_NUM 1
620
+/*
621
+ * Maximum number of hw breakpoint supported on powerpc. Number of
622
+ * breakpoints supported by actual hw might be less than this, which
623
+ * is decided at run time in nr_wp_slots().
624
+ */
625
+#define HBP_NUM_MAX	2
610626 
611627 #endif /* !__ASSEMBLY__ */
612628