hc
2024-01-05 071106ecf68c401173c58808b1cf5f68cc50d390
kernel/arch/parisc/include/asm/tlbflush.h
....@@ -8,21 +8,6 @@
88 #include <linux/sched.h>
99 #include <asm/mmu_context.h>
1010
11
-
12
-/* This is for the serialisation of PxTLB broadcasts. At least on the
13
- * N class systems, only one PxTLB inter processor broadcast can be
14
- * active at any one time on the Merced bus. This tlb purge
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- * synchronisation is fairly lightweight and harmless so we activate
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- * it on all systems not just the N class.
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-
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- * It is also used to ensure PTE updates are atomic and consistent
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- * with the TLB.
20
- */
21
-extern spinlock_t pa_tlb_lock;
22
-
23
-#define purge_tlb_start(flags) spin_lock_irqsave(&pa_tlb_lock, flags)
24
-#define purge_tlb_end(flags) spin_unlock_irqrestore(&pa_tlb_lock, flags)
25
-
2611 extern void flush_tlb_all(void);
2712 extern void flush_tlb_all_local(void *);
2813
....@@ -79,14 +64,6 @@
7964 static inline void flush_tlb_page(struct vm_area_struct *vma,
8065 unsigned long addr)
8166 {
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- unsigned long flags, sid;
83
-
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- sid = vma->vm_mm->context;
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- purge_tlb_start(flags);
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- mtsp(sid, 1);
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- pdtlb(addr);
88
- if (unlikely(split_tlb))
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- pitlb(addr);
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- purge_tlb_end(flags);
67
+ purge_tlb_entries(vma->vm_mm, addr);
9168 }
9269 #endif