.. | .. |
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3 | 3 | |
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4 | 4 | #include <linux/linkage.h> |
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5 | 5 | #include <linux/init.h> |
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| 6 | +#include <linux/pgtable.h> |
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6 | 7 | #include <asm/ptrace.h> |
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7 | 8 | #include <asm/asm-offsets.h> |
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8 | 9 | #include <asm/page.h> |
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9 | | -#include <asm/pgtable.h> |
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10 | | -#include <asm/sizes.h> |
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| 10 | +#include <linux/sizes.h> |
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11 | 11 | #include <asm/thread_info.h> |
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12 | 12 | |
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13 | 13 | #ifdef CONFIG_CPU_BIG_ENDIAN |
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.. | .. |
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123 | 123 | andi $r0, $r0, MMU_CFG_mskTBS |
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124 | 124 | srli $r6, $r6, MMU_CFG_offTBW |
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125 | 125 | srli $r0, $r0, MMU_CFG_offTBS |
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126 | | - /* |
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127 | | - * we just map the kernel to the maximum way - 1 of tlb |
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128 | | - * reserver one way for UART VA mapping |
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129 | | - * it will cause page fault if UART mapping cover the kernel mapping |
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130 | | - * |
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131 | | - * direct mapping is not supported now. |
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132 | | - */ |
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133 | | - li $r2, 't' |
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134 | | - beqz $r6, __error ! MMU_CFG.TBW = 0 is direct mappin |
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| 126 | + addi $r6, $r6, #0x1 ! MMU_CFG.TBW value -> meaning |
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135 | 127 | addi $r0, $r0, #0x2 ! MMU_CFG.TBS value -> meaning |
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136 | 128 | sll $r0, $r6, $r0 ! entries = k-way * n-set |
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137 | 129 | mul $r6, $r0, $r5 ! max size = entries * page size |
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138 | 130 | /* check kernel image size */ |
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139 | 131 | la $r3, (_end - PAGE_OFFSET) |
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140 | | - li $r2, 's' |
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141 | 132 | bgt $r3, $r6, __error |
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142 | 133 | |
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143 | 134 | li $r2, #(PHYS_OFFSET + TLB_DATA_kernel_text_attr) |
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.. | .. |
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160 | 151 | #endif |
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161 | 152 | mtsr $r3, $TLB_MISC |
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162 | 153 | |
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163 | | - mfsr $r0, $MISC_CTL ! Enable BTB and RTP and shadow sp |
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| 154 | + mfsr $r0, $MISC_CTL ! Enable BTB, RTP, shadow sp, and HW_PRE |
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164 | 155 | ori $r0, $r0, #MISC_init |
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165 | 156 | mtsr $r0, $MISC_CTL |
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166 | 157 | |
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