hc
2024-01-05 071106ecf68c401173c58808b1cf5f68cc50d390
kernel/arch/nds32/kernel/head.S
....@@ -3,11 +3,11 @@
33
44 #include <linux/linkage.h>
55 #include <linux/init.h>
6
+#include <linux/pgtable.h>
67 #include <asm/ptrace.h>
78 #include <asm/asm-offsets.h>
89 #include <asm/page.h>
9
-#include <asm/pgtable.h>
10
-#include <asm/sizes.h>
10
+#include <linux/sizes.h>
1111 #include <asm/thread_info.h>
1212
1313 #ifdef CONFIG_CPU_BIG_ENDIAN
....@@ -123,21 +123,12 @@
123123 andi $r0, $r0, MMU_CFG_mskTBS
124124 srli $r6, $r6, MMU_CFG_offTBW
125125 srli $r0, $r0, MMU_CFG_offTBS
126
- /*
127
- * we just map the kernel to the maximum way - 1 of tlb
128
- * reserver one way for UART VA mapping
129
- * it will cause page fault if UART mapping cover the kernel mapping
130
- *
131
- * direct mapping is not supported now.
132
- */
133
- li $r2, 't'
134
- beqz $r6, __error ! MMU_CFG.TBW = 0 is direct mappin
126
+ addi $r6, $r6, #0x1 ! MMU_CFG.TBW value -> meaning
135127 addi $r0, $r0, #0x2 ! MMU_CFG.TBS value -> meaning
136128 sll $r0, $r6, $r0 ! entries = k-way * n-set
137129 mul $r6, $r0, $r5 ! max size = entries * page size
138130 /* check kernel image size */
139131 la $r3, (_end - PAGE_OFFSET)
140
- li $r2, 's'
141132 bgt $r3, $r6, __error
142133
143134 li $r2, #(PHYS_OFFSET + TLB_DATA_kernel_text_attr)
....@@ -160,7 +151,7 @@
160151 #endif
161152 mtsr $r3, $TLB_MISC
162153
163
- mfsr $r0, $MISC_CTL ! Enable BTB and RTP and shadow sp
154
+ mfsr $r0, $MISC_CTL ! Enable BTB, RTP, shadow sp, and HW_PRE
164155 ori $r0, $r0, #MISC_init
165156 mtsr $r0, $MISC_CTL
166157