change wifi driver to cypress

hc

2024-01-05 071106ecf68c401173c58808b1cf5f68cc50d390

 kernel/arch/nds32/include/asm/bitfield.h
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@@ -1,4 +1,4 @@
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-// SPDX-License-Identifier: GPL-2.0
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+/* SPDX-License-Identifier: GPL-2.0 */
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 // Copyright (C) 2005-2017 Andes Technology Corporation
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 #ifndef __NDS32_BITFIELD_H__
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@@ -250,6 +250,11 @@
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 #define ITYPE_mskSTYPE		( 0xF  << ITYPE_offSTYPE )
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 #define ITYPE_mskCPID		( 0x3  << ITYPE_offCPID )
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+
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+/* Additional definitions of ITYPE register for FPU */
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+#define FPU_DISABLE_EXCEPTION	(0x1  << ITYPE_offSTYPE)
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+#define FPU_EXCEPTION		(0x2  << ITYPE_offSTYPE)
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+#define FPU_CPID		0	/* FPU Co-Processor ID is 0 */
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 #define NDS32_VECTOR_mskNONEXCEPTION	0x78
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 #define NDS32_VECTOR_offEXCEPTION	8
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@@ -735,14 +740,20 @@
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 #define N13MISC_CTL_offRTP	1	/* Disable Return Target Predictor */
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 #define N13MISC_CTL_offPTEPF	2	/* Disable HPTWK L2 PTE pefetch */
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 #define N13MISC_CTL_offSP_SHADOW_EN	4	/* Enable shadow stack pointers */
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+#define MISC_CTL_offHWPRE      11      /* Enable HardWare PREFETCH */
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 /* bit 6, 9:31 reserved */
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 #define N13MISC_CTL_makBTB	( 0x1  << N13MISC_CTL_offBTB )
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 #define N13MISC_CTL_makRTP	( 0x1  << N13MISC_CTL_offRTP )
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 #define N13MISC_CTL_makPTEPF	( 0x1  << N13MISC_CTL_offPTEPF )
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 #define N13MISC_CTL_makSP_SHADOW_EN	( 0x1  << N13MISC_CTL_offSP_SHADOW_EN )
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+#define MISC_CTL_makHWPRE_EN     ( 0x1  << MISC_CTL_offHWPRE )
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+#ifdef CONFIG_HW_PRE
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+#define MISC_init	(N13MISC_CTL_makBTB|N13MISC_CTL_makRTP|N13MISC_CTL_makSP_SHADOW_EN|MISC_CTL_makHWPRE_EN)
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+#else
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 #define MISC_init	(N13MISC_CTL_makBTB|N13MISC_CTL_makRTP|N13MISC_CTL_makSP_SHADOW_EN)
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+#endif
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 /******************************************************************************
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  * PRUSR_ACC_CTL (Privileged Resource User Access Control Registers)
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@@ -926,6 +937,7 @@
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 #define FPCSR_mskDNIT           ( 0x1  << FPCSR_offDNIT )
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 #define FPCSR_mskRIT		( 0x1  << FPCSR_offRIT )
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 #define FPCSR_mskALL		(FPCSR_mskIVO | FPCSR_mskDBZ | FPCSR_mskOVF | FPCSR_mskUDF | FPCSR_mskIEX)
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+#define FPCSR_mskALLE_NO_UDF_IEXE (FPCSR_mskIVOE | FPCSR_mskDBZE | FPCSR_mskOVFE)
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 #define FPCSR_mskALLE		(FPCSR_mskIVOE | FPCSR_mskDBZE | FPCSR_mskOVFE | FPCSR_mskUDFE | FPCSR_mskIEXE)
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 #define FPCSR_mskALLT           (FPCSR_mskIVOT | FPCSR_mskDBZT | FPCSR_mskOVFT | FPCSR_mskUDFT | FPCSR_mskIEXT |FPCSR_mskDNIT | FPCSR_mskRIT)
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..
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@@ -946,6 +958,15 @@
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 #define FPCFG_mskIMVER		( 0x1F  << FPCFG_offIMVER )
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 #define FPCFG_mskAVER		( 0x1F  << FPCFG_offAVER )
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+/* 8 Single precision or 4 double precision registers are available */
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+#define SP8_DP4_reg		0
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+/* 16 Single precision or 8 double precision registers are available */
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+#define SP16_DP8_reg		1
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+/* 32 Single precision or 16 double precision registers are available */
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+#define SP32_DP16_reg		2
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+/* 32 Single precision or 32 double precision registers are available */
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+#define SP32_DP32_reg		3
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+
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 /******************************************************************************
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  * fucpr: FUCOP_CTL (FPU and Coprocessor Enable Control Register)
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  *****************************************************************************/