~hc/RK356X_SDK_RELEASE.git

..	..	@@ -3,169 +3,161 @@
3	3	* Copyright (C) 1999, 2000 Ralf Baechle
4	4	* Copyright (C) 1999, 2000 Silicon Graphics, Inc.
5	5	*/
6		-#ifndef _IOC3_H
7		-#define _IOC3_H
	6	+#ifndef MIPS_SN_IOC3_H
	7	+#define MIPS_SN_IOC3_H
8	8
9	9	#include <linux/types.h>
10	10
11		-/* SUPERIO uart register map */
12		-typedef volatile struct ioc3_uartregs {
13		- union {
14		- volatile u8 rbr; /* read only, DLAB == 0 */
15		- volatile u8 thr; /* write only, DLAB == 0 */
16		- volatile u8 dll; /* DLAB == 1 */
17		- } u1;
18		- union {
19		- volatile u8 ier; /* DLAB == 0 */
20		- volatile u8 dlm; /* DLAB == 1 */
21		- } u2;
22		- union {
23		- volatile u8 iir; /* read only */
24		- volatile u8 fcr; /* write only */
25		- } u3;
26		- volatile u8 iu_lcr;
27		- volatile u8 iu_mcr;
28		- volatile u8 iu_lsr;
29		- volatile u8 iu_msr;
30		- volatile u8 iu_scr;
31		-} ioc3_uregs_t;
	11	+/* serial port register map */
	12	+struct ioc3_serialregs {
	13	+ u32 sscr;
	14	+ u32 stpir;
	15	+ u32 stcir;
	16	+ u32 srpir;
	17	+ u32 srcir;
	18	+ u32 srtr;
	19	+ u32 shadow;
	20	+};
32	21
33		-#define iu_rbr u1.rbr
34		-#define iu_thr u1.thr
35		-#define iu_dll u1.dll
36		-#define iu_ier u2.ier
37		-#define iu_dlm u2.dlm
38		-#define iu_iir u3.iir
39		-#define iu_fcr u3.fcr
	22	+/* SUPERIO uart register map */
	23	+struct ioc3_uartregs {
	24	+ u8 iu_lcr;
	25	+ union {
	26	+ u8 iu_iir; /* read only */
	27	+ u8 iu_fcr; /* write only */
	28	+ };
	29	+ union {
	30	+ u8 iu_ier; /* DLAB == 0 */
	31	+ u8 iu_dlm; /* DLAB == 1 */
	32	+ };
	33	+ union {
	34	+ u8 iu_rbr; /* read only, DLAB == 0 */
	35	+ u8 iu_thr; /* write only, DLAB == 0 */
	36	+ u8 iu_dll; /* DLAB == 1 */
	37	+ };
	38	+ u8 iu_scr;
	39	+ u8 iu_msr;
	40	+ u8 iu_lsr;
	41	+ u8 iu_mcr;
	42	+};
40	43
41	44	struct ioc3_sioregs {
42		- volatile u8 fill[0x141]; /* starts at 0x141 */
	45	+ u8 fill[0x141]; /* starts at 0x141 */
43	46
44		- volatile u8 uartc;
45		- volatile u8 kbdcg;
	47	+ u8 kbdcg;
	48	+ u8 uartc;
46	49
47		- volatile u8 fill0[0x150 - 0x142 - 1];
	50	+ u8 fill0[0x151 - 0x142 - 1];
48	51
49		- volatile u8 pp_data;
50		- volatile u8 pp_dsr;
51		- volatile u8 pp_dcr;
	52	+ u8 pp_dcr;
	53	+ u8 pp_dsr;
	54	+ u8 pp_data;
52	55
53		- volatile u8 fill1[0x158 - 0x152 - 1];
	56	+ u8 fill1[0x159 - 0x153 - 1];
54	57
55		- volatile u8 pp_fifa;
56		- volatile u8 pp_cfgb;
57		- volatile u8 pp_ecr;
	58	+ u8 pp_ecr;
	59	+ u8 pp_cfgb;
	60	+ u8 pp_fifa;
58	61
59		- volatile u8 fill2[0x168 - 0x15a - 1];
	62	+ u8 fill2[0x16a - 0x15b - 1];
60	63
61		- volatile u8 rtcad;
62		- volatile u8 rtcdat;
	64	+ u8 rtcdat;
	65	+ u8 rtcad;
63	66
64		- volatile u8 fill3[0x170 - 0x169 - 1];
	67	+ u8 fill3[0x170 - 0x16b - 1];
65	68
66	69	struct ioc3_uartregs uartb; /* 0x20170 */
67	70	struct ioc3_uartregs uarta; /* 0x20178 */
68	71	};
69	72
	73	+struct ioc3_ethregs {
	74	+ u32 emcr; /* 0x000f0 */
	75	+ u32 eisr; /* 0x000f4 */
	76	+ u32 eier; /* 0x000f8 */
	77	+ u32 ercsr; /* 0x000fc */
	78	+ u32 erbr_h; /* 0x00100 */
	79	+ u32 erbr_l; /* 0x00104 */
	80	+ u32 erbar; /* 0x00108 */
	81	+ u32 ercir; /* 0x0010c */
	82	+ u32 erpir; /* 0x00110 */
	83	+ u32 ertr; /* 0x00114 */
	84	+ u32 etcsr; /* 0x00118 */
	85	+ u32 ersr; /* 0x0011c */
	86	+ u32 etcdc; /* 0x00120 */
	87	+ u32 ebir; /* 0x00124 */
	88	+ u32 etbr_h; /* 0x00128 */
	89	+ u32 etbr_l; /* 0x0012c */
	90	+ u32 etcir; /* 0x00130 */
	91	+ u32 etpir; /* 0x00134 */
	92	+ u32 emar_h; /* 0x00138 */
	93	+ u32 emar_l; /* 0x0013c */
	94	+ u32 ehar_h; /* 0x00140 */
	95	+ u32 ehar_l; /* 0x00144 */
	96	+ u32 micr; /* 0x00148 */
	97	+ u32 midr_r; /* 0x0014c */
	98	+ u32 midr_w; /* 0x00150 */
	99	+};
	100	+
	101	+struct ioc3_serioregs {
	102	+ u32 km_csr; /* 0x0009c */
	103	+ u32 k_rd; /* 0x000a0 */
	104	+ u32 m_rd; /* 0x000a4 */
	105	+ u32 k_wd; /* 0x000a8 */
	106	+ u32 m_wd; /* 0x000ac */
	107	+};
	108	+
70	109	/* Register layout of IOC3 in configuration space. */
71	110	struct ioc3 {
72		- volatile u32 pad0[7]; /* 0x00000 */
73		- volatile u32 sio_ir; /* 0x0001c */
74		- volatile u32 sio_ies; /* 0x00020 */
75		- volatile u32 sio_iec; /* 0x00024 */
76		- volatile u32 sio_cr; /* 0x00028 */
77		- volatile u32 int_out; /* 0x0002c */
78		- volatile u32 mcr; /* 0x00030 */
	111	+ /* PCI Config Space registers */
	112	+ u32 pci_id; /* 0x00000 */
	113	+ u32 pci_scr; /* 0x00004 */
	114	+ u32 pci_rev; /* 0x00008 */
	115	+ u32 pci_lat; /* 0x0000c */
	116	+ u32 pci_addr; /* 0x00010 */
	117	+ u32 pci_err_addr_l; /* 0x00014 */
	118	+ u32 pci_err_addr_h; /* 0x00018 */
	119	+
	120	+ u32 sio_ir; /* 0x0001c */
	121	+ u32 sio_ies; /* 0x00020 */
	122	+ u32 sio_iec; /* 0x00024 */
	123	+ u32 sio_cr; /* 0x00028 */
	124	+ u32 int_out; /* 0x0002c */
	125	+ u32 mcr; /* 0x00030 */
79	126
80	127	/* General Purpose I/O registers */
81		- volatile u32 gpcr_s; /* 0x00034 */
82		- volatile u32 gpcr_c; /* 0x00038 */
83		- volatile u32 gpdr; /* 0x0003c */
84		- volatile u32 gppr_0; /* 0x00040 */
85		- volatile u32 gppr_1; /* 0x00044 */
86		- volatile u32 gppr_2; /* 0x00048 */
87		- volatile u32 gppr_3; /* 0x0004c */
88		- volatile u32 gppr_4; /* 0x00050 */
89		- volatile u32 gppr_5; /* 0x00054 */
90		- volatile u32 gppr_6; /* 0x00058 */
91		- volatile u32 gppr_7; /* 0x0005c */
92		- volatile u32 gppr_8; /* 0x00060 */
93		- volatile u32 gppr_9; /* 0x00064 */
94		- volatile u32 gppr_10; /* 0x00068 */
95		- volatile u32 gppr_11; /* 0x0006c */
96		- volatile u32 gppr_12; /* 0x00070 */
97		- volatile u32 gppr_13; /* 0x00074 */
98		- volatile u32 gppr_14; /* 0x00078 */
99		- volatile u32 gppr_15; /* 0x0007c */
	128	+ u32 gpcr_s; /* 0x00034 */
	129	+ u32 gpcr_c; /* 0x00038 */
	130	+ u32 gpdr; /* 0x0003c */
	131	+ u32 gppr[16]; /* 0x00040 */
100	132
101	133	/* Parallel Port Registers */
102		- volatile u32 ppbr_h_a; /* 0x00080 */
103		- volatile u32 ppbr_l_a; /* 0x00084 */
104		- volatile u32 ppcr_a; /* 0x00088 */
105		- volatile u32 ppcr; /* 0x0008c */
106		- volatile u32 ppbr_h_b; /* 0x00090 */
107		- volatile u32 ppbr_l_b; /* 0x00094 */
108		- volatile u32 ppcr_b; /* 0x00098 */
	134	+ u32 ppbr_h_a; /* 0x00080 */
	135	+ u32 ppbr_l_a; /* 0x00084 */
	136	+ u32 ppcr_a; /* 0x00088 */
	137	+ u32 ppcr; /* 0x0008c */
	138	+ u32 ppbr_h_b; /* 0x00090 */
	139	+ u32 ppbr_l_b; /* 0x00094 */
	140	+ u32 ppcr_b; /* 0x00098 */
109	141
110	142	/* Keyboard and Mouse Registers */
111		- volatile u32 km_csr; /* 0x0009c */
112		- volatile u32 k_rd; /* 0x000a0 */
113		- volatile u32 m_rd; /* 0x000a4 */
114		- volatile u32 k_wd; /* 0x000a8 */
115		- volatile u32 m_wd; /* 0x000ac */
	143	+ struct ioc3_serioregs serio;
116	144
117	145	/* Serial Port Registers */
118		- volatile u32 sbbr_h; /* 0x000b0 */
119		- volatile u32 sbbr_l; /* 0x000b4 */
120		- volatile u32 sscr_a; /* 0x000b8 */
121		- volatile u32 stpir_a; /* 0x000bc */
122		- volatile u32 stcir_a; /* 0x000c0 */
123		- volatile u32 srpir_a; /* 0x000c4 */
124		- volatile u32 srcir_a; /* 0x000c8 */
125		- volatile u32 srtr_a; /* 0x000cc */
126		- volatile u32 shadow_a; /* 0x000d0 */
127		- volatile u32 sscr_b; /* 0x000d4 */
128		- volatile u32 stpir_b; /* 0x000d8 */
129		- volatile u32 stcir_b; /* 0x000dc */
130		- volatile u32 srpir_b; /* 0x000e0 */
131		- volatile u32 srcir_b; /* 0x000e4 */
132		- volatile u32 srtr_b; /* 0x000e8 */
133		- volatile u32 shadow_b; /* 0x000ec */
	146	+ u32 sbbr_h; /* 0x000b0 */
	147	+ u32 sbbr_l; /* 0x000b4 */
	148	+ struct ioc3_serialregs port_a;
	149	+ struct ioc3_serialregs port_b;
134	150
135		- /* Ethernet Registers */
136		- volatile u32 emcr; /* 0x000f0 */
137		- volatile u32 eisr; /* 0x000f4 */
138		- volatile u32 eier; /* 0x000f8 */
139		- volatile u32 ercsr; /* 0x000fc */
140		- volatile u32 erbr_h; /* 0x00100 */
141		- volatile u32 erbr_l; /* 0x00104 */
142		- volatile u32 erbar; /* 0x00108 */
143		- volatile u32 ercir; /* 0x0010c */
144		- volatile u32 erpir; /* 0x00110 */
145		- volatile u32 ertr; /* 0x00114 */
146		- volatile u32 etcsr; /* 0x00118 */
147		- volatile u32 ersr; /* 0x0011c */
148		- volatile u32 etcdc; /* 0x00120 */
149		- volatile u32 ebir; /* 0x00124 */
150		- volatile u32 etbr_h; /* 0x00128 */
151		- volatile u32 etbr_l; /* 0x0012c */
152		- volatile u32 etcir; /* 0x00130 */
153		- volatile u32 etpir; /* 0x00134 */
154		- volatile u32 emar_h; /* 0x00138 */
155		- volatile u32 emar_l; /* 0x0013c */
156		- volatile u32 ehar_h; /* 0x00140 */
157		- volatile u32 ehar_l; /* 0x00144 */
158		- volatile u32 micr; /* 0x00148 */
159		- volatile u32 midr_r; /* 0x0014c */
160		- volatile u32 midr_w; /* 0x00150 */
161		- volatile u32 pad1[(0x20000 - 0x00154) / 4];
	151	+ /* Ethernet Registers */
	152	+ struct ioc3_ethregs eth;
	153	+ u32 pad1[(0x20000 - 0x00154) / 4];
162	154
163	155	/* SuperIO Registers XXX */
164	156	struct ioc3_sioregs sregs; /* 0x20000 */
165		- volatile u32 pad2[(0x40000 - 0x20180) / 4];
	157	+ u32 pad2[(0x40000 - 0x20180) / 4];
166	158
167	159	/* SSRAM Diagnostic Access */
168		- volatile u32 ssram[(0x80000 - 0x40000) / 4];
	160	+ u32 ssram[(0x80000 - 0x40000) / 4];
169	161
170	162	/* Bytebus device offsets
171	163	0x80000 - Access to the generic devices selected with DEV0
..	..	@@ -177,6 +169,20 @@
177	169	0xE0000 - Access to the generic devices selected with DEV3
178	170	0xFFFFF bytebus DEV_SEL_3 */
179	171	};
	172	+
	173	+
	174	+#define PCI_LAT 0xc /* Latency Timer */
	175	+#define PCI_SCR_DROP_MODE_EN 0x00008000 /* drop pios on parity err */
	176	+#define UARTA_BASE 0x178
	177	+#define UARTB_BASE 0x170
	178	+
	179	+/*
	180	+ * Bytebus device space
	181	+ */
	182	+#define IOC3_BYTEBUS_DEV0 0x80000L
	183	+#define IOC3_BYTEBUS_DEV1 0xa0000L
	184	+#define IOC3_BYTEBUS_DEV2 0xc0000L
	185	+#define IOC3_BYTEBUS_DEV3 0xe0000L
180	186
181	187	/*
182	188	* Ethernet RX Buffer
..	..	@@ -233,28 +239,20 @@
233	239	#define ETXD_B2CNT_MASK 0x7ff00000
234	240	#define ETXD_B2CNT_SHIFT 20
235	241
236		-/*
237		- * Bytebus device space
238		- */
239		-#define IOC3_BYTEBUS_DEV0 0x80000L
240		-#define IOC3_BYTEBUS_DEV1 0xa0000L
241		-#define IOC3_BYTEBUS_DEV2 0xc0000L
242		-#define IOC3_BYTEBUS_DEV3 0xe0000L
243		-
244	242	/* ------------------------------------------------------------------------- */
245	243
246	244	/* Superio Registers (PIO Access) */
247	245	#define IOC3_SIO_BASE 0x20000
248	246	#define IOC3_SIO_UARTC (IOC3_SIO_BASE+0x141) /* UART Config */
249	247	#define IOC3_SIO_KBDCG (IOC3_SIO_BASE+0x142) /* KBD Config */
250		-#define IOC3_SIO_PP_BASE (IOC3_SIO_BASE+PP_BASE) /* Parallel Port */
	248	+#define IOC3_SIO_PP_BASE (IOC3_SIO_BASE+PP_BASE) /* Parallel Port */
251	249	#define IOC3_SIO_RTC_BASE (IOC3_SIO_BASE+0x168) /* Real Time Clock */
252	250	#define IOC3_SIO_UB_BASE (IOC3_SIO_BASE+UARTB_BASE) /* UART B */
253	251	#define IOC3_SIO_UA_BASE (IOC3_SIO_BASE+UARTA_BASE) /* UART A */
254	252
255	253	/* SSRAM Diagnostic Access */
256	254	#define IOC3_SSRAM IOC3_RAM_OFF /* base of SSRAM diagnostic access */
257		-#define IOC3_SSRAM_LEN 0x40000 /* 256kb (address space size, may not be fully populated) */
	255	+#define IOC3_SSRAM_LEN 0x40000 /* 256kb (addrspc sz, may not be populated) */
258	256	#define IOC3_SSRAM_DM 0x0000ffff /* data mask */
259	257	#define IOC3_SSRAM_PM 0x00010000 /* parity mask */
260	258
..	..	@@ -294,10 +292,10 @@
294	292	SIO_IR to assert */
295	293	#define KM_CSR_M_TO_EN 0x00080000 /* KM_CSR_M_TO + KM_CSR_M_TO_EN = cause
296	294	SIO_IR to assert */
297		-#define KM_CSR_K_CLAMP_ONE 0x00100000 /* Pull K_CLK low after rec. one char */
298		-#define KM_CSR_M_CLAMP_ONE 0x00200000 /* Pull M_CLK low after rec. one char */
299		-#define KM_CSR_K_CLAMP_THREE 0x00400000 /* Pull K_CLK low after rec. three chars */
300		-#define KM_CSR_M_CLAMP_THREE 0x00800000 /* Pull M_CLK low after rec. three char */
	295	+#define KM_CSR_K_CLAMP_1 0x00100000 /* Pull K_CLK low aft recv 1 char */
	296	+#define KM_CSR_M_CLAMP_1 0x00200000 /* Pull M_CLK low aft recv 1 char */
	297	+#define KM_CSR_K_CLAMP_3 0x00400000 /* Pull K_CLK low aft recv 3 chars */
	298	+#define KM_CSR_M_CLAMP_3 0x00800000 /* Pull M_CLK low aft recv 3 chars */
301	299
302	300	/* bitmasks for IOC3_K_RD and IOC3_M_RD */
303	301	#define KM_RD_DATA_2 0x000000ff /* 3rd char recvd since last read */
..	..	@@ -440,10 +438,6 @@
440	438	SIO_IR_PP_INTB \| SIO_IR_PP_MEMERR)
441	439	#define SIO_IR_RT (SIO_IR_RT_INT \| SIO_IR_GEN_INT1)
442	440
443		-/* macro to load pending interrupts */
444		-#define IOC3_PENDING_INTRS(mem) (PCI_INW(&((mem)->sio_ir)) & \
445		- PCI_INW(&((mem)->sio_ies_ro)))
446		-
447	441	/* bitmasks for SIO_CR */
448	442	#define SIO_CR_SIO_RESET 0x00000001 /* reset the SIO */
449	443	#define SIO_CR_SER_A_BASE 0x000000fe /* DMA poll addr port A */
..	..	@@ -500,10 +494,11 @@
500	494	#define GPCR_UARTB_MODESEL 0x40 /* pin is output to port B mode sel */
501	495	#define GPCR_UARTA_MODESEL 0x80 /* pin is output to port A mode sel */
502	496
503		-#define GPPR_PHY_RESET_PIN 5 /* GIO pin controlling phy reset */
504		-#define GPPR_UARTB_MODESEL_PIN 6 /* GIO pin controlling uart b mode select */
505		-#define GPPR_UARTA_MODESEL_PIN 7 /* GIO pin controlling uart a mode select */
	497	+#define GPPR_PHY_RESET_PIN 5 /* GIO pin cntrlling phy reset */
	498	+#define GPPR_UARTB_MODESEL_PIN 6 /* GIO pin cntrlling uart b mode sel */
	499	+#define GPPR_UARTA_MODESEL_PIN 7 /* GIO pin cntrlling uart a mode sel */
506	500
	501	+/* ethernet */
507	502	#define EMCR_DUPLEX 0x00000001
508	503	#define EMCR_PROMISC 0x00000002
509	504	#define EMCR_PADEN 0x00000004
..	..	@@ -595,70 +590,17 @@
595	590
596	591	#define MIDR_DATA_MASK 0x0000ffff
597	592
598		-#define ERXBUF_IPCKSUM_MASK 0x0000ffff
599		-#define ERXBUF_BYTECNT_MASK 0x07ff0000
600		-#define ERXBUF_BYTECNT_SHIFT 16
601		-#define ERXBUF_V 0x80000000
	593	+/* subsystem IDs supplied by card detection in pci-xtalk-bridge */
	594	+#define IOC3_SUBSYS_IP27_BASEIO6G 0xc300
	595	+#define IOC3_SUBSYS_IP27_MIO 0xc301
	596	+#define IOC3_SUBSYS_IP27_BASEIO 0xc302
	597	+#define IOC3_SUBSYS_IP29_SYSBOARD 0xc303
	598	+#define IOC3_SUBSYS_IP30_SYSBOARD 0xc304
	599	+#define IOC3_SUBSYS_MENET 0xc305
	600	+#define IOC3_SUBSYS_MENET4 0xc306
	601	+#define IOC3_SUBSYS_IO7 0xc307
	602	+#define IOC3_SUBSYS_IO8 0xc308
	603	+#define IOC3_SUBSYS_IO9 0xc309
	604	+#define IOC3_SUBSYS_IP34_SYSBOARD 0xc30A
602	605
603		-#define ERXBUF_CRCERR 0x00000001 /* aka RSV15 */
604		-#define ERXBUF_FRAMERR 0x00000002 /* aka RSV14 */
605		-#define ERXBUF_CODERR 0x00000004 /* aka RSV13 */
606		-#define ERXBUF_INVPREAMB 0x00000008 /* aka RSV18 */
607		-#define ERXBUF_LOLEN 0x00007000 /* aka RSV2_0 */
608		-#define ERXBUF_HILEN 0x03ff0000 /* aka RSV12_3 */
609		-#define ERXBUF_MULTICAST 0x04000000 /* aka RSV16 */
610		-#define ERXBUF_BROADCAST 0x08000000 /* aka RSV17 */
611		-#define ERXBUF_LONGEVENT 0x10000000 /* aka RSV19 */
612		-#define ERXBUF_BADPKT 0x20000000 /* aka RSV20 */
613		-#define ERXBUF_GOODPKT 0x40000000 /* aka RSV21 */
614		-#define ERXBUF_CARRIER 0x80000000 /* aka RSV22 */
615		-
616		-#define ETXD_BYTECNT_MASK 0x000007ff /* total byte count */
617		-#define ETXD_INTWHENDONE 0x00001000 /* intr when done */
618		-#define ETXD_D0V 0x00010000 /* data 0 valid */
619		-#define ETXD_B1V 0x00020000 /* buf 1 valid */
620		-#define ETXD_B2V 0x00040000 /* buf 2 valid */
621		-#define ETXD_DOCHECKSUM 0x00080000 /* insert ip cksum */
622		-#define ETXD_CHKOFF_MASK 0x07f00000 /* cksum byte offset */
623		-#define ETXD_CHKOFF_SHIFT 20
624		-
625		-#define ETXD_D0CNT_MASK 0x0000007f
626		-#define ETXD_B1CNT_MASK 0x0007ff00
627		-#define ETXD_B1CNT_SHIFT 8
628		-#define ETXD_B2CNT_MASK 0x7ff00000
629		-#define ETXD_B2CNT_SHIFT 20
630		-
631		-typedef enum ioc3_subdevs_e {
632		- ioc3_subdev_ether,
633		- ioc3_subdev_generic,
634		- ioc3_subdev_nic,
635		- ioc3_subdev_kbms,
636		- ioc3_subdev_ttya,
637		- ioc3_subdev_ttyb,
638		- ioc3_subdev_ecpp,
639		- ioc3_subdev_rt,
640		- ioc3_nsubdevs
641		-} ioc3_subdev_t;
642		-
643		-/* subdevice disable bits,
644		- * from the standard INFO_LBL_SUBDEVS
645		- */
646		-#define IOC3_SDB_ETHER (1<<ioc3_subdev_ether)
647		-#define IOC3_SDB_GENERIC (1<<ioc3_subdev_generic)
648		-#define IOC3_SDB_NIC (1<<ioc3_subdev_nic)
649		-#define IOC3_SDB_KBMS (1<<ioc3_subdev_kbms)
650		-#define IOC3_SDB_TTYA (1<<ioc3_subdev_ttya)
651		-#define IOC3_SDB_TTYB (1<<ioc3_subdev_ttyb)
652		-#define IOC3_SDB_ECPP (1<<ioc3_subdev_ecpp)
653		-#define IOC3_SDB_RT (1<<ioc3_subdev_rt)
654		-
655		-#define IOC3_ALL_SUBDEVS ((1<<ioc3_nsubdevs)-1)
656		-
657		-#define IOC3_SDB_SERIAL (IOC3_SDB_TTYA\|IOC3_SDB_TTYB)
658		-
659		-#define IOC3_STD_SUBDEVS IOC3_ALL_SUBDEVS
660		-
661		-#define IOC3_INTA_SUBDEVS IOC3_SDB_ETHER
662		-#define IOC3_INTB_SUBDEVS (IOC3_SDB_GENERIC\|IOC3_SDB_KBMS\|IOC3_SDB_SERIAL\|IOC3_SDB_ECPP\|IOC3_SDB_RT)
663		-
664		-#endif /* _IOC3_H */
	606	+#endif /* MIPS_SN_IOC3_H */