| .. | .. |
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| 31 | 31 | { |
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| 32 | 32 | unsigned long result; |
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| 33 | 33 | |
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| 34 | | - if (kernel_uses_llsc && R10000_LLSC_WAR) { |
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| 34 | + if (kernel_uses_llsc && IS_ENABLED(CONFIG_WAR_R10000_LLSC)) { |
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| 35 | 35 | unsigned long temp; |
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| 36 | 36 | |
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| 37 | 37 | __asm__ __volatile__( |
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| 38 | + " .set push \n" |
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| 38 | 39 | " .set arch=r4000 \n" |
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| 40 | + __SYNC(full, loongson3_war) " \n" |
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| 39 | 41 | "1:" __LL "%1, %2 # local_add_return \n" |
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| 40 | 42 | " addu %0, %1, %3 \n" |
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| 41 | 43 | __SC "%0, %2 \n" |
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| 42 | 44 | " beqzl %0, 1b \n" |
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| 43 | 45 | " addu %0, %1, %3 \n" |
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| 44 | | - " .set mips0 \n" |
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| 46 | + " .set pop \n" |
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| 45 | 47 | : "=&r" (result), "=&r" (temp), "=m" (l->a.counter) |
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| 46 | 48 | : "Ir" (i), "m" (l->a.counter) |
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| 47 | 49 | : "memory"); |
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| .. | .. |
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| 49 | 51 | unsigned long temp; |
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| 50 | 52 | |
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| 51 | 53 | __asm__ __volatile__( |
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| 54 | + " .set push \n" |
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| 52 | 55 | " .set "MIPS_ISA_ARCH_LEVEL" \n" |
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| 56 | + __SYNC(full, loongson3_war) " \n" |
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| 53 | 57 | "1:" __LL "%1, %2 # local_add_return \n" |
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| 54 | 58 | " addu %0, %1, %3 \n" |
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| 55 | 59 | __SC "%0, %2 \n" |
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| 56 | 60 | " beqz %0, 1b \n" |
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| 57 | 61 | " addu %0, %1, %3 \n" |
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| 58 | | - " .set mips0 \n" |
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| 62 | + " .set pop \n" |
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| 59 | 63 | : "=&r" (result), "=&r" (temp), "=m" (l->a.counter) |
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| 60 | 64 | : "Ir" (i), "m" (l->a.counter) |
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| 61 | 65 | : "memory"); |
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| .. | .. |
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| 76 | 80 | { |
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| 77 | 81 | unsigned long result; |
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| 78 | 82 | |
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| 79 | | - if (kernel_uses_llsc && R10000_LLSC_WAR) { |
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| 83 | + if (kernel_uses_llsc && IS_ENABLED(CONFIG_WAR_R10000_LLSC)) { |
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| 80 | 84 | unsigned long temp; |
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| 81 | 85 | |
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| 82 | 86 | __asm__ __volatile__( |
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| 87 | + " .set push \n" |
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| 83 | 88 | " .set arch=r4000 \n" |
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| 89 | + __SYNC(full, loongson3_war) " \n" |
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| 84 | 90 | "1:" __LL "%1, %2 # local_sub_return \n" |
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| 85 | 91 | " subu %0, %1, %3 \n" |
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| 86 | 92 | __SC "%0, %2 \n" |
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| 87 | 93 | " beqzl %0, 1b \n" |
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| 88 | 94 | " subu %0, %1, %3 \n" |
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| 89 | | - " .set mips0 \n" |
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| 95 | + " .set pop \n" |
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| 90 | 96 | : "=&r" (result), "=&r" (temp), "=m" (l->a.counter) |
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| 91 | 97 | : "Ir" (i), "m" (l->a.counter) |
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| 92 | 98 | : "memory"); |
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| .. | .. |
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| 94 | 100 | unsigned long temp; |
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| 95 | 101 | |
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| 96 | 102 | __asm__ __volatile__( |
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| 103 | + " .set push \n" |
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| 97 | 104 | " .set "MIPS_ISA_ARCH_LEVEL" \n" |
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| 105 | + __SYNC(full, loongson3_war) " \n" |
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| 98 | 106 | "1:" __LL "%1, %2 # local_sub_return \n" |
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| 99 | 107 | " subu %0, %1, %3 \n" |
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| 100 | 108 | __SC "%0, %2 \n" |
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| 101 | 109 | " beqz %0, 1b \n" |
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| 102 | 110 | " subu %0, %1, %3 \n" |
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| 103 | | - " .set mips0 \n" |
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| 111 | + " .set pop \n" |
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| 104 | 112 | : "=&r" (result), "=&r" (temp), "=m" (l->a.counter) |
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| 105 | 113 | : "Ir" (i), "m" (l->a.counter) |
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| 106 | 114 | : "memory"); |
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