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hc
2024-01-05 071106ecf68c401173c58808b1cf5f68cc50d390 
 kernel/arch/mips/include/asm/io.h
....@@ -20,6 +20,7 @@
2020 #include <linux/irqflags.h>
2121 
2222 #include <asm/addrspace.h>
23
+#include <asm/barrier.h>
2324 #include <asm/bug.h>
2425 #include <asm/byteorder.h>
2526 #include <asm/cpu.h>
....@@ -29,14 +30,7 @@
2930 #include <asm/pgtable-bits.h>
3031 #include <asm/processor.h>
3132 #include <asm/string.h>
32
-
33
-#include <ioremap.h>
3433 #include <mangle-port.h>
35
-
36
-/*
37
- * Slowdown I/O port space accesses for antique hardware.
38
- */
39
-#undef CONF_SLOWDOWN_IO
4034 
4135 /*
4236  * Raw operations are never swapped in software.  OTOH values that raw
....@@ -50,9 +44,12 @@
5044 # define __raw_ioswabq(a, x)	(x)
5145 # define ____raw_ioswabq(a, x)	(x)
5246 
53
-/* ioswab[bwlq], __mem_ioswab[bwlq] are defined in mangle-port.h */
47
+# define __relaxed_ioswabb ioswabb
48
+# define __relaxed_ioswabw ioswabw
49
+# define __relaxed_ioswabl ioswabl
50
+# define __relaxed_ioswabq ioswabq
5451 
55
-#define IO_SPACE_LIMIT 0xffff
52
+/* ioswab[bwlq], __mem_ioswab[bwlq] are defined in mangle-port.h */
5653 
5754 /*
5855  * On MIPS I/O ports are memory mapped, so we access them using normal
....@@ -60,7 +57,7 @@
6057  * which all ports are being mapped.  For sake of efficiency some code
6158  * assumes that this is an address that can be loaded with a single lui
6259  * instruction, so the lower 16 bits must be zero.  Should be true on
63
- * on any sane architecture; generic code does not use this assumption.
60
+ * any sane architecture; generic code does not use this assumption.
6461  */
6562 extern unsigned long mips_io_port_base;
6663 
....@@ -70,31 +67,26 @@
7067 }
7168 
7269 /*
73
- * Thanks to James van Artsdalen for a better timing-fix than
74
- * the two short jumps: using outb's to a nonexistent port seems
75
- * to guarantee better timings even on fast machines.
76
- *
77
- * On the other hand, I'd like to be sure of a non-existent port:
78
- * I feel a bit unsafe about using 0x80 (should be safe, though)
79
- *
80
- *		Linus
81
- *
70
+ * Provide the necessary definitions for generic iomap. We make use of
71
+ * mips_io_port_base for iomap(), but we don't reserve any low addresses for
72
+ * use with I/O ports.
8273  */
8374 
84
-#define __SLOW_DOWN_IO \
85
-	__asm__ __volatile__( \
86
-		"sb\t$0,0x80(%0)" \
87
-		: : "r" (mips_io_port_base));
75
+#define HAVE_ARCH_PIO_SIZE
76
+#define PIO_OFFSET	mips_io_port_base
77
+#define PIO_MASK	IO_SPACE_LIMIT
78
+#define PIO_RESERVED	0x0UL
8879 
89
-#ifdef CONF_SLOWDOWN_IO
90
-#ifdef REALLY_SLOW_IO
91
-#define SLOW_DOWN_IO { __SLOW_DOWN_IO; __SLOW_DOWN_IO; __SLOW_DOWN_IO; __SLOW_DOWN_IO; }
92
-#else
93
-#define SLOW_DOWN_IO __SLOW_DOWN_IO
94
-#endif
95
-#else
96
-#define SLOW_DOWN_IO
97
-#endif
80
+/*
81
+ * Enforce in-order execution of data I/O.  In the MIPS architecture
82
+ * these are equivalent to corresponding platform-specific memory
83
+ * barriers defined in <asm/barrier.h>.  API pinched from PowerPC,
84
+ * with sync additionally defined.
85
+ */
86
+#define iobarrier_rw() mb()
87
+#define iobarrier_r() rmb()
88
+#define iobarrier_w() wmb()
89
+#define iobarrier_sync() iob()
9890 
9991 /*
10092  *     virt_to_phys    -       map virtual addresses to physical
....@@ -143,8 +135,6 @@
143135 	return phys_to_virt(address);
144136 }
145137 
146
-#define isa_page_to_bus page_to_phys
147
-
148138 /*
149139  * However PCI ones are not necessarily 1:1 and therefore these interfaces
150140  * are forbidden in portable PCI drivers.
....@@ -159,59 +149,9 @@
159149  */
160150 #define page_to_phys(page)	((dma_addr_t)page_to_pfn(page) << PAGE_SHIFT)
161151 
162
-extern void __iomem * __ioremap(phys_addr_t offset, phys_addr_t size, unsigned long flags);
163
-extern void __iounmap(const volatile void __iomem *addr);
164
-
165
-#ifndef CONFIG_PCI
166
-struct pci_dev;
167
-static inline void pci_iounmap(struct pci_dev *dev, void __iomem *addr) {}
168
-#endif
169
-
170
-static inline void __iomem * __ioremap_mode(phys_addr_t offset, unsigned long size,
171
-	unsigned long flags)
172
-{
173
-	void __iomem *addr = plat_ioremap(offset, size, flags);
174
-
175
-	if (addr)
176
-		return addr;
177
-
178
-#define __IS_LOW512(addr) (!((phys_addr_t)(addr) & (phys_addr_t) ~0x1fffffffULL))
179
-
180
-	if (cpu_has_64bit_addresses) {
181
-		u64 base = UNCAC_BASE;
182
-
183
-		/*
184
-		 * R10000 supports a 2 bit uncached attribute therefore
185
-		 * UNCAC_BASE may not equal IO_BASE.
186
-		 */
187
-		if (flags == _CACHE_UNCACHED)
188
-			base = (u64) IO_BASE;
189
-		return (void __iomem *) (unsigned long) (base + offset);
190
-	} else if (__builtin_constant_p(offset) &&
191
-		   __builtin_constant_p(size) && __builtin_constant_p(flags)) {
192
-		phys_addr_t phys_addr, last_addr;
193
-
194
-		phys_addr = fixup_bigphys_addr(offset, size);
195
-
196
-		/* Don't allow wraparound or zero size. */
197
-		last_addr = phys_addr + size - 1;
198
-		if (!size || last_addr < phys_addr)
199
-			return NULL;
200
-
201
-		/*
202
-		 * Map uncached objects in the low 512MB of address
203
-		 * space using KSEG1.
204
-		 */
205
-		if (__IS_LOW512(phys_addr) && __IS_LOW512(last_addr) &&
206
-		    flags == _CACHE_UNCACHED)
207
-			return (void __iomem *)
208
-				(unsigned long)CKSEG1ADDR(phys_addr);
209
-	}
210
-
211
-	return __ioremap(offset, size, flags);
212
-
213
-#undef __IS_LOW512
214
-}
152
+void __iomem *ioremap_prot(phys_addr_t offset, unsigned long size,
153
+		unsigned long prot_val);
154
+void iounmap(const volatile void __iomem *addr);
215155 
216156 /*
217157  * ioremap     -   map bus memory into CPU space
....@@ -225,37 +165,15 @@
225165  * address.
226166  */
227167 #define ioremap(offset, size)						\
228
-	__ioremap_mode((offset), (size), _CACHE_UNCACHED)
168
+	ioremap_prot((offset), (size), _CACHE_UNCACHED)
169
+#define ioremap_uc		ioremap
229170 
230171 /*
231
- * ioremap_nocache     -   map bus memory into CPU space
232
- * @offset:    bus address of the memory
233
- * @size:      size of the resource to map
234
- *
235
- * ioremap_nocache performs a platform specific sequence of operations to
236
- * make bus memory CPU accessible via the readb/readw/readl/writeb/
237
- * writew/writel functions and the other mmio helpers. The returned
238
- * address is not guaranteed to be usable directly as a virtual
239
- * address.
240
- *
241
- * This version of ioremap ensures that the memory is marked uncachable
242
- * on the CPU as well as honouring existing caching rules from things like
243
- * the PCI bus. Note that there are other caches and buffers on many
244
- * busses. In particular driver authors should read up on PCI writes
245
- *
246
- * It's useful if some control registers are in such an area and
247
- * write combining or read caching is not desirable:
248
- */
249
-#define ioremap_nocache(offset, size)					\
250
-	__ioremap_mode((offset), (size), _CACHE_UNCACHED)
251
-#define ioremap_uc ioremap_nocache
252
-
253
-/*
254
- * ioremap_cachable -	map bus memory into CPU space
172
+ * ioremap_cache -	map bus memory into CPU space
255173  * @offset:	    bus address of the memory
256174  * @size:	    size of the resource to map
257175  *
258
- * ioremap_nocache performs a platform specific sequence of operations to
176
+ * ioremap_cache performs a platform specific sequence of operations to
259177  * make bus memory CPU accessible via the readb/readw/readl/writeb/
260178  * writew/writel functions and the other mmio helpers. The returned
261179  * address is not guaranteed to be usable directly as a virtual
....@@ -265,9 +183,8 @@
265183  * the CPU.  Also enables full write-combining.	 Useful for some
266184  * memory-like regions on I/O busses.
267185  */
268
-#define ioremap_cachable(offset, size)					\
269
-	__ioremap_mode((offset), (size), _page_cachable_default)
270
-#define ioremap_cache ioremap_cachable
186
+#define ioremap_cache(offset, size)					\
187
+	ioremap_prot((offset), (size), _page_cachable_default)
271188 
272189 /*
273190  * ioremap_wc     -   map bus memory into CPU space
....@@ -288,31 +205,15 @@
288205  * _CACHE_UNCACHED option (see cpu_probe() method).
289206  */
290207 #define ioremap_wc(offset, size)					\
291
-	__ioremap_mode((offset), (size), boot_cpu_data.writecombine)
208
+	ioremap_prot((offset), (size), boot_cpu_data.writecombine)
292209 
293
-static inline void iounmap(const volatile void __iomem *addr)
294
-{
295
-	if (plat_iounmap(addr))
296
-		return;
297
-
298
-#define __IS_KSEG1(addr) (((unsigned long)(addr) & ~0x1fffffffUL) == CKSEG1)
299
-
300
-	if (cpu_has_64bit_addresses ||
301
-	    (__builtin_constant_p(addr) && __IS_KSEG1(addr)))
302
-		return;
303
-
304
-	__iounmap(addr);
305
-
306
-#undef __IS_KSEG1
307
-}
308
-
309
-#if defined(CONFIG_CPU_CAVIUM_OCTEON) || defined(CONFIG_LOONGSON3_ENHANCEMENT)
210
+#if defined(CONFIG_CPU_CAVIUM_OCTEON) || defined(CONFIG_CPU_LOONGSON64)
310211 #define war_io_reorder_wmb()		wmb()
311212 #else
312213 #define war_io_reorder_wmb()		barrier()
313214 #endif
314215 
315
-#define __BUILD_MEMORY_SINGLE(pfx, bwlq, type, irq)			\
216
+#define __BUILD_MEMORY_SINGLE(pfx, bwlq, type, barrier, relax, irq)	\
316217 									\
317218 static inline void pfx##write##bwlq(type val,				\
318219 				    volatile void __iomem *mem)		\
....@@ -320,7 +221,10 @@
320221 	volatile type *__mem;						\
321222 	type __val;							\
322223 									\
323
-	war_io_reorder_wmb();					\
224
+	if (barrier)							\
225
+		iobarrier_rw();						\
226
+	else								\
227
+		war_io_reorder_wmb();					\
324228 									\
325229 	__mem = (void *)__swizzle_addr_##bwlq((unsigned long)(mem));	\
326230 									\
....@@ -335,13 +239,14 @@
335239 		if (irq)						\
336240 			local_irq_save(__flags);			\
337241 		__asm__ __volatile__(					\
338
-			".set	arch=r4000"	"\t\t# __writeq""\n\t"	\
242
+			".set	push"		"\t\t# __writeq""\n\t"	\
243
+			".set	arch=r4000"			"\n\t"	\
339244 			"dsll32 %L0, %L0, 0"			"\n\t"	\
340245 			"dsrl32 %L0, %L0, 0"			"\n\t"	\
341246 			"dsll32 %M0, %M0, 0"			"\n\t"	\
342247 			"or	%L0, %L0, %M0"			"\n\t"	\
343248 			"sd	%L0, %2"			"\n\t"	\
344
-			".set	mips0"				"\n"	\
249
+			".set	pop"				"\n"	\
345250 			: "=r" (__tmp)					\
346251 			: "0" (__val), "m" (*__mem));			\
347252 		if (irq)						\
....@@ -357,6 +262,9 @@
357262 									\
358263 	__mem = (void *)__swizzle_addr_##bwlq((unsigned long)(mem));	\
359264 									\
265
+	if (barrier)							\
266
+		iobarrier_rw();						\
267
+									\
360268 	if (sizeof(type) != sizeof(u64) || sizeof(u64) == sizeof(long)) \
361269 		__val = *__mem;						\
362270 	else if (cpu_has_64bits) {					\
....@@ -365,11 +273,12 @@
365273 		if (irq)						\
366274 			local_irq_save(__flags);			\
367275 		__asm__ __volatile__(					\
368
-			".set	arch=r4000"	"\t\t# __readq" "\n\t"	\
276
+			".set	push"		"\t\t# __readq" "\n\t"	\
277
+			".set	arch=r4000"			"\n\t"	\
369278 			"ld	%L0, %1"			"\n\t"	\
370279 			"dsra32 %M0, %L0, 0"			"\n\t"	\
371280 			"sll	%L0, %L0, 0"			"\n\t"	\
372
-			".set	mips0"				"\n"	\
281
+			".set	pop"				"\n"	\
373282 			: "=r" (__val)					\
374283 			: "m" (*__mem));				\
375284 		if (irq)						\
....@@ -380,18 +289,22 @@
380289 	}								\
381290 									\
382291 	/* prevent prefetching of coherent DMA data prematurely */	\
383
-	rmb();								\
292
+	if (!relax)							\
293
+		rmb();							\
384294 	return pfx##ioswab##bwlq(__mem, __val);				\
385295 }
386296 
387
-#define __BUILD_IOPORT_SINGLE(pfx, bwlq, type, p, slow)			\
297
+#define __BUILD_IOPORT_SINGLE(pfx, bwlq, type, barrier, relax, p)	\
388298 									\
389299 static inline void pfx##out##bwlq##p(type val, unsigned long port)	\
390300 {									\
391301 	volatile type *__addr;						\
392302 	type __val;							\
393303 									\
394
-	war_io_reorder_wmb();					\
304
+	if (barrier)							\
305
+		iobarrier_rw();						\
306
+	else								\
307
+		war_io_reorder_wmb();					\
395308 									\
396309 	__addr = (void *)__swizzle_addr_##bwlq(mips_io_port_base + port); \
397310 									\
....@@ -401,7 +314,6 @@
401314 	BUILD_BUG_ON(sizeof(type) > sizeof(unsigned long));		\
402315 									\
403316 	*__addr = __val;						\
404
-	slow;								\
405317 }									\
406318 									\
407319 static inline type pfx##in##bwlq##p(unsigned long port)			\
....@@ -413,32 +325,41 @@
413325 									\
414326 	BUILD_BUG_ON(sizeof(type) > sizeof(unsigned long));		\
415327 									\
328
+	if (barrier)							\
329
+		iobarrier_rw();						\
330
+									\
416331 	__val = *__addr;						\
417
-	slow;								\
418332 									\
419333 	/* prevent prefetching of coherent DMA data prematurely */	\
420
-	rmb();								\
334
+	if (!relax)							\
335
+		rmb();							\
421336 	return pfx##ioswab##bwlq(__addr, __val);			\
422337 }
423338 
424
-#define __BUILD_MEMORY_PFX(bus, bwlq, type)				\
339
+#define __BUILD_MEMORY_PFX(bus, bwlq, type, relax)			\
425340 									\
426
-__BUILD_MEMORY_SINGLE(bus, bwlq, type, 1)
341
+__BUILD_MEMORY_SINGLE(bus, bwlq, type, 1, relax, 1)
427342 
428343 #define BUILDIO_MEM(bwlq, type)						\
429344 									\
430
-__BUILD_MEMORY_PFX(__raw_, bwlq, type)					\
431
-__BUILD_MEMORY_PFX(, bwlq, type)					\
432
-__BUILD_MEMORY_PFX(__mem_, bwlq, type)					\
345
+__BUILD_MEMORY_PFX(__raw_, bwlq, type, 0)				\
346
+__BUILD_MEMORY_PFX(__relaxed_, bwlq, type, 1)				\
347
+__BUILD_MEMORY_PFX(__mem_, bwlq, type, 0)				\
348
+__BUILD_MEMORY_PFX(, bwlq, type, 0)
433349 
434350 BUILDIO_MEM(b, u8)
435351 BUILDIO_MEM(w, u16)
436352 BUILDIO_MEM(l, u32)
353
+#ifdef CONFIG_64BIT
437354 BUILDIO_MEM(q, u64)
355
+#else
356
+__BUILD_MEMORY_PFX(__raw_, q, u64, 0)
357
+__BUILD_MEMORY_PFX(__mem_, q, u64, 0)
358
+#endif
438359 
439360 #define __BUILD_IOPORT_PFX(bus, bwlq, type)				\
440
-	__BUILD_IOPORT_SINGLE(bus, bwlq, type, ,)			\
441
-	__BUILD_IOPORT_SINGLE(bus, bwlq, type, _p, SLOW_DOWN_IO)
361
+	__BUILD_IOPORT_SINGLE(bus, bwlq, type, 1, 0,)			\
362
+	__BUILD_IOPORT_SINGLE(bus, bwlq, type, 1, 0, _p)
442363 
443364 #define BUILDIO_IOPORT(bwlq, type)					\
444365 	__BUILD_IOPORT_PFX(, bwlq, type)				\
....@@ -453,19 +374,23 @@
453374 
454375 #define __BUILDIO(bwlq, type)						\
455376 									\
456
-__BUILD_MEMORY_SINGLE(____raw_, bwlq, type, 0)
377
+__BUILD_MEMORY_SINGLE(____raw_, bwlq, type, 1, 0, 0)
457378 
458379 __BUILDIO(q, u64)
459380 
460
-#define readb_relaxed			readb
461
-#define readw_relaxed			readw
462
-#define readl_relaxed			readl
463
-#define readq_relaxed			readq
381
+#define readb_relaxed			__relaxed_readb
382
+#define readw_relaxed			__relaxed_readw
383
+#define readl_relaxed			__relaxed_readl
384
+#ifdef CONFIG_64BIT
385
+#define readq_relaxed			__relaxed_readq
386
+#endif
464387 
465
-#define writeb_relaxed			writeb
466
-#define writew_relaxed			writew
467
-#define writel_relaxed			writel
468
-#define writeq_relaxed			writeq
388
+#define writeb_relaxed			__relaxed_writeb
389
+#define writew_relaxed			__relaxed_writew
390
+#define writel_relaxed			__relaxed_writel
391
+#ifdef CONFIG_64BIT
392
+#define writeq_relaxed			__relaxed_writeq
393
+#endif
469394 
470395 #define readb_be(addr)							\
471396 	__raw_readb((__force unsigned *)(addr))
....@@ -488,8 +413,10 @@
488413 /*
489414  * Some code tests for these symbols
490415  */
416
+#ifdef CONFIG_64BIT
491417 #define readq				readq
492418 #define writeq				writeq
419
+#endif
493420 
494421 #define __BUILD_MEMORY_STRING(bwlq, type)				\
495422 									\
....@@ -549,14 +476,6 @@
549476 BUILDSTRING(l, u32)
550477 #ifdef CONFIG_64BIT
551478 BUILDSTRING(q, u64)
552
-#endif
553
-
554
-
555
-#ifdef CONFIG_CPU_CAVIUM_OCTEON
556
-#define mmiowb() wmb()
557
-#else
558
-/* Depends on MIPS II instruction set */
559
-#define mmiowb() asm volatile ("sync" ::: "memory")
560479 #endif
561480 
562481 static inline void memset_io(volatile void __iomem *addr, unsigned char val, int count)