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2024-01-05 071106ecf68c401173c58808b1cf5f68cc50d390 
 kernel/arch/mips/include/asm/cpu.h
....@@ -9,6 +9,8 @@
99 #ifndef _ASM_CPU_H
1010 #define _ASM_CPU_H
1111 
12
+#include <linux/bits.h>
13
+
1214 /*
1315    As of the MIPS32 and MIPS64 specs from MTI, the PRId register (CP0
1416    register 15, select 0) is defined in this (backwards compatible) way:
....@@ -44,8 +46,9 @@
4446 #define PRID_COMP_NETLOGIC	0x0c0000
4547 #define PRID_COMP_CAVIUM	0x0d0000
4648 #define PRID_COMP_LOONGSON	0x140000
47
-#define PRID_COMP_INGENIC_D0	0xd00000	/* JZ4740, JZ4750 */
48
-#define PRID_COMP_INGENIC_D1	0xd10000	/* JZ4770, JZ4775 */
49
+#define PRID_COMP_INGENIC_13	0x130000	/* X2000 */
50
+#define PRID_COMP_INGENIC_D0	0xd00000	/* JZ4740, JZ4750, X1830 */
51
+#define PRID_COMP_INGENIC_D1	0xd10000	/* JZ4770, JZ4775, X1000 */
4952 #define PRID_COMP_INGENIC_E1	0xe10000	/* JZ4780 */
5053 
5154 /*
....@@ -89,7 +92,9 @@
8992 #define PRID_IMP_LOONGSON_32	0x4200  /* Loongson-1 */
9093 #define PRID_IMP_R5432		0x5400
9194 #define PRID_IMP_R5500		0x5500
92
-#define PRID_IMP_LOONGSON_64	0x6300  /* Loongson-2/3 */
95
+#define PRID_IMP_LOONGSON_64R	0x6100  /* Reduced Loongson-2 */
96
+#define PRID_IMP_LOONGSON_64C	0x6300  /* Classic Loongson-2 and Loongson-3 */
97
+#define PRID_IMP_LOONGSON_64G	0xc000  /* Generic Loongson-2 and Loongson-3 */
9398 
9499 #define PRID_IMP_UNKNOWN	0xff00
95100 
....@@ -181,7 +186,9 @@
181186  * These are the PRID's for when 23:16 == PRID_COMP_INGENIC_*
182187  */
183188 
184
-#define PRID_IMP_JZRISC	       0x0200
189
+#define PRID_IMP_XBURST_REV1	0x0200	/* XBurst®1 with MXU1.0/MXU1.1 SIMD ISA	*/
190
+#define PRID_IMP_XBURST_REV2	0x0100	/* XBurst®1 with MXU2.0 SIMD ISA		*/
191
+#define PRID_IMP_XBURST2		0x2000	/* XBurst®2 with MXU2.1 SIMD ISA		*/
185192 
186193 /*
187194  * These are the PRID's for when 23:16 == PRID_COMP_NETLOGIC
....@@ -245,11 +252,16 @@
245252 #define PRID_REV_LOONGSON1C		0x0020	/* Same as Loongson-1B */
246253 #define PRID_REV_LOONGSON2E		0x0002
247254 #define PRID_REV_LOONGSON2F		0x0003
255
+#define PRID_REV_LOONGSON2K_R1_0	0x0000
256
+#define PRID_REV_LOONGSON2K_R1_1	0x0001
257
+#define PRID_REV_LOONGSON2K_R1_2	0x0002
258
+#define PRID_REV_LOONGSON2K_R1_3	0x0003
248259 #define PRID_REV_LOONGSON3A_R1		0x0005
249260 #define PRID_REV_LOONGSON3B_R1		0x0006
250261 #define PRID_REV_LOONGSON3B_R2		0x0007
251
-#define PRID_REV_LOONGSON3A_R2		0x0008
262
+#define PRID_REV_LOONGSON3A_R2_0	0x0008
252263 #define PRID_REV_LOONGSON3A_R3_0	0x0009
264
+#define PRID_REV_LOONGSON3A_R2_1	0x000c
253265 #define PRID_REV_LOONGSON3A_R3_1	0x000d
254266 
255267 /*
....@@ -290,17 +302,12 @@
290302 	/*
291303 	 * R4000 class processors
292304 	 */
293
-	CPU_R4000PC, CPU_R4000SC, CPU_R4000MC, CPU_R4200, CPU_R4300, CPU_R4310,
305
+	CPU_R4000PC, CPU_R4000SC, CPU_R4000MC, CPU_R4200,
294306 	CPU_R4400PC, CPU_R4400SC, CPU_R4400MC, CPU_R4600, CPU_R4640, CPU_R4650,
295
-	CPU_R4700, CPU_R5000, CPU_R5500, CPU_NEVADA, CPU_R5432, CPU_R10000,
307
+	CPU_R4700, CPU_R5000, CPU_R5500, CPU_NEVADA, CPU_R10000,
296308 	CPU_R12000, CPU_R14000, CPU_R16000, CPU_VR41XX, CPU_VR4111, CPU_VR4121,
297309 	CPU_VR4122, CPU_VR4131, CPU_VR4133, CPU_VR4181, CPU_VR4181A, CPU_RM7000,
298310 	CPU_SR71000, CPU_TX49XX,
299
-
300
-	/*
301
-	 * R8000 class processors
302
-	 */
303
-	CPU_R8000,
304311 
305312 	/*
306313 	 * TX3900 class processors
....@@ -312,15 +319,15 @@
312319 	 */
313320 	CPU_4KC, CPU_4KEC, CPU_4KSC, CPU_24K, CPU_34K, CPU_1004K, CPU_74K,
314321 	CPU_ALCHEMY, CPU_PR4450, CPU_BMIPS32, CPU_BMIPS3300, CPU_BMIPS4350,
315
-	CPU_BMIPS4380, CPU_BMIPS5000, CPU_JZRISC, CPU_LOONGSON1, CPU_M14KC,
322
+	CPU_BMIPS4380, CPU_BMIPS5000, CPU_XBURST, CPU_LOONGSON32, CPU_M14KC,
316323 	CPU_M14KEC, CPU_INTERAPTIV, CPU_P5600, CPU_PROAPTIV, CPU_1074K,
317324 	CPU_M5150, CPU_I6400, CPU_P6600, CPU_M6250,
318325 
319326 	/*
320327 	 * MIPS64 class processors
321328 	 */
322
-	CPU_5KC, CPU_5KE, CPU_20KC, CPU_25KF, CPU_SB1, CPU_SB1A, CPU_LOONGSON2,
323
-	CPU_LOONGSON3, CPU_CAVIUM_OCTEON, CPU_CAVIUM_OCTEON_PLUS,
329
+	CPU_5KC, CPU_5KE, CPU_20KC, CPU_25KF, CPU_SB1, CPU_SB1A, CPU_LOONGSON2EF,
330
+	CPU_LOONGSON64, CPU_CAVIUM_OCTEON, CPU_CAVIUM_OCTEON_PLUS,
324331 	CPU_CAVIUM_OCTEON2, CPU_CAVIUM_OCTEON3, CPU_XLR, CPU_XLP, CPU_I6500,
325332 
326333 	CPU_QEMU_GENERIC,
....@@ -342,85 +349,85 @@
342349 #define MIPS_CPU_ISA_M32R2	0x00000020
343350 #define MIPS_CPU_ISA_M64R1	0x00000040
344351 #define MIPS_CPU_ISA_M64R2	0x00000080
345
-#define MIPS_CPU_ISA_M32R6	0x00000100
346
-#define MIPS_CPU_ISA_M64R6	0x00000200
352
+#define MIPS_CPU_ISA_M32R5	0x00000100
353
+#define MIPS_CPU_ISA_M64R5	0x00000200
354
+#define MIPS_CPU_ISA_M32R6	0x00000400
355
+#define MIPS_CPU_ISA_M64R6	0x00000800
347356 
348357 #define MIPS_CPU_ISA_32BIT (MIPS_CPU_ISA_II | MIPS_CPU_ISA_M32R1 | \
349
-	MIPS_CPU_ISA_M32R2 | MIPS_CPU_ISA_M32R6)
358
+	MIPS_CPU_ISA_M32R2 | MIPS_CPU_ISA_M32R5 | MIPS_CPU_ISA_M32R6)
350359 #define MIPS_CPU_ISA_64BIT (MIPS_CPU_ISA_III | MIPS_CPU_ISA_IV | \
351360 	MIPS_CPU_ISA_V | MIPS_CPU_ISA_M64R1 | MIPS_CPU_ISA_M64R2 | \
352
-	MIPS_CPU_ISA_M64R6)
353
-
354
-/*
355
- * Private version of BIT_ULL() to escape include file recursion hell.
356
- * We soon will have to switch to another mechanism that will work with
357
- * more than 64 bits anyway.
358
- */
359
-#define MBIT_ULL(bit)		(1ULL << (bit))
361
+	MIPS_CPU_ISA_M64R5 | MIPS_CPU_ISA_M64R6)
360362 
361363 /*
362364  * CPU Option encodings
363365  */
364
-#define MIPS_CPU_TLB		MBIT_ULL( 0)	/* CPU has TLB */
365
-#define MIPS_CPU_4KEX		MBIT_ULL( 1)	/* "R4K" exception model */
366
-#define MIPS_CPU_3K_CACHE	MBIT_ULL( 2)	/* R3000-style caches */
367
-#define MIPS_CPU_4K_CACHE	MBIT_ULL( 3)	/* R4000-style caches */
368
-#define MIPS_CPU_TX39_CACHE	MBIT_ULL( 4)	/* TX3900-style caches */
369
-#define MIPS_CPU_FPU		MBIT_ULL( 5)	/* CPU has FPU */
370
-#define MIPS_CPU_32FPR		MBIT_ULL( 6)	/* 32 dbl. prec. FP registers */
371
-#define MIPS_CPU_COUNTER	MBIT_ULL( 7)	/* Cycle count/compare */
372
-#define MIPS_CPU_WATCH		MBIT_ULL( 8)	/* watchpoint registers */
373
-#define MIPS_CPU_DIVEC		MBIT_ULL( 9)	/* dedicated interrupt vector */
374
-#define MIPS_CPU_VCE		MBIT_ULL(10)	/* virt. coherence conflict possible */
375
-#define MIPS_CPU_CACHE_CDEX_P	MBIT_ULL(11)	/* Create_Dirty_Exclusive CACHE op */
376
-#define MIPS_CPU_CACHE_CDEX_S	MBIT_ULL(12)	/* ... same for seconary cache ... */
377
-#define MIPS_CPU_MCHECK		MBIT_ULL(13)	/* Machine check exception */
378
-#define MIPS_CPU_EJTAG		MBIT_ULL(14)	/* EJTAG exception */
379
-#define MIPS_CPU_NOFPUEX	MBIT_ULL(15)	/* no FPU exception */
380
-#define MIPS_CPU_LLSC		MBIT_ULL(16)	/* CPU has ll/sc instructions */
381
-#define MIPS_CPU_INCLUSIVE_CACHES	MBIT_ULL(17)	/* P-cache subset enforced */
382
-#define MIPS_CPU_PREFETCH	MBIT_ULL(18)	/* CPU has usable prefetch */
383
-#define MIPS_CPU_VINT		MBIT_ULL(19)	/* CPU supports MIPSR2 vectored interrupts */
384
-#define MIPS_CPU_VEIC		MBIT_ULL(20)	/* CPU supports MIPSR2 external interrupt controller mode */
385
-#define MIPS_CPU_ULRI		MBIT_ULL(21)	/* CPU has ULRI feature */
386
-#define MIPS_CPU_PCI		MBIT_ULL(22)	/* CPU has Perf Ctr Int indicator */
387
-#define MIPS_CPU_RIXI		MBIT_ULL(23)	/* CPU has TLB Read/eXec Inhibit */
388
-#define MIPS_CPU_MICROMIPS	MBIT_ULL(24)	/* CPU has microMIPS capability */
389
-#define MIPS_CPU_TLBINV		MBIT_ULL(25)	/* CPU supports TLBINV/F */
390
-#define MIPS_CPU_SEGMENTS	MBIT_ULL(26)	/* CPU supports Segmentation Control registers */
391
-#define MIPS_CPU_EVA		MBIT_ULL(27)	/* CPU supports Enhanced Virtual Addressing */
392
-#define MIPS_CPU_HTW		MBIT_ULL(28)	/* CPU support Hardware Page Table Walker */
393
-#define MIPS_CPU_RIXIEX		MBIT_ULL(29)	/* CPU has unique exception codes for {Read, Execute}-Inhibit exceptions */
394
-#define MIPS_CPU_MAAR		MBIT_ULL(30)	/* MAAR(I) registers are present */
395
-#define MIPS_CPU_FRE		MBIT_ULL(31)	/* FRE & UFE bits implemented */
396
-#define MIPS_CPU_RW_LLB		MBIT_ULL(32)	/* LLADDR/LLB writes are allowed */
397
-#define MIPS_CPU_LPA		MBIT_ULL(33)	/* CPU supports Large Physical Addressing */
398
-#define MIPS_CPU_CDMM		MBIT_ULL(34)	/* CPU has Common Device Memory Map */
399
-#define MIPS_CPU_BP_GHIST	MBIT_ULL(35)	/* R12K+ Branch Prediction Global History */
400
-#define MIPS_CPU_SP		MBIT_ULL(36)	/* Small (1KB) page support */
401
-#define MIPS_CPU_FTLB		MBIT_ULL(37)	/* CPU has Fixed-page-size TLB */
402
-#define MIPS_CPU_NAN_LEGACY	MBIT_ULL(38)	/* Legacy NaN implemented */
403
-#define MIPS_CPU_NAN_2008	MBIT_ULL(39)	/* 2008 NaN implemented */
404
-#define MIPS_CPU_VP		MBIT_ULL(40)	/* MIPSr6 Virtual Processors (multi-threading) */
405
-#define MIPS_CPU_LDPTE		MBIT_ULL(41)	/* CPU has ldpte/lddir instructions */
406
-#define MIPS_CPU_MVH		MBIT_ULL(42)	/* CPU supports MFHC0/MTHC0 */
407
-#define MIPS_CPU_EBASE_WG	MBIT_ULL(43)	/* CPU has EBase.WG */
408
-#define MIPS_CPU_BADINSTR	MBIT_ULL(44)	/* CPU has BadInstr register */
409
-#define MIPS_CPU_BADINSTRP	MBIT_ULL(45)	/* CPU has BadInstrP register */
410
-#define MIPS_CPU_CTXTC		MBIT_ULL(46)	/* CPU has [X]ConfigContext registers */
411
-#define MIPS_CPU_PERF		MBIT_ULL(47)	/* CPU has MIPS performance counters */
412
-#define MIPS_CPU_GUESTCTL0EXT	MBIT_ULL(48)	/* CPU has VZ GuestCtl0Ext register */
413
-#define MIPS_CPU_GUESTCTL1	MBIT_ULL(49)	/* CPU has VZ GuestCtl1 register */
414
-#define MIPS_CPU_GUESTCTL2	MBIT_ULL(50)	/* CPU has VZ GuestCtl2 register */
415
-#define MIPS_CPU_GUESTID	MBIT_ULL(51)	/* CPU uses VZ ASE GuestID feature */
416
-#define MIPS_CPU_DRG		MBIT_ULL(52)	/* CPU has VZ Direct Root to Guest (DRG) */
417
-#define MIPS_CPU_UFR		MBIT_ULL(53)	/* CPU supports User mode FR switching */
366
+#define MIPS_CPU_TLB		BIT_ULL( 0)	/* CPU has TLB */
367
+#define MIPS_CPU_4KEX		BIT_ULL( 1)	/* "R4K" exception model */
368
+#define MIPS_CPU_3K_CACHE	BIT_ULL( 2)	/* R3000-style caches */
369
+#define MIPS_CPU_4K_CACHE	BIT_ULL( 3)	/* R4000-style caches */
370
+#define MIPS_CPU_TX39_CACHE	BIT_ULL( 4)	/* TX3900-style caches */
371
+#define MIPS_CPU_FPU		BIT_ULL( 5)	/* CPU has FPU */
372
+#define MIPS_CPU_32FPR		BIT_ULL( 6)	/* 32 dbl. prec. FP registers */
373
+#define MIPS_CPU_COUNTER	BIT_ULL( 7)	/* Cycle count/compare */
374
+#define MIPS_CPU_WATCH		BIT_ULL( 8)	/* watchpoint registers */
375
+#define MIPS_CPU_DIVEC		BIT_ULL( 9)	/* dedicated interrupt vector */
376
+#define MIPS_CPU_VCE		BIT_ULL(10)	/* virt. coherence conflict possible */
377
+#define MIPS_CPU_CACHE_CDEX_P	BIT_ULL(11)	/* Create_Dirty_Exclusive CACHE op */
378
+#define MIPS_CPU_CACHE_CDEX_S	BIT_ULL(12)	/* ... same for seconary cache ... */
379
+#define MIPS_CPU_MCHECK		BIT_ULL(13)	/* Machine check exception */
380
+#define MIPS_CPU_EJTAG		BIT_ULL(14)	/* EJTAG exception */
381
+#define MIPS_CPU_NOFPUEX	BIT_ULL(15)	/* no FPU exception */
382
+#define MIPS_CPU_LLSC		BIT_ULL(16)	/* CPU has ll/sc instructions */
383
+#define MIPS_CPU_INCLUSIVE_CACHES BIT_ULL(17)	/* P-cache subset enforced */
384
+#define MIPS_CPU_PREFETCH	BIT_ULL(18)	/* CPU has usable prefetch */
385
+#define MIPS_CPU_VINT		BIT_ULL(19)	/* CPU supports MIPSR2 vectored interrupts */
386
+#define MIPS_CPU_VEIC		BIT_ULL(20)	/* CPU supports MIPSR2 external interrupt controller mode */
387
+#define MIPS_CPU_ULRI		BIT_ULL(21)	/* CPU has ULRI feature */
388
+#define MIPS_CPU_PCI		BIT_ULL(22)	/* CPU has Perf Ctr Int indicator */
389
+#define MIPS_CPU_RIXI		BIT_ULL(23)	/* CPU has TLB Read/eXec Inhibit */
390
+#define MIPS_CPU_MICROMIPS	BIT_ULL(24)	/* CPU has microMIPS capability */
391
+#define MIPS_CPU_TLBINV		BIT_ULL(25)	/* CPU supports TLBINV/F */
392
+#define MIPS_CPU_SEGMENTS	BIT_ULL(26)	/* CPU supports Segmentation Control registers */
393
+#define MIPS_CPU_EVA		BIT_ULL(27)	/* CPU supports Enhanced Virtual Addressing */
394
+#define MIPS_CPU_HTW		BIT_ULL(28)	/* CPU support Hardware Page Table Walker */
395
+#define MIPS_CPU_RIXIEX		BIT_ULL(29)	/* CPU has unique exception codes for {Read, Execute}-Inhibit exceptions */
396
+#define MIPS_CPU_MAAR		BIT_ULL(30)	/* MAAR(I) registers are present */
397
+#define MIPS_CPU_FRE		BIT_ULL(31)	/* FRE & UFE bits implemented */
398
+#define MIPS_CPU_RW_LLB		BIT_ULL(32)	/* LLADDR/LLB writes are allowed */
399
+#define MIPS_CPU_LPA		BIT_ULL(33)	/* CPU supports Large Physical Addressing */
400
+#define MIPS_CPU_CDMM		BIT_ULL(34)	/* CPU has Common Device Memory Map */
401
+#define MIPS_CPU_SP		BIT_ULL(36)	/* Small (1KB) page support */
402
+#define MIPS_CPU_FTLB		BIT_ULL(37)	/* CPU has Fixed-page-size TLB */
403
+#define MIPS_CPU_NAN_LEGACY	BIT_ULL(38)	/* Legacy NaN implemented */
404
+#define MIPS_CPU_NAN_2008	BIT_ULL(39)	/* 2008 NaN implemented */
405
+#define MIPS_CPU_VP		BIT_ULL(40)	/* MIPSr6 Virtual Processors (multi-threading) */
406
+#define MIPS_CPU_LDPTE		BIT_ULL(41)	/* CPU has ldpte/lddir instructions */
407
+#define MIPS_CPU_MVH		BIT_ULL(42)	/* CPU supports MFHC0/MTHC0 */
408
+#define MIPS_CPU_EBASE_WG	BIT_ULL(43)	/* CPU has EBase.WG */
409
+#define MIPS_CPU_BADINSTR	BIT_ULL(44)	/* CPU has BadInstr register */
410
+#define MIPS_CPU_BADINSTRP	BIT_ULL(45)	/* CPU has BadInstrP register */
411
+#define MIPS_CPU_CTXTC		BIT_ULL(46)	/* CPU has [X]ConfigContext registers */
412
+#define MIPS_CPU_PERF		BIT_ULL(47)	/* CPU has MIPS performance counters */
413
+#define MIPS_CPU_GUESTCTL0EXT	BIT_ULL(48)	/* CPU has VZ GuestCtl0Ext register */
414
+#define MIPS_CPU_GUESTCTL1	BIT_ULL(49)	/* CPU has VZ GuestCtl1 register */
415
+#define MIPS_CPU_GUESTCTL2	BIT_ULL(50)	/* CPU has VZ GuestCtl2 register */
416
+#define MIPS_CPU_GUESTID	BIT_ULL(51)	/* CPU uses VZ ASE GuestID feature */
417
+#define MIPS_CPU_DRG		BIT_ULL(52)	/* CPU has VZ Direct Root to Guest (DRG) */
418
+#define MIPS_CPU_UFR		BIT_ULL(53)	/* CPU supports User mode FR switching */
418419 #define MIPS_CPU_SHARED_FTLB_RAM \
419
-				MBIT_ULL(54)	/* CPU shares FTLB RAM with another */
420
+				BIT_ULL(54)	/* CPU shares FTLB RAM with another */
420421 #define MIPS_CPU_SHARED_FTLB_ENTRIES \
421
-				MBIT_ULL(55)	/* CPU shares FTLB entries with another */
422
+				BIT_ULL(55)	/* CPU shares FTLB entries with another */
422423 #define MIPS_CPU_MT_PER_TC_PERF_COUNTERS \
423
-				MBIT_ULL(56)	/* CPU has perf counters implemented per TC (MIPSMT ASE) */
424
+				BIT_ULL(56)	/* CPU has perf counters implemented per TC (MIPSMT ASE) */
425
+#define MIPS_CPU_MMID		BIT_ULL(57)	/* CPU supports MemoryMapIDs */
426
+#define MIPS_CPU_MM_SYSAD	BIT_ULL(58)	/* CPU supports write-through SysAD Valid merge */
427
+#define MIPS_CPU_MM_FULL	BIT_ULL(59)	/* CPU supports write-through full merge */
428
+#define MIPS_CPU_MAC_2008_ONLY	BIT_ULL(60)	/* CPU Only support MAC2008 Fused multiply-add instruction */
429
+#define MIPS_CPU_FTLBPAREX	BIT_ULL(61)	/* CPU has FTLB parity exception */
430
+#define MIPS_CPU_GSEXCEX	BIT_ULL(62)	/* CPU has GSExc exception */
424431 
425432 /*
426433  * CPU ASE encodings