change wifi driver to cypress

hc

2024-01-05 071106ecf68c401173c58808b1cf5f68cc50d390

 kernel/arch/mips/include/asm/cpu-features.h
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@@ -15,6 +15,7 @@
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 #include <cpu-feature-overrides.h>
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 #define __ase(ase)			(cpu_data[0].ases & (ase))
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+#define __isa(isa)			(cpu_data[0].isa_level & (isa))
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 #define __opt(opt)			(cpu_data[0].options & (opt))
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 /*
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@@ -51,6 +52,20 @@
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  */
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 #define __isa_lt_and_ase(isa, ase)	((MIPS_ISA_REV < (isa)) && __ase(ase))
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 #define __isa_lt_and_opt(isa, opt)	((MIPS_ISA_REV < (isa)) && __opt(opt))
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+
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+/*
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+ * Similarly allow for ISA level checks that take into account knowledge of the
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+ * ISA targeted by the kernel build, provided by MIPS_ISA_REV.
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+ */
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+#define __isa_ge_and_flag(isa, flag)	((MIPS_ISA_REV >= (isa)) && __isa(flag))
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+#define __isa_ge_or_flag(isa, flag)	((MIPS_ISA_REV >= (isa)) || __isa(flag))
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+#define __isa_lt_and_flag(isa, flag)	((MIPS_ISA_REV < (isa)) && __isa(flag))
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+#define __isa_range(ge, lt) \
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+	((MIPS_ISA_REV >= (ge)) && (MIPS_ISA_REV < (lt)))
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+#define __isa_range_or_flag(ge, lt, flag) \
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+	(__isa_range(ge, lt) || ((MIPS_ISA_REV < (lt)) && __isa(flag)))
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+#define __isa_range_and_ase(ge, lt, ase) \
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+	(__isa_range(ge, lt) && __ase(ase))
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 /*
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  * SMP assumption: Options of CPU 0 are a superset of all processors.
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@@ -111,14 +126,36 @@
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 #define cpu_has_tx39_cache	__opt(MIPS_CPU_TX39_CACHE)
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 #endif
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 #ifndef cpu_has_octeon_cache
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-#define cpu_has_octeon_cache	0
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+#define cpu_has_octeon_cache						\
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+({									\
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+	int __res;							\
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+									\
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+	switch (boot_cpu_type()) {					\
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+	case CPU_CAVIUM_OCTEON:						\
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+	case CPU_CAVIUM_OCTEON_PLUS:					\
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+	case CPU_CAVIUM_OCTEON2:					\
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+	case CPU_CAVIUM_OCTEON3:					\
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+		__res = 1;						\
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+		break;							\
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+									\
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+	default:							\
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+		__res = 0;						\
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+	}								\
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+									\
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+	__res;								\
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+})
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 #endif
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 /* Don't override `cpu_has_fpu' to 1 or the "nofpu" option won't work.  */
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 #ifndef cpu_has_fpu
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-#define cpu_has_fpu		(current_cpu_data.options & MIPS_CPU_FPU)
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-#define raw_cpu_has_fpu		(raw_current_cpu_data.options & MIPS_CPU_FPU)
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+# ifdef CONFIG_MIPS_FP_SUPPORT
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+#  define cpu_has_fpu		(current_cpu_data.options & MIPS_CPU_FPU)
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+#  define raw_cpu_has_fpu	(raw_current_cpu_data.options & MIPS_CPU_FPU)
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+# else
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+#  define cpu_has_fpu		0
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+#  define raw_cpu_has_fpu	0
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+# endif
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 #else
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-#define raw_cpu_has_fpu		cpu_has_fpu
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+# define raw_cpu_has_fpu	cpu_has_fpu
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 #endif
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 #ifndef cpu_has_32fpr
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 #define cpu_has_32fpr		__isa_ge_or_opt(1, MIPS_CPU_32FPR)
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@@ -152,9 +189,6 @@
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 #endif
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 #ifndef cpu_has_llsc
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 #define cpu_has_llsc		__isa_ge_or_opt(1, MIPS_CPU_LLSC)
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-#endif
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-#ifndef cpu_has_bp_ghist
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-#define cpu_has_bp_ghist	__opt(MIPS_CPU_BP_GHIST)
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 #endif
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 #ifndef kernel_uses_llsc
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 #define kernel_uses_llsc	cpu_has_llsc
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@@ -195,7 +229,9 @@
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 #endif
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 #ifndef cpu_has_mmips
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-# ifdef CONFIG_SYS_SUPPORTS_MICROMIPS
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+# if defined(__mips_micromips)
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+#  define cpu_has_mmips		1
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+# elif defined(CONFIG_SYS_SUPPORTS_MICROMIPS)
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 #  define cpu_has_mmips		__opt(MIPS_CPU_MICROMIPS)
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 # else
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 #  define cpu_has_mmips		0
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@@ -223,9 +259,6 @@
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 #ifndef cpu_has_pindexed_dcache
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 #define cpu_has_pindexed_dcache	(cpu_data[0].dcache.flags & MIPS_CACHE_PINDEX)
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 #endif
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-#ifndef cpu_has_local_ebase
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-#define cpu_has_local_ebase	1
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-#endif
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 /*
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  * I-Cache snoops remote store.	 This only matters on SMP.  Some multiprocessors
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@@ -246,48 +279,47 @@
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 #endif
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 #endif
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-/* __builtin_constant_p(cpu_has_mips_r) && cpu_has_mips_r */
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-#if !((defined(cpu_has_mips32r1) && cpu_has_mips32r1) || \
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-	  (defined(cpu_has_mips32r2) && cpu_has_mips32r2) || \
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-	  (defined(cpu_has_mips32r6) && cpu_has_mips32r6) || \
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-	  (defined(cpu_has_mips64r1) && cpu_has_mips64r1) || \
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-	  (defined(cpu_has_mips64r2) && cpu_has_mips64r2) || \
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-	  (defined(cpu_has_mips64r6) && cpu_has_mips64r6))
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-#define CPU_NO_EFFICIENT_FFS 1
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-#endif
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-
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 #ifndef cpu_has_mips_1
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-# define cpu_has_mips_1		(!cpu_has_mips_r6)
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+# define cpu_has_mips_1		(MIPS_ISA_REV < 6)
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 #endif
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 #ifndef cpu_has_mips_2
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-# define cpu_has_mips_2		(cpu_data[0].isa_level & MIPS_CPU_ISA_II)
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+# define cpu_has_mips_2		__isa_lt_and_flag(6, MIPS_CPU_ISA_II)
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 #endif
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 #ifndef cpu_has_mips_3
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-# define cpu_has_mips_3		(cpu_data[0].isa_level & MIPS_CPU_ISA_III)
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+# define cpu_has_mips_3		__isa_lt_and_flag(6, MIPS_CPU_ISA_III)
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 #endif
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 #ifndef cpu_has_mips_4
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-# define cpu_has_mips_4		(cpu_data[0].isa_level & MIPS_CPU_ISA_IV)
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+# define cpu_has_mips_4		__isa_lt_and_flag(6, MIPS_CPU_ISA_IV)
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 #endif
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 #ifndef cpu_has_mips_5
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-# define cpu_has_mips_5		(cpu_data[0].isa_level & MIPS_CPU_ISA_V)
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+# define cpu_has_mips_5		__isa_lt_and_flag(6, MIPS_CPU_ISA_V)
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 #endif
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 #ifndef cpu_has_mips32r1
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-# define cpu_has_mips32r1	(cpu_data[0].isa_level & MIPS_CPU_ISA_M32R1)
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+# define cpu_has_mips32r1	__isa_range_or_flag(1, 6, MIPS_CPU_ISA_M32R1)
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 #endif
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 #ifndef cpu_has_mips32r2
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-# define cpu_has_mips32r2	(cpu_data[0].isa_level & MIPS_CPU_ISA_M32R2)
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+# define cpu_has_mips32r2	__isa_range_or_flag(2, 6, MIPS_CPU_ISA_M32R2)
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+#endif
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+#ifndef cpu_has_mips32r5
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+# define cpu_has_mips32r5	__isa_range_or_flag(5, 6, MIPS_CPU_ISA_M32R5)
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 #endif
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 #ifndef cpu_has_mips32r6
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-# define cpu_has_mips32r6	(cpu_data[0].isa_level & MIPS_CPU_ISA_M32R6)
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+# define cpu_has_mips32r6	__isa_ge_or_flag(6, MIPS_CPU_ISA_M32R6)
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 #endif
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 #ifndef cpu_has_mips64r1
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-# define cpu_has_mips64r1	(cpu_data[0].isa_level & MIPS_CPU_ISA_M64R1)
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+# define cpu_has_mips64r1	(cpu_has_64bits && \
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+				 __isa_range_or_flag(1, 6, MIPS_CPU_ISA_M64R1))
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 #endif
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 #ifndef cpu_has_mips64r2
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-# define cpu_has_mips64r2	(cpu_data[0].isa_level & MIPS_CPU_ISA_M64R2)
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+# define cpu_has_mips64r2	(cpu_has_64bits && \
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+				 __isa_range_or_flag(2, 6, MIPS_CPU_ISA_M64R2))
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+#endif
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+#ifndef cpu_has_mips64r5
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+# define cpu_has_mips64r5	(cpu_has_64bits && \
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+				 __isa_range_or_flag(5, 6, MIPS_CPU_ISA_M64R5))
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 #endif
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 #ifndef cpu_has_mips64r6
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-# define cpu_has_mips64r6	(cpu_data[0].isa_level & MIPS_CPU_ISA_M64R6)
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+# define cpu_has_mips64r6	__isa_ge_and_flag(6, MIPS_CPU_ISA_M64R6)
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 #endif
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 /*
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@@ -306,19 +338,25 @@
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 				(cpu_has_mips_3 | cpu_has_mips_4_5_64_r2_r6)
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 #define cpu_has_mips_4_5_64_r2_r6					\
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 				(cpu_has_mips_4_5 | cpu_has_mips64r1 |	\
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-				 cpu_has_mips_r2 | cpu_has_mips_r6)
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+				 cpu_has_mips_r2 | cpu_has_mips_r5 | \
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+				 cpu_has_mips_r6)
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-#define cpu_has_mips32	(cpu_has_mips32r1 | cpu_has_mips32r2 | cpu_has_mips32r6)
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-#define cpu_has_mips64	(cpu_has_mips64r1 | cpu_has_mips64r2 | cpu_has_mips64r6)
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+#define cpu_has_mips32	(cpu_has_mips32r1 | cpu_has_mips32r2 | \
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+			 cpu_has_mips32r5 | cpu_has_mips32r6)
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+#define cpu_has_mips64	(cpu_has_mips64r1 | cpu_has_mips64r2 | \
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+			 cpu_has_mips64r5 | cpu_has_mips64r6)
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 #define cpu_has_mips_r1 (cpu_has_mips32r1 | cpu_has_mips64r1)
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 #define cpu_has_mips_r2 (cpu_has_mips32r2 | cpu_has_mips64r2)
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+#define cpu_has_mips_r5	(cpu_has_mips32r5 | cpu_has_mips64r5)
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 #define cpu_has_mips_r6	(cpu_has_mips32r6 | cpu_has_mips64r6)
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 #define cpu_has_mips_r	(cpu_has_mips32r1 | cpu_has_mips32r2 | \
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-			 cpu_has_mips32r6 | cpu_has_mips64r1 | \
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-			 cpu_has_mips64r2 | cpu_has_mips64r6)
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+			 cpu_has_mips32r5 | cpu_has_mips32r6 | \
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+			 cpu_has_mips64r1 | cpu_has_mips64r2 | \
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+			 cpu_has_mips64r5 | cpu_has_mips64r6)
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-/* MIPSR2 and MIPSR6 have a lot of similarities */
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-#define cpu_has_mips_r2_r6	(cpu_has_mips_r2 | cpu_has_mips_r6)
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+/* MIPSR2 - MIPSR6 have a lot of similarities */
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+#define cpu_has_mips_r2_r6	(cpu_has_mips_r2 | cpu_has_mips_r5 | \
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+				 cpu_has_mips_r6)
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 /*
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  * cpu_has_mips_r2_exec_hazard - return if IHB is required on current processor
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@@ -332,7 +370,7 @@
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 ({									\
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 	int __res;							\
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 									\
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-	switch (current_cpu_type()) {					\
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+	switch (boot_cpu_type()) {					\
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 	case CPU_M14KC:							\
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 	case CPU_74K:							\
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 	case CPU_1074K:							\
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@@ -404,7 +442,7 @@
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 #endif
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 #ifndef cpu_has_mipsmt
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-#define cpu_has_mipsmt		__isa_lt_and_ase(6, MIPS_ASE_MIPSMT)
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+#define cpu_has_mipsmt		__isa_range_and_ase(2, 6, MIPS_ASE_MIPSMT)
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 #endif
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 #ifndef cpu_has_vp
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@@ -428,9 +466,6 @@
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 # ifndef cpu_has_64bit_gp_regs
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 # define cpu_has_64bit_gp_regs		0
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 # endif
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-# ifndef cpu_has_64bit_addresses
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-# define cpu_has_64bit_addresses	0
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-# endif
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 # ifndef cpu_vmbits
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 # define cpu_vmbits 31
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 # endif
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@@ -448,9 +483,6 @@
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 # endif
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 # ifndef cpu_has_64bit_gp_regs
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 # define cpu_has_64bit_gp_regs		1
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-# endif
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-# ifndef cpu_has_64bit_addresses
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-# define cpu_has_64bit_addresses	1
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 # endif
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 # ifndef cpu_vmbits
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 # define cpu_vmbits cpu_data[0].vmbits
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@@ -548,6 +580,18 @@
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 # define cpu_has_perf		__opt(MIPS_CPU_PERF)
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 #endif
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+#ifndef cpu_has_mac2008_only
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+# define cpu_has_mac2008_only	__opt(MIPS_CPU_MAC_2008_ONLY)
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+#endif
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+
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+#ifndef cpu_has_ftlbparex
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+# define cpu_has_ftlbparex	__opt(MIPS_CPU_FTLBPAREX)
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+#endif
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+
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+#ifndef cpu_has_gsexcex
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+# define cpu_has_gsexcex	__opt(MIPS_CPU_GSEXCEX)
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+#endif
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+
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 #ifdef CONFIG_SMP
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 /*
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  * Some systems share FTLB RAMs between threads within a core (siblings in
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@@ -597,6 +641,27 @@
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 #endif /* CONFIG_MIPS_MT_SMP */
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 /*
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+ * We only enable MMID support for configurations which natively support 64 bit
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+ * atomics because getting good performance from the allocator relies upon
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+ * efficient atomic64_*() functions.
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+ */
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+#ifndef cpu_has_mmid
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+# ifdef CONFIG_GENERIC_ATOMIC64
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+#  define cpu_has_mmid		0
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+# else
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+#  define cpu_has_mmid		__isa_ge_and_opt(6, MIPS_CPU_MMID)
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+# endif
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+#endif
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+
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+#ifndef cpu_has_mm_sysad
657
+# define cpu_has_mm_sysad	__opt(MIPS_CPU_MM_SYSAD)
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+#endif
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+
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+#ifndef cpu_has_mm_full
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+# define cpu_has_mm_full	__opt(MIPS_CPU_MM_FULL)
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+#endif
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+
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+/*
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  * Guest capabilities
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  */
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 #ifndef cpu_guest_has_conf1
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@@ -641,6 +706,9 @@
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 #ifndef cpu_guest_has_htw
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 #define cpu_guest_has_htw	(cpu_data[0].guest.options & MIPS_CPU_HTW)
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 #endif
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+#ifndef cpu_guest_has_ldpte
710
+#define cpu_guest_has_ldpte	(cpu_data[0].guest.options & MIPS_CPU_LDPTE)
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+#endif
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 #ifndef cpu_guest_has_mvh
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 #define cpu_guest_has_mvh	(cpu_data[0].guest.options & MIPS_CPU_MVH)
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 #endif