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12 | 12 | #include <linux/types.h> |
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13 | 13 | #include <linux/profile.h> |
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14 | 14 | |
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15 | | -#include <asm/machvec.h> |
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16 | 15 | #include <asm/ptrace.h> |
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17 | 16 | #include <asm/smp.h> |
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18 | 17 | |
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56 | 55 | extern int ia64_first_device_vector; |
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57 | 56 | extern int ia64_last_device_vector; |
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58 | 57 | |
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59 | | -#if defined(CONFIG_SMP) && (defined(CONFIG_IA64_GENERIC) || defined (CONFIG_IA64_DIG)) |
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| 58 | +#ifdef CONFIG_SMP |
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60 | 59 | /* Reserve the lower priority vector than device vectors for "move IRQ" IPI */ |
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61 | 60 | #define IA64_IRQ_MOVE_VECTOR 0x30 /* "move IRQ" IPI */ |
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62 | 61 | #define IA64_DEF_FIRST_DEVICE_VECTOR 0x31 |
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114 | 113 | #define ia64_register_ipi ia64_native_register_ipi |
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115 | 114 | #define assign_irq_vector ia64_native_assign_irq_vector |
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116 | 115 | #define free_irq_vector ia64_native_free_irq_vector |
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117 | | -#define register_percpu_irq ia64_native_register_percpu_irq |
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118 | 116 | #define ia64_resend_irq ia64_native_resend_irq |
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119 | 117 | |
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120 | 118 | extern void ia64_native_register_ipi(void); |
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124 | 122 | extern int reserve_irq_vector (int vector); |
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125 | 123 | extern void __setup_vector_irq(int cpu); |
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126 | 124 | extern void ia64_send_ipi (int cpu, int vector, int delivery_mode, int redirect); |
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127 | | -extern void ia64_native_register_percpu_irq (ia64_vector vec, struct irqaction *action); |
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128 | 125 | extern void destroy_and_reserve_irq (unsigned int irq); |
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129 | 126 | |
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130 | | -#if defined(CONFIG_SMP) && (defined(CONFIG_IA64_GENERIC) || defined(CONFIG_IA64_DIG)) |
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| 127 | +#ifdef CONFIG_SMP |
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131 | 128 | extern int irq_prepare_move(int irq, int cpu); |
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132 | 129 | extern void irq_complete_move(unsigned int irq); |
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133 | 130 | #else |
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137 | 134 | |
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138 | 135 | static inline void ia64_native_resend_irq(unsigned int vector) |
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139 | 136 | { |
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140 | | - platform_send_ipi(smp_processor_id(), vector, IA64_IPI_DM_INT, 0); |
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| 137 | + ia64_send_ipi(smp_processor_id(), vector, IA64_IPI_DM_INT, 0); |
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141 | 138 | } |
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142 | | - |
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143 | | -/* |
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144 | | - * Default implementations for the irq-descriptor API: |
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145 | | - */ |
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146 | | -#ifndef CONFIG_IA64_GENERIC |
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147 | | -static inline ia64_vector __ia64_irq_to_vector(int irq) |
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148 | | -{ |
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149 | | - return irq_cfg[irq].vector; |
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150 | | -} |
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151 | | - |
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152 | | -static inline unsigned int |
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153 | | -__ia64_local_vector_to_irq (ia64_vector vec) |
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154 | | -{ |
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155 | | - return __this_cpu_read(vector_irq[vec]); |
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156 | | -} |
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157 | | -#endif |
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158 | 139 | |
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159 | 140 | /* |
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160 | 141 | * Next follows the irq descriptor interface. On IA-64, each CPU supports 256 interrupt |
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.. | .. |
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170 | 151 | static inline ia64_vector |
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171 | 152 | irq_to_vector (int irq) |
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172 | 153 | { |
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173 | | - return platform_irq_to_vector(irq); |
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| 154 | + return irq_cfg[irq].vector; |
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174 | 155 | } |
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175 | 156 | |
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176 | 157 | /* |
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.. | .. |
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181 | 162 | static inline unsigned int |
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182 | 163 | local_vector_to_irq (ia64_vector vec) |
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183 | 164 | { |
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184 | | - return platform_local_vector_to_irq(vec); |
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| 165 | + return __this_cpu_read(vector_irq[vec]); |
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185 | 166 | } |
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186 | 167 | |
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187 | 168 | #endif /* _ASM_IA64_HW_IRQ_H */ |
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