change wifi driver to cypress

hc

2024-01-05 071106ecf68c401173c58808b1cf5f68cc50d390

 kernel/arch/arm64/include/asm/cache.h
..
..
@@ -1,22 +1,12 @@
1
+/* SPDX-License-Identifier: GPL-2.0-only */
1
2
 /*
2
3
  * Copyright (C) 2012 ARM Ltd.
3
- *
4
- * This program is free software; you can redistribute it and/or modify
5
- * it under the terms of the GNU General Public License version 2 as
6
- * published by the Free Software Foundation.
7
- *
8
- * This program is distributed in the hope that it will be useful,
9
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
10
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
11
- * GNU General Public License for more details.
12
- *
13
- * You should have received a copy of the GNU General Public License
14
- * along with this program.  If not, see <http://www.gnu.org/licenses/>.
15
4
  */
16
5
 #ifndef __ASM_CACHE_H
17
6
 #define __ASM_CACHE_H
18
7
 
19
8
 #include <asm/cputype.h>
9
+#include <asm/mte-def.h>
20
10
 
21
11
 #define CTR_L1IP_SHIFT		14
22
12
 #define CTR_L1IP_MASK		3
..
..
@@ -35,11 +25,21 @@
35
25
 #define CTR_L1IP(ctr)		(((ctr) >> CTR_L1IP_SHIFT) & CTR_L1IP_MASK)
36
26
 
37
27
 #define ICACHE_POLICY_VPIPT	0
28
+#define ICACHE_POLICY_RESERVED	1
38
29
 #define ICACHE_POLICY_VIPT	2
39
30
 #define ICACHE_POLICY_PIPT	3
40
31
 
41
32
 #define L1_CACHE_SHIFT		(6)
42
33
 #define L1_CACHE_BYTES		(1 << L1_CACHE_SHIFT)
34
+
35
+
36
+#define CLIDR_LOUU_SHIFT	27
37
+#define CLIDR_LOC_SHIFT		24
38
+#define CLIDR_LOUIS_SHIFT	21
39
+
40
+#define CLIDR_LOUU(clidr)	(((clidr) >> CLIDR_LOUU_SHIFT) & 0x7)
41
+#define CLIDR_LOC(clidr)	(((clidr) >> CLIDR_LOC_SHIFT) & 0x7)
42
+#define CLIDR_LOUIS(clidr)	(((clidr) >> CLIDR_LOUIS_SHIFT) & 0x7)
43
43
 
44
44
 /*
45
45
  * Memory returned by kmalloc() may be used for DMA, so we must make
..
..
@@ -50,13 +50,21 @@
50
50
  */
51
51
 #define ARCH_DMA_MINALIGN	(128)
52
52
 
53
-#ifdef CONFIG_KASAN_SW_TAGS
54
-#define ARCH_SLAB_MINALIGN	(1ULL << KASAN_SHADOW_SCALE_SHIFT)
55
-#endif
56
-
57
53
 #ifndef __ASSEMBLY__
58
54
 
59
55
 #include <linux/bitops.h>
56
+#include <linux/kasan-enabled.h>
57
+
58
+#ifdef CONFIG_KASAN_SW_TAGS
59
+#define ARCH_SLAB_MINALIGN	(1ULL << KASAN_SHADOW_SCALE_SHIFT)
60
+#elif defined(CONFIG_KASAN_HW_TAGS)
61
+static inline unsigned int arch_slab_minalign(void)
62
+{
63
+	return kasan_hw_tags_enabled() ? MTE_GRANULE_SIZE :
64
+					 __alignof__(unsigned long long);
65
+}
66
+#define arch_slab_minalign() arch_slab_minalign()
67
+#endif
60
68
 
61
69
 #define ICACHEF_ALIASING	0
62
70
 #define ICACHEF_VPIPT		1
..
..
@@ -71,7 +79,7 @@
71
79
 	return test_bit(ICACHEF_ALIASING, &__icache_flags);
72
80
 }
73
81
 
74
-static inline int icache_is_vpipt(void)
82
+static __always_inline int icache_is_vpipt(void)
75
83
 {
76
84
 	return test_bit(ICACHEF_VPIPT, &__icache_flags);
77
85
 }
..
..
@@ -81,14 +89,48 @@
81
89
 	return (read_cpuid_cachetype() >> CTR_CWG_SHIFT) & CTR_CWG_MASK;
82
90
 }
83
91
 
84
-#define __read_mostly __attribute__((__section__(".data..read_mostly")))
92
+#define __read_mostly __section(".data..read_mostly")
85
93
 
86
-static inline int cache_line_size(void)
94
+static inline int cache_line_size_of_cpu(void)
87
95
 {
88
96
 	u32 cwg = cache_type_cwg();
97
+
89
98
 	return cwg ? 4 << cwg : ARCH_DMA_MINALIGN;
90
99
 }
91
100
 
101
+int cache_line_size(void);
102
+
103
+/*
104
+ * Read the effective value of CTR_EL0.
105
+ *
106
+ * According to ARM ARM for ARMv8-A (ARM DDI 0487C.a),
107
+ * section D10.2.33 "CTR_EL0, Cache Type Register" :
108
+ *
109
+ * CTR_EL0.IDC reports the data cache clean requirements for
110
+ * instruction to data coherence.
111
+ *
112
+ *  0 - dcache clean to PoU is required unless :
113
+ *     (CLIDR_EL1.LoC == 0) || (CLIDR_EL1.LoUIS == 0 && CLIDR_EL1.LoUU == 0)
114
+ *  1 - dcache clean to PoU is not required for i-to-d coherence.
115
+ *
116
+ * This routine provides the CTR_EL0 with the IDC field updated to the
117
+ * effective state.
118
+ */
119
+static inline u32 __attribute_const__ read_cpuid_effective_cachetype(void)
120
+{
121
+	u32 ctr = read_cpuid_cachetype();
122
+
123
+	if (!(ctr & BIT(CTR_IDC_SHIFT))) {
124
+		u64 clidr = read_sysreg(clidr_el1);
125
+
126
+		if (CLIDR_LOC(clidr) == 0 ||
127
+		    (CLIDR_LOUIS(clidr) == 0 && CLIDR_LOUU(clidr) == 0))
128
+			ctr |= BIT(CTR_IDC_SHIFT);
129
+	}
130
+
131
+	return ctr;
132
+}
133
+
92
134
 #endif	/* __ASSEMBLY__ */
93
135
 
94
136
 #endif