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2024-01-05 071106ecf68c401173c58808b1cf5f68cc50d390 
 kernel/arch/arm64/boot/dts/ti/k3-am65-main.dtsi
....@@ -2,10 +2,31 @@
22 /*
33  * Device Tree Source for AM6 SoC Family Main Domain peripherals
44  *
5
- * Copyright (C) 2016-2018 Texas Instruments Incorporated - http://www.ti.com/
5
+ * Copyright (C) 2016-2018 Texas Instruments Incorporated - https://www.ti.com/
66  */
7
+#include <dt-bindings/phy/phy-am654-serdes.h>
78 
89 &cbass_main {
10
+	msmc_ram: sram@70000000 {
11
+		compatible = "mmio-sram";
12
+		reg = <0x0 0x70000000 0x0 0x200000>;
13
+		#address-cells = <1>;
14
+		#size-cells = <1>;
15
+		ranges = <0x0 0x0 0x70000000 0x200000>;
16
+
17
+		atf-sram@0 {
18
+			reg = <0x0 0x20000>;
19
+		};
20
+
21
+		sysfw-sram@f0000 {
22
+			reg = <0xf0000 0x10000>;
23
+		};
24
+
25
+		l3cache-sram@100000 {
26
+			reg = <0x100000 0x100000>;
27
+		};
28
+	};
29
+
930 	gic500: interrupt-controller@1800000 {
1031 		compatible = "arm,gic-v3";
1132 		#address-cells = <2>;
....@@ -14,18 +35,899 @@
1435 		#interrupt-cells = <3>;
1536 		interrupt-controller;
1637 		reg = <0x00 0x01800000 0x00 0x10000>,	/* GICD */
17
-		      <0x00 0x01880000 0x00 0x90000>;	/* GICR */
38
+		      <0x00 0x01880000 0x00 0x90000>,	/* GICR */
39
+		      <0x00 0x6f000000 0x00 0x2000>,	/* GICC */
40
+		      <0x00 0x6f010000 0x00 0x1000>,	/* GICH */
41
+		      <0x00 0x6f020000 0x00 0x2000>;	/* GICV */
1842 		/*
1943 		 * vcpumntirq:
2044 		 * virtual CPU interface maintenance interrupt
2145 		 */
2246 		interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;
2347 
24
-		gic_its: gic-its@1820000 {
48
+		gic_its: msi-controller@1820000 {
2549 			compatible = "arm,gic-v3-its";
2650 			reg = <0x00 0x01820000 0x00 0x10000>;
51
+			socionext,synquacer-pre-its = <0x1000000 0x400000>;
2752 			msi-controller;
2853 			#msi-cells = <1>;
2954 		};
3055 	};
56
+
57
+	serdes0: serdes@900000 {
58
+		compatible = "ti,phy-am654-serdes";
59
+		reg = <0x0 0x900000 0x0 0x2000>;
60
+		reg-names = "serdes";
61
+		#phy-cells = <2>;
62
+		power-domains = <&k3_pds 153 TI_SCI_PD_EXCLUSIVE>;
63
+		clocks = <&k3_clks 153 4>, <&k3_clks 153 1>, <&serdes1 AM654_SERDES_LO_REFCLK>;
64
+		clock-output-names = "serdes0_cmu_refclk", "serdes0_lo_refclk", "serdes0_ro_refclk";
65
+		assigned-clocks = <&k3_clks 153 4>, <&serdes0 AM654_SERDES_CMU_REFCLK>;
66
+		assigned-clock-parents = <&k3_clks 153 8>, <&k3_clks 153 4>;
67
+		ti,serdes-clk = <&serdes0_clk>;
68
+		#clock-cells = <1>;
69
+		mux-controls = <&serdes_mux 0>;
70
+	};
71
+
72
+	serdes1: serdes@910000 {
73
+		compatible = "ti,phy-am654-serdes";
74
+		reg = <0x0 0x910000 0x0 0x2000>;
75
+		reg-names = "serdes";
76
+		#phy-cells = <2>;
77
+		power-domains = <&k3_pds 154 TI_SCI_PD_EXCLUSIVE>;
78
+		clocks = <&serdes0 AM654_SERDES_RO_REFCLK>, <&k3_clks 154 1>, <&k3_clks 154 5>;
79
+		clock-output-names = "serdes1_cmu_refclk", "serdes1_lo_refclk", "serdes1_ro_refclk";
80
+		assigned-clocks = <&k3_clks 154 5>, <&serdes1 AM654_SERDES_CMU_REFCLK>;
81
+		assigned-clock-parents = <&k3_clks 154 9>, <&k3_clks 154 5>;
82
+		ti,serdes-clk = <&serdes1_clk>;
83
+		#clock-cells = <1>;
84
+		mux-controls = <&serdes_mux 1>;
85
+	};
86
+
87
+	main_uart0: serial@2800000 {
88
+		compatible = "ti,am654-uart";
89
+		reg = <0x00 0x02800000 0x00 0x100>;
90
+		reg-shift = <2>;
91
+		reg-io-width = <4>;
92
+		interrupts = <GIC_SPI 192 IRQ_TYPE_LEVEL_HIGH>;
93
+		clock-frequency = <48000000>;
94
+		current-speed = <115200>;
95
+		power-domains = <&k3_pds 146 TI_SCI_PD_EXCLUSIVE>;
96
+	};
97
+
98
+	main_uart1: serial@2810000 {
99
+		compatible = "ti,am654-uart";
100
+		reg = <0x00 0x02810000 0x00 0x100>;
101
+		reg-shift = <2>;
102
+		reg-io-width = <4>;
103
+		interrupts = <GIC_SPI 193 IRQ_TYPE_LEVEL_HIGH>;
104
+		clock-frequency = <48000000>;
105
+		power-domains = <&k3_pds 147 TI_SCI_PD_EXCLUSIVE>;
106
+	};
107
+
108
+	main_uart2: serial@2820000 {
109
+		compatible = "ti,am654-uart";
110
+		reg = <0x00 0x02820000 0x00 0x100>;
111
+		reg-shift = <2>;
112
+		reg-io-width = <4>;
113
+		interrupts = <GIC_SPI 194 IRQ_TYPE_LEVEL_HIGH>;
114
+		clock-frequency = <48000000>;
115
+		power-domains = <&k3_pds 148 TI_SCI_PD_EXCLUSIVE>;
116
+	};
117
+
118
+	crypto: crypto@4e00000 {
119
+		compatible = "ti,am654-sa2ul";
120
+		reg = <0x0 0x4e00000 0x0 0x1200>;
121
+		power-domains = <&k3_pds 136 TI_SCI_PD_EXCLUSIVE>;
122
+		#address-cells = <2>;
123
+		#size-cells = <2>;
124
+		ranges = <0x0 0x04e00000 0x00 0x04e00000 0x0 0x30000>;
125
+		status = "okay";
126
+
127
+		dmas = <&main_udmap 0xc000>, <&main_udmap 0x4000>,
128
+				<&main_udmap 0x4001>;
129
+		dma-names = "tx", "rx1", "rx2";
130
+
131
+		rng: rng@4e10000 {
132
+			compatible = "inside-secure,safexcel-eip76";
133
+			reg = <0x0 0x4e10000 0x0 0x7d>;
134
+			interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>;
135
+			clocks = <&k3_clks 136 1>;
136
+		};
137
+	};
138
+
139
+	main_pmx0: pinctrl@11c000 {
140
+		compatible = "pinctrl-single";
141
+		reg = <0x0 0x11c000 0x0 0x2e4>;
142
+		#pinctrl-cells = <1>;
143
+		pinctrl-single,register-width = <32>;
144
+		pinctrl-single,function-mask = <0xffffffff>;
145
+	};
146
+
147
+	main_pmx1: pinctrl@11c2e8 {
148
+		compatible = "pinctrl-single";
149
+		reg = <0x0 0x11c2e8 0x0 0x24>;
150
+		#pinctrl-cells = <1>;
151
+		pinctrl-single,register-width = <32>;
152
+		pinctrl-single,function-mask = <0xffffffff>;
153
+	};
154
+
155
+	main_i2c0: i2c@2000000 {
156
+		compatible = "ti,am654-i2c", "ti,omap4-i2c";
157
+		reg = <0x0 0x2000000 0x0 0x100>;
158
+		interrupts = <GIC_SPI 200 IRQ_TYPE_LEVEL_HIGH>;
159
+		#address-cells = <1>;
160
+		#size-cells = <0>;
161
+		clock-names = "fck";
162
+		clocks = <&k3_clks 110 1>;
163
+		power-domains = <&k3_pds 110 TI_SCI_PD_EXCLUSIVE>;
164
+	};
165
+
166
+	main_i2c1: i2c@2010000 {
167
+		compatible = "ti,am654-i2c", "ti,omap4-i2c";
168
+		reg = <0x0 0x2010000 0x0 0x100>;
169
+		interrupts = <GIC_SPI 201 IRQ_TYPE_LEVEL_HIGH>;
170
+		#address-cells = <1>;
171
+		#size-cells = <0>;
172
+		clock-names = "fck";
173
+		clocks = <&k3_clks 111 1>;
174
+		power-domains = <&k3_pds 111 TI_SCI_PD_EXCLUSIVE>;
175
+	};
176
+
177
+	main_i2c2: i2c@2020000 {
178
+		compatible = "ti,am654-i2c", "ti,omap4-i2c";
179
+		reg = <0x0 0x2020000 0x0 0x100>;
180
+		interrupts = <GIC_SPI 202 IRQ_TYPE_LEVEL_HIGH>;
181
+		#address-cells = <1>;
182
+		#size-cells = <0>;
183
+		clock-names = "fck";
184
+		clocks = <&k3_clks 112 1>;
185
+		power-domains = <&k3_pds 112 TI_SCI_PD_EXCLUSIVE>;
186
+	};
187
+
188
+	main_i2c3: i2c@2030000 {
189
+		compatible = "ti,am654-i2c", "ti,omap4-i2c";
190
+		reg = <0x0 0x2030000 0x0 0x100>;
191
+		interrupts = <GIC_SPI 203 IRQ_TYPE_LEVEL_HIGH>;
192
+		#address-cells = <1>;
193
+		#size-cells = <0>;
194
+		clock-names = "fck";
195
+		clocks = <&k3_clks 113 1>;
196
+		power-domains = <&k3_pds 113 TI_SCI_PD_EXCLUSIVE>;
197
+	};
198
+
199
+	ecap0: pwm@3100000 {
200
+		compatible = "ti,am654-ecap", "ti,am3352-ecap";
201
+		#pwm-cells = <3>;
202
+		reg = <0x0 0x03100000 0x0 0x60>;
203
+		power-domains = <&k3_pds 39 TI_SCI_PD_EXCLUSIVE>;
204
+		clocks = <&k3_clks 39 0>;
205
+		clock-names = "fck";
206
+	};
207
+
208
+	main_spi0: spi@2100000 {
209
+		compatible = "ti,am654-mcspi","ti,omap4-mcspi";
210
+		reg = <0x0 0x2100000 0x0 0x400>;
211
+		interrupts = <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>;
212
+		clocks = <&k3_clks 137 1>;
213
+		power-domains = <&k3_pds 137 TI_SCI_PD_EXCLUSIVE>;
214
+		#address-cells = <1>;
215
+		#size-cells = <0>;
216
+		dmas = <&main_udmap 0xc500>, <&main_udmap 0x4500>;
217
+		dma-names = "tx0", "rx0";
218
+	};
219
+
220
+	main_spi1: spi@2110000 {
221
+		compatible = "ti,am654-mcspi","ti,omap4-mcspi";
222
+		reg = <0x0 0x2110000 0x0 0x400>;
223
+		interrupts = <GIC_SPI 185 IRQ_TYPE_LEVEL_HIGH>;
224
+		clocks = <&k3_clks 138 1>;
225
+		power-domains = <&k3_pds 138 TI_SCI_PD_EXCLUSIVE>;
226
+		#address-cells = <1>;
227
+		#size-cells = <0>;
228
+		assigned-clocks = <&k3_clks 137 1>;
229
+		assigned-clock-rates = <48000000>;
230
+	};
231
+
232
+	main_spi2: spi@2120000 {
233
+		compatible = "ti,am654-mcspi","ti,omap4-mcspi";
234
+		reg = <0x0 0x2120000 0x0 0x400>;
235
+		interrupts = <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>;
236
+		clocks = <&k3_clks 139 1>;
237
+		power-domains = <&k3_pds 139 TI_SCI_PD_EXCLUSIVE>;
238
+		#address-cells = <1>;
239
+		#size-cells = <0>;
240
+	};
241
+
242
+	main_spi3: spi@2130000 {
243
+		compatible = "ti,am654-mcspi","ti,omap4-mcspi";
244
+		reg = <0x0 0x2130000 0x0 0x400>;
245
+		interrupts = <GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>;
246
+		clocks = <&k3_clks 140 1>;
247
+		power-domains = <&k3_pds 140 TI_SCI_PD_EXCLUSIVE>;
248
+		#address-cells = <1>;
249
+		#size-cells = <0>;
250
+	};
251
+
252
+	main_spi4: spi@2140000 {
253
+		compatible = "ti,am654-mcspi","ti,omap4-mcspi";
254
+		reg = <0x0 0x2140000 0x0 0x400>;
255
+		interrupts = <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>;
256
+		clocks = <&k3_clks 141 1>;
257
+		power-domains = <&k3_pds 141 TI_SCI_PD_EXCLUSIVE>;
258
+		#address-cells = <1>;
259
+		#size-cells = <0>;
260
+	};
261
+
262
+	sdhci0: sdhci@4f80000 {
263
+		compatible = "ti,am654-sdhci-5.1";
264
+		reg = <0x0 0x4f80000 0x0 0x260>, <0x0 0x4f90000 0x0 0x134>;
265
+		power-domains = <&k3_pds 47 TI_SCI_PD_EXCLUSIVE>;
266
+		clocks = <&k3_clks 47 0>, <&k3_clks 47 1>;
267
+		clock-names = "clk_ahb", "clk_xin";
268
+		interrupts = <GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>;
269
+		mmc-ddr-1_8v;
270
+		mmc-hs200-1_8v;
271
+		ti,otap-del-sel-legacy = <0x0>;
272
+		ti,otap-del-sel-mmc-hs = <0x0>;
273
+		ti,otap-del-sel-sd-hs = <0x0>;
274
+		ti,otap-del-sel-sdr12 = <0x0>;
275
+		ti,otap-del-sel-sdr25 = <0x0>;
276
+		ti,otap-del-sel-sdr50 = <0x8>;
277
+		ti,otap-del-sel-sdr104 = <0x7>;
278
+		ti,otap-del-sel-ddr50 = <0x5>;
279
+		ti,otap-del-sel-ddr52 = <0x5>;
280
+		ti,otap-del-sel-hs200 = <0x5>;
281
+		ti,otap-del-sel-hs400 = <0x0>;
282
+		ti,trm-icp = <0x8>;
283
+		dma-coherent;
284
+	};
285
+
286
+	sdhci1: sdhci@4fa0000 {
287
+		compatible = "ti,am654-sdhci-5.1";
288
+		reg = <0x0 0x4fa0000 0x0 0x260>, <0x0 0x4fb0000 0x0 0x134>;
289
+		power-domains = <&k3_pds 48 TI_SCI_PD_EXCLUSIVE>;
290
+		clocks = <&k3_clks 48 0>, <&k3_clks 48 1>;
291
+		clock-names = "clk_ahb", "clk_xin";
292
+		interrupts = <GIC_SPI 137 IRQ_TYPE_LEVEL_HIGH>;
293
+		ti,otap-del-sel-legacy = <0x0>;
294
+		ti,otap-del-sel-mmc-hs = <0x0>;
295
+		ti,otap-del-sel-sd-hs = <0x0>;
296
+		ti,otap-del-sel-sdr12 = <0x0>;
297
+		ti,otap-del-sel-sdr25 = <0x0>;
298
+		ti,otap-del-sel-sdr50 = <0x8>;
299
+		ti,otap-del-sel-sdr104 = <0x7>;
300
+		ti,otap-del-sel-ddr50 = <0x4>;
301
+		ti,otap-del-sel-ddr52 = <0x4>;
302
+		ti,otap-del-sel-hs200 = <0x7>;
303
+		ti,clkbuf-sel = <0x7>;
304
+		ti,otap-del-sel = <0x2>;
305
+		ti,trm-icp = <0x8>;
306
+		dma-coherent;
307
+		no-1-8-v;
308
+	};
309
+
310
+	scm_conf: scm-conf@100000 {
311
+		compatible = "syscon", "simple-mfd";
312
+		reg = <0 0x00100000 0 0x1c000>;
313
+		#address-cells = <1>;
314
+		#size-cells = <1>;
315
+		ranges = <0x0 0x0 0x00100000 0x1c000>;
316
+
317
+		pcie0_mode: pcie-mode@4060 {
318
+			compatible = "syscon";
319
+			reg = <0x00004060 0x4>;
320
+		};
321
+
322
+		pcie1_mode: pcie-mode@4070 {
323
+			compatible = "syscon";
324
+			reg = <0x00004070 0x4>;
325
+		};
326
+
327
+		pcie_devid: pcie-devid@210 {
328
+			compatible = "syscon";
329
+			reg = <0x00000210 0x4>;
330
+		};
331
+
332
+		serdes0_clk: clock@4080 {
333
+			compatible = "syscon";
334
+			reg = <0x00004080 0x4>;
335
+		};
336
+
337
+		serdes1_clk: clock@4090 {
338
+			compatible = "syscon";
339
+			reg = <0x00004090 0x4>;
340
+		};
341
+
342
+		serdes_mux: mux-controller {
343
+			compatible = "mmio-mux";
344
+			#mux-control-cells = <1>;
345
+			mux-reg-masks = <0x4080 0x3>, /* SERDES0 lane select */
346
+					<0x4090 0x3>; /* SERDES1 lane select */
347
+		};
348
+
349
+		dss_oldi_io_ctrl: dss-oldi-io-ctrl@41e0 {
350
+			compatible = "syscon";
351
+			reg = <0x0000041e0 0x14>;
352
+		};
353
+
354
+		ehrpwm_tbclk: clock@4140 {
355
+			compatible = "ti,am654-ehrpwm-tbclk", "syscon";
356
+			reg = <0x4140 0x18>;
357
+			#clock-cells = <1>;
358
+		};
359
+	};
360
+
361
+	dwc3_0: dwc3@4000000 {
362
+		compatible = "ti,am654-dwc3";
363
+		reg = <0x0 0x4000000 0x0 0x4000>;
364
+		#address-cells = <1>;
365
+		#size-cells = <1>;
366
+		ranges = <0x0 0x0 0x4000000 0x20000>;
367
+		interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>;
368
+		dma-coherent;
369
+		power-domains = <&k3_pds 151 TI_SCI_PD_EXCLUSIVE>;
370
+		clocks = <&k3_clks 151 2>, <&k3_clks 151 7>;
371
+		assigned-clocks = <&k3_clks 151 2>, <&k3_clks 151 7>;
372
+		assigned-clock-parents = <&k3_clks 151 4>,	/* set REF_CLK to 20MHz i.e. PER0_PLL/48 */
373
+					 <&k3_clks 151 9>;	/* set PIPE3_TXB_CLK to CLK_12M_RC/256 (for HS only) */
374
+
375
+		usb0: usb@10000 {
376
+			compatible = "snps,dwc3";
377
+			reg = <0x10000 0x10000>;
378
+			interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>,
379
+				     <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>,
380
+				     <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>;
381
+			interrupt-names = "peripheral",
382
+					  "host",
383
+					  "otg";
384
+			maximum-speed = "high-speed";
385
+			dr_mode = "otg";
386
+			phys = <&usb0_phy>;
387
+			phy-names = "usb2-phy";
388
+			snps,dis_u3_susphy_quirk;
389
+		};
390
+	};
391
+
392
+	usb0_phy: phy@4100000 {
393
+		compatible = "ti,am654-usb2", "ti,omap-usb2";
394
+		reg = <0x0 0x4100000 0x0 0x54>;
395
+		syscon-phy-power = <&scm_conf 0x4000>;
396
+		clocks = <&k3_clks 151 0>, <&k3_clks 151 1>;
397
+		clock-names = "wkupclk", "refclk";
398
+		#phy-cells = <0>;
399
+	};
400
+
401
+	dwc3_1: dwc3@4020000 {
402
+		compatible = "ti,am654-dwc3";
403
+		reg = <0x0 0x4020000 0x0 0x4000>;
404
+		#address-cells = <1>;
405
+		#size-cells = <1>;
406
+		ranges = <0x0 0x0 0x4020000 0x20000>;
407
+		interrupts = <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>;
408
+		dma-coherent;
409
+		power-domains = <&k3_pds 152 TI_SCI_PD_EXCLUSIVE>;
410
+		clocks = <&k3_clks 152 2>;
411
+		assigned-clocks = <&k3_clks 152 2>;
412
+		assigned-clock-parents = <&k3_clks 152 4>;	/* set REF_CLK to 20MHz i.e. PER0_PLL/48 */
413
+
414
+		usb1: usb@10000 {
415
+			compatible = "snps,dwc3";
416
+			reg = <0x10000 0x10000>;
417
+			interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>,
418
+				     <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>,
419
+				     <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>;
420
+			interrupt-names = "peripheral",
421
+					  "host",
422
+					  "otg";
423
+			maximum-speed = "high-speed";
424
+			dr_mode = "otg";
425
+			phys = <&usb1_phy>;
426
+			phy-names = "usb2-phy";
427
+		};
428
+	};
429
+
430
+	usb1_phy: phy@4110000 {
431
+		compatible = "ti,am654-usb2", "ti,omap-usb2";
432
+		reg = <0x0 0x4110000 0x0 0x54>;
433
+		syscon-phy-power = <&scm_conf 0x4020>;
434
+		clocks = <&k3_clks 152 0>, <&k3_clks 152 1>;
435
+		clock-names = "wkupclk", "refclk";
436
+		#phy-cells = <0>;
437
+	};
438
+
439
+	intr_main_gpio: interrupt-controller0 {
440
+		compatible = "ti,sci-intr";
441
+		ti,intr-trigger-type = <1>;
442
+		interrupt-controller;
443
+		interrupt-parent = <&gic500>;
444
+		#interrupt-cells = <1>;
445
+		ti,sci = <&dmsc>;
446
+		ti,sci-dev-id = <100>;
447
+		ti,interrupt-ranges = <0 392 32>;
448
+	};
449
+
450
+	main-navss {
451
+		compatible = "simple-mfd";
452
+		#address-cells = <2>;
453
+		#size-cells = <2>;
454
+		ranges;
455
+		dma-coherent;
456
+		dma-ranges;
457
+
458
+		ti,sci-dev-id = <118>;
459
+
460
+		intr_main_navss: interrupt-controller1 {
461
+			compatible = "ti,sci-intr";
462
+			ti,intr-trigger-type = <4>;
463
+			interrupt-controller;
464
+			interrupt-parent = <&gic500>;
465
+			#interrupt-cells = <1>;
466
+			ti,sci = <&dmsc>;
467
+			ti,sci-dev-id = <182>;
468
+			ti,interrupt-ranges = <0 64 64>,
469
+					      <64 448 64>;
470
+		};
471
+
472
+		inta_main_udmass: interrupt-controller@33d00000 {
473
+			compatible = "ti,sci-inta";
474
+			reg = <0x0 0x33d00000 0x0 0x100000>;
475
+			interrupt-controller;
476
+			interrupt-parent = <&intr_main_navss>;
477
+			msi-controller;
478
+			ti,sci = <&dmsc>;
479
+			ti,sci-dev-id = <179>;
480
+			ti,interrupt-ranges = <0 0 256>;
481
+		};
482
+
483
+		secure_proxy_main: mailbox@32c00000 {
484
+			compatible = "ti,am654-secure-proxy";
485
+			#mbox-cells = <1>;
486
+			reg-names = "target_data", "rt", "scfg";
487
+			reg = <0x00 0x32c00000 0x00 0x100000>,
488
+			      <0x00 0x32400000 0x00 0x100000>,
489
+			      <0x00 0x32800000 0x00 0x100000>;
490
+			interrupt-names = "rx_011";
491
+			interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
492
+		};
493
+
494
+		hwspinlock: spinlock@30e00000 {
495
+			compatible = "ti,am654-hwspinlock";
496
+			reg = <0x00 0x30e00000 0x00 0x1000>;
497
+			#hwlock-cells = <1>;
498
+		};
499
+
500
+		mailbox0_cluster0: mailbox@31f80000 {
501
+			compatible = "ti,am654-mailbox";
502
+			reg = <0x00 0x31f80000 0x00 0x200>;
503
+			#mbox-cells = <1>;
504
+			ti,mbox-num-users = <4>;
505
+			ti,mbox-num-fifos = <16>;
506
+			interrupt-parent = <&intr_main_navss>;
507
+		};
508
+
509
+		mailbox0_cluster1: mailbox@31f81000 {
510
+			compatible = "ti,am654-mailbox";
511
+			reg = <0x00 0x31f81000 0x00 0x200>;
512
+			#mbox-cells = <1>;
513
+			ti,mbox-num-users = <4>;
514
+			ti,mbox-num-fifos = <16>;
515
+			interrupt-parent = <&intr_main_navss>;
516
+		};
517
+
518
+		mailbox0_cluster2: mailbox@31f82000 {
519
+			compatible = "ti,am654-mailbox";
520
+			reg = <0x00 0x31f82000 0x00 0x200>;
521
+			#mbox-cells = <1>;
522
+			ti,mbox-num-users = <4>;
523
+			ti,mbox-num-fifos = <16>;
524
+			interrupt-parent = <&intr_main_navss>;
525
+		};
526
+
527
+		mailbox0_cluster3: mailbox@31f83000 {
528
+			compatible = "ti,am654-mailbox";
529
+			reg = <0x00 0x31f83000 0x00 0x200>;
530
+			#mbox-cells = <1>;
531
+			ti,mbox-num-users = <4>;
532
+			ti,mbox-num-fifos = <16>;
533
+			interrupt-parent = <&intr_main_navss>;
534
+		};
535
+
536
+		mailbox0_cluster4: mailbox@31f84000 {
537
+			compatible = "ti,am654-mailbox";
538
+			reg = <0x00 0x31f84000 0x00 0x200>;
539
+			#mbox-cells = <1>;
540
+			ti,mbox-num-users = <4>;
541
+			ti,mbox-num-fifos = <16>;
542
+			interrupt-parent = <&intr_main_navss>;
543
+		};
544
+
545
+		mailbox0_cluster5: mailbox@31f85000 {
546
+			compatible = "ti,am654-mailbox";
547
+			reg = <0x00 0x31f85000 0x00 0x200>;
548
+			#mbox-cells = <1>;
549
+			ti,mbox-num-users = <4>;
550
+			ti,mbox-num-fifos = <16>;
551
+			interrupt-parent = <&intr_main_navss>;
552
+		};
553
+
554
+		mailbox0_cluster6: mailbox@31f86000 {
555
+			compatible = "ti,am654-mailbox";
556
+			reg = <0x00 0x31f86000 0x00 0x200>;
557
+			#mbox-cells = <1>;
558
+			ti,mbox-num-users = <4>;
559
+			ti,mbox-num-fifos = <16>;
560
+			interrupt-parent = <&intr_main_navss>;
561
+		};
562
+
563
+		mailbox0_cluster7: mailbox@31f87000 {
564
+			compatible = "ti,am654-mailbox";
565
+			reg = <0x00 0x31f87000 0x00 0x200>;
566
+			#mbox-cells = <1>;
567
+			ti,mbox-num-users = <4>;
568
+			ti,mbox-num-fifos = <16>;
569
+			interrupt-parent = <&intr_main_navss>;
570
+		};
571
+
572
+		mailbox0_cluster8: mailbox@31f88000 {
573
+			compatible = "ti,am654-mailbox";
574
+			reg = <0x00 0x31f88000 0x00 0x200>;
575
+			#mbox-cells = <1>;
576
+			ti,mbox-num-users = <4>;
577
+			ti,mbox-num-fifos = <16>;
578
+			interrupt-parent = <&intr_main_navss>;
579
+		};
580
+
581
+		mailbox0_cluster9: mailbox@31f89000 {
582
+			compatible = "ti,am654-mailbox";
583
+			reg = <0x00 0x31f89000 0x00 0x200>;
584
+			#mbox-cells = <1>;
585
+			ti,mbox-num-users = <4>;
586
+			ti,mbox-num-fifos = <16>;
587
+			interrupt-parent = <&intr_main_navss>;
588
+		};
589
+
590
+		mailbox0_cluster10: mailbox@31f8a000 {
591
+			compatible = "ti,am654-mailbox";
592
+			reg = <0x00 0x31f8a000 0x00 0x200>;
593
+			#mbox-cells = <1>;
594
+			ti,mbox-num-users = <4>;
595
+			ti,mbox-num-fifos = <16>;
596
+			interrupt-parent = <&intr_main_navss>;
597
+		};
598
+
599
+		mailbox0_cluster11: mailbox@31f8b000 {
600
+			compatible = "ti,am654-mailbox";
601
+			reg = <0x00 0x31f8b000 0x00 0x200>;
602
+			#mbox-cells = <1>;
603
+			ti,mbox-num-users = <4>;
604
+			ti,mbox-num-fifos = <16>;
605
+			interrupt-parent = <&intr_main_navss>;
606
+		};
607
+
608
+		ringacc: ringacc@3c000000 {
609
+			compatible = "ti,am654-navss-ringacc";
610
+			reg =	<0x0 0x3c000000 0x0 0x400000>,
611
+				<0x0 0x38000000 0x0 0x400000>,
612
+				<0x0 0x31120000 0x0 0x100>,
613
+				<0x0 0x33000000 0x0 0x40000>;
614
+			reg-names = "rt", "fifos", "proxy_gcfg", "proxy_target";
615
+			ti,num-rings = <818>;
616
+			ti,sci-rm-range-gp-rings = <0x1>; /* GP ring range */
617
+			ti,dma-ring-reset-quirk;
618
+			ti,sci = <&dmsc>;
619
+			ti,sci-dev-id = <187>;
620
+			msi-parent = <&inta_main_udmass>;
621
+		};
622
+
623
+		main_udmap: dma-controller@31150000 {
624
+			compatible = "ti,am654-navss-main-udmap";
625
+			reg =	<0x0 0x31150000 0x0 0x100>,
626
+				<0x0 0x34000000 0x0 0x100000>,
627
+				<0x0 0x35000000 0x0 0x100000>;
628
+			reg-names = "gcfg", "rchanrt", "tchanrt";
629
+			msi-parent = <&inta_main_udmass>;
630
+			#dma-cells = <1>;
631
+
632
+			ti,sci = <&dmsc>;
633
+			ti,sci-dev-id = <188>;
634
+			ti,ringacc = <&ringacc>;
635
+
636
+			ti,sci-rm-range-tchan = <0xf>, /* TX_HCHAN */
637
+						<0xd>; /* TX_CHAN */
638
+			ti,sci-rm-range-rchan = <0xb>, /* RX_HCHAN */
639
+						<0xa>; /* RX_CHAN */
640
+			ti,sci-rm-range-rflow = <0x0>; /* GP RFLOW */
641
+		};
642
+
643
+		cpts@310d0000 {
644
+			compatible = "ti,am65-cpts";
645
+			reg = <0x0 0x310d0000 0x0 0x400>;
646
+			reg-names = "cpts";
647
+			clocks = <&main_cpts_mux>;
648
+			clock-names = "cpts";
649
+			interrupts-extended = <&intr_main_navss 391>;
650
+			interrupt-names = "cpts";
651
+			ti,cpts-periodic-outputs = <6>;
652
+			ti,cpts-ext-ts-inputs = <8>;
653
+
654
+			main_cpts_mux: refclk-mux {
655
+				#clock-cells = <0>;
656
+				clocks = <&k3_clks 118 5>, <&k3_clks 118 11>,
657
+					<&k3_clks 118 6>, <&k3_clks 118 3>,
658
+					<&k3_clks 118 8>, <&k3_clks 118 14>,
659
+					<&k3_clks 120 3>, <&k3_clks 121 3>;
660
+				assigned-clocks = <&main_cpts_mux>;
661
+				assigned-clock-parents = <&k3_clks 118 5>;
662
+			};
663
+		};
664
+	};
665
+
666
+	main_gpio0: gpio@600000 {
667
+		compatible = "ti,am654-gpio", "ti,keystone-gpio";
668
+		reg = <0x0 0x600000 0x0 0x100>;
669
+		gpio-controller;
670
+		#gpio-cells = <2>;
671
+		interrupt-parent = <&intr_main_gpio>;
672
+		interrupts = <192>, <193>, <194>, <195>, <196>, <197>;
673
+		interrupt-controller;
674
+		#interrupt-cells = <2>;
675
+		ti,ngpio = <96>;
676
+		ti,davinci-gpio-unbanked = <0>;
677
+		clocks = <&k3_clks 57 0>;
678
+		clock-names = "gpio";
679
+	};
680
+
681
+	main_gpio1: gpio@601000 {
682
+		compatible = "ti,am654-gpio", "ti,keystone-gpio";
683
+		reg = <0x0 0x601000 0x0 0x100>;
684
+		gpio-controller;
685
+		#gpio-cells = <2>;
686
+		interrupt-parent = <&intr_main_gpio>;
687
+		interrupts = <200>, <201>, <202>, <203>, <204>, <205>;
688
+		interrupt-controller;
689
+		#interrupt-cells = <2>;
690
+		ti,ngpio = <90>;
691
+		ti,davinci-gpio-unbanked = <0>;
692
+		clocks = <&k3_clks 58 0>;
693
+		clock-names = "gpio";
694
+	};
695
+
696
+	pcie0_rc: pcie@5500000 {
697
+		compatible = "ti,am654-pcie-rc";
698
+		reg =  <0x0 0x5500000 0x0 0x1000>, <0x0 0x5501000 0x0 0x1000>, <0x0 0x10000000 0x0 0x2000>, <0x0 0x5506000 0x0 0x1000>;
699
+		reg-names = "app", "dbics", "config", "atu";
700
+		power-domains = <&k3_pds 120 TI_SCI_PD_EXCLUSIVE>;
701
+		#address-cells = <3>;
702
+		#size-cells = <2>;
703
+		ranges = <0x81000000 0 0          0x0 0x10020000 0 0x00010000
704
+			  0x82000000 0 0x10030000 0x0 0x10030000 0 0x07FD0000>;
705
+		ti,syscon-pcie-id = <&pcie_devid>;
706
+		ti,syscon-pcie-mode = <&pcie0_mode>;
707
+		bus-range = <0x0 0xff>;
708
+		num-viewport = <16>;
709
+		max-link-speed = <2>;
710
+		dma-coherent;
711
+		interrupts = <GIC_SPI 340 IRQ_TYPE_EDGE_RISING>;
712
+		msi-map = <0x0 &gic_its 0x0 0x10000>;
713
+	};
714
+
715
+	pcie0_ep: pcie-ep@5500000 {
716
+		compatible = "ti,am654-pcie-ep";
717
+		reg =  <0x0 0x5500000 0x0 0x1000>, <0x0 0x5501000 0x0 0x1000>, <0x0 0x10000000 0x0 0x8000000>, <0x0 0x5506000 0x0 0x1000>;
718
+		reg-names = "app", "dbics", "addr_space", "atu";
719
+		power-domains = <&k3_pds 120 TI_SCI_PD_EXCLUSIVE>;
720
+		ti,syscon-pcie-mode = <&pcie0_mode>;
721
+		num-ib-windows = <16>;
722
+		num-ob-windows = <16>;
723
+		max-link-speed = <2>;
724
+		dma-coherent;
725
+		interrupts = <GIC_SPI 340 IRQ_TYPE_EDGE_RISING>;
726
+	};
727
+
728
+	pcie1_rc: pcie@5600000 {
729
+		compatible = "ti,am654-pcie-rc";
730
+		reg =  <0x0 0x5600000 0x0 0x1000>, <0x0 0x5601000 0x0 0x1000>, <0x0 0x18000000 0x0 0x2000>, <0x0 0x5606000 0x0 0x1000>;
731
+		reg-names = "app", "dbics", "config", "atu";
732
+		power-domains = <&k3_pds 121 TI_SCI_PD_EXCLUSIVE>;
733
+		#address-cells = <3>;
734
+		#size-cells = <2>;
735
+		ranges = <0x81000000 0 0          0x0   0x18020000 0 0x00010000
736
+			  0x82000000 0 0x18030000 0x0   0x18030000 0 0x07FD0000>;
737
+		ti,syscon-pcie-id = <&pcie_devid>;
738
+		ti,syscon-pcie-mode = <&pcie1_mode>;
739
+		bus-range = <0x0 0xff>;
740
+		num-viewport = <16>;
741
+		max-link-speed = <2>;
742
+		dma-coherent;
743
+		interrupts = <GIC_SPI 355 IRQ_TYPE_EDGE_RISING>;
744
+		msi-map = <0x0 &gic_its 0x10000 0x10000>;
745
+	};
746
+
747
+	pcie1_ep: pcie-ep@5600000 {
748
+		compatible = "ti,am654-pcie-ep";
749
+		reg =  <0x0 0x5600000 0x0 0x1000>, <0x0 0x5601000 0x0 0x1000>, <0x0 0x18000000 0x0 0x4000000>, <0x0 0x5606000 0x0 0x1000>;
750
+		reg-names = "app", "dbics", "addr_space", "atu";
751
+		power-domains = <&k3_pds 121 TI_SCI_PD_EXCLUSIVE>;
752
+		ti,syscon-pcie-mode = <&pcie1_mode>;
753
+		num-ib-windows = <16>;
754
+		num-ob-windows = <16>;
755
+		max-link-speed = <2>;
756
+		dma-coherent;
757
+		interrupts = <GIC_SPI 355 IRQ_TYPE_EDGE_RISING>;
758
+	};
759
+
760
+	mcasp0: mcasp@2b00000 {
761
+		compatible = "ti,am33xx-mcasp-audio";
762
+		reg = <0x0 0x02b00000 0x0 0x2000>,
763
+			<0x0 0x02b08000 0x0 0x1000>;
764
+		reg-names = "mpu","dat";
765
+		interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>,
766
+				<GIC_SPI 209 IRQ_TYPE_LEVEL_HIGH>;
767
+		interrupt-names = "tx", "rx";
768
+
769
+		dmas = <&main_udmap 0xc400>, <&main_udmap 0x4400>;
770
+		dma-names = "tx", "rx";
771
+
772
+		clocks = <&k3_clks 104 0>;
773
+		clock-names = "fck";
774
+		power-domains = <&k3_pds 104 TI_SCI_PD_EXCLUSIVE>;
775
+
776
+		status = "disabled";
777
+	};
778
+
779
+	mcasp1: mcasp@2b10000 {
780
+		compatible = "ti,am33xx-mcasp-audio";
781
+		reg = <0x0 0x02b10000 0x0 0x2000>,
782
+			<0x0 0x02b18000 0x0 0x1000>;
783
+		reg-names = "mpu","dat";
784
+		interrupts = <GIC_SPI 210 IRQ_TYPE_LEVEL_HIGH>,
785
+				<GIC_SPI 211 IRQ_TYPE_LEVEL_HIGH>;
786
+		interrupt-names = "tx", "rx";
787
+
788
+		dmas = <&main_udmap 0xc401>, <&main_udmap 0x4401>;
789
+		dma-names = "tx", "rx";
790
+
791
+		clocks = <&k3_clks 105 0>;
792
+		clock-names = "fck";
793
+		power-domains = <&k3_pds 105 TI_SCI_PD_EXCLUSIVE>;
794
+
795
+		status = "disabled";
796
+	};
797
+
798
+	mcasp2: mcasp@2b20000 {
799
+		compatible = "ti,am33xx-mcasp-audio";
800
+		reg = <0x0 0x02b20000 0x0 0x2000>,
801
+			<0x0 0x02b28000 0x0 0x1000>;
802
+		reg-names = "mpu","dat";
803
+		interrupts = <GIC_SPI 212 IRQ_TYPE_LEVEL_HIGH>,
804
+				<GIC_SPI 213 IRQ_TYPE_LEVEL_HIGH>;
805
+		interrupt-names = "tx", "rx";
806
+
807
+		dmas = <&main_udmap 0xc402>, <&main_udmap 0x4402>;
808
+		dma-names = "tx", "rx";
809
+
810
+		clocks = <&k3_clks 106 0>;
811
+		clock-names = "fck";
812
+		power-domains = <&k3_pds 106 TI_SCI_PD_EXCLUSIVE>;
813
+
814
+		status = "disabled";
815
+	};
816
+
817
+	cal: cal@6f03000 {
818
+		compatible = "ti,am654-cal";
819
+		reg = <0x0 0x06f03000 0x0 0x400>,
820
+		      <0x0 0x06f03800 0x0 0x40>;
821
+		reg-names = "cal_top",
822
+			    "cal_rx_core0";
823
+		interrupts = <GIC_SPI 152 IRQ_TYPE_LEVEL_HIGH>;
824
+		ti,camerrx-control = <&scm_conf 0x40c0>;
825
+		clock-names = "fck";
826
+		clocks = <&k3_clks 2 0>;
827
+		power-domains = <&k3_pds 2 TI_SCI_PD_EXCLUSIVE>;
828
+
829
+		ports {
830
+			#address-cells = <1>;
831
+			#size-cells = <0>;
832
+
833
+			csi2_0: port@0 {
834
+				reg = <0>;
835
+			};
836
+		};
837
+	};
838
+
839
+	dss: dss@4a00000 {
840
+		compatible = "ti,am65x-dss";
841
+		reg =	<0x0 0x04a00000 0x0 0x1000>, /* common */
842
+			<0x0 0x04a02000 0x0 0x1000>, /* vidl1 */
843
+			<0x0 0x04a06000 0x0 0x1000>, /* vid */
844
+			<0x0 0x04a07000 0x0 0x1000>, /* ovr1 */
845
+			<0x0 0x04a08000 0x0 0x1000>, /* ovr2 */
846
+			<0x0 0x04a0a000 0x0 0x1000>, /* vp1 */
847
+			<0x0 0x04a0b000 0x0 0x1000>; /* vp2 */
848
+		reg-names = "common", "vidl1", "vid",
849
+			"ovr1", "ovr2", "vp1", "vp2";
850
+
851
+		ti,am65x-oldi-io-ctrl = <&dss_oldi_io_ctrl>;
852
+
853
+		power-domains = <&k3_pds 67 TI_SCI_PD_EXCLUSIVE>;
854
+
855
+		clocks =	<&k3_clks 67 1>,
856
+				<&k3_clks 216 1>,
857
+				<&k3_clks 67 2>;
858
+		clock-names = "fck", "vp1", "vp2";
859
+
860
+		/*
861
+		 * Set vp2 clk (DPI_1_IN_CLK) mux to PLL4 via
862
+		 * DIV1. See "Figure 12-3365. DSS Integration"
863
+		 * in AM65x TRM for details.
864
+		 */
865
+		assigned-clocks = <&k3_clks 67 2>;
866
+		assigned-clock-parents = <&k3_clks 67 5>;
867
+
868
+		interrupts = <GIC_SPI 166 IRQ_TYPE_EDGE_RISING>;
869
+
870
+		status = "disabled";
871
+
872
+		dma-coherent;
873
+
874
+		dss_ports: ports {
875
+			#address-cells = <1>;
876
+			#size-cells = <0>;
877
+		};
878
+	};
879
+
880
+	ehrpwm0: pwm@3000000 {
881
+		compatible = "ti,am654-ehrpwm", "ti,am3352-ehrpwm";
882
+		#pwm-cells = <3>;
883
+		reg = <0x0 0x3000000 0x0 0x100>;
884
+		power-domains = <&k3_pds 40 TI_SCI_PD_EXCLUSIVE>;
885
+		clocks = <&ehrpwm_tbclk 0>, <&k3_clks 40 0>;
886
+		clock-names = "tbclk", "fck";
887
+	};
888
+
889
+	ehrpwm1: pwm@3010000 {
890
+		compatible = "ti,am654-ehrpwm", "ti,am3352-ehrpwm";
891
+		#pwm-cells = <3>;
892
+		reg = <0x0 0x3010000 0x0 0x100>;
893
+		power-domains = <&k3_pds 41 TI_SCI_PD_EXCLUSIVE>;
894
+		clocks = <&ehrpwm_tbclk 1>, <&k3_clks 41 0>;
895
+		clock-names = "tbclk", "fck";
896
+	};
897
+
898
+	ehrpwm2: pwm@3020000 {
899
+		compatible = "ti,am654-ehrpwm", "ti,am3352-ehrpwm";
900
+		#pwm-cells = <3>;
901
+		reg = <0x0 0x3020000 0x0 0x100>;
902
+		power-domains = <&k3_pds 42 TI_SCI_PD_EXCLUSIVE>;
903
+		clocks = <&ehrpwm_tbclk 2>, <&k3_clks 42 0>;
904
+		clock-names = "tbclk", "fck";
905
+	};
906
+
907
+	ehrpwm3: pwm@3030000 {
908
+		compatible = "ti,am654-ehrpwm", "ti,am3352-ehrpwm";
909
+		#pwm-cells = <3>;
910
+		reg = <0x0 0x3030000 0x0 0x100>;
911
+		power-domains = <&k3_pds 43 TI_SCI_PD_EXCLUSIVE>;
912
+		clocks = <&ehrpwm_tbclk 3>, <&k3_clks 43 0>;
913
+		clock-names = "tbclk", "fck";
914
+	};
915
+
916
+	ehrpwm4: pwm@3040000 {
917
+		compatible = "ti,am654-ehrpwm", "ti,am3352-ehrpwm";
918
+		#pwm-cells = <3>;
919
+		reg = <0x0 0x3040000 0x0 0x100>;
920
+		power-domains = <&k3_pds 44 TI_SCI_PD_EXCLUSIVE>;
921
+		clocks = <&ehrpwm_tbclk 4>, <&k3_clks 44 0>;
922
+		clock-names = "tbclk", "fck";
923
+	};
924
+
925
+	ehrpwm5: pwm@3050000 {
926
+		compatible = "ti,am654-ehrpwm", "ti,am3352-ehrpwm";
927
+		#pwm-cells = <3>;
928
+		reg = <0x0 0x3050000 0x0 0x100>;
929
+		power-domains = <&k3_pds 45 TI_SCI_PD_EXCLUSIVE>;
930
+		clocks = <&ehrpwm_tbclk 5>, <&k3_clks 45 0>;
931
+		clock-names = "tbclk", "fck";
932
+	};
31933 };