forked from ~ljy/RK356X_SDK_RELEASE
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hc
2024-01-05 071106ecf68c401173c58808b1cf5f68cc50d390 
 kernel/arch/arm64/boot/dts/rockchip/rk3568.dtsi
....@@ -59,7 +59,8 @@
5959 		spi1 = &spi1;
6060 		spi2 = &spi2;
6161 		spi3 = &spi3;
62
-		spi4 = &sfc; // for U-Boot
62
+		lvds0 = &lvds;
63
+		lvds1 = &lvds1;
6364 	};
6465 
6566 	cpus {
....@@ -126,8 +127,11 @@
126127 		opp-shared;
127128 
128129 		mbist-vmin = <825000 900000 950000>;
129
-		nvmem-cells = <&cpu_leakage>, <&core_pvtm>, <&mbist_vmin>, <&cpu_opp_info>;
130
-		nvmem-cell-names = "leakage", "pvtm", "mbist-vmin", "opp-info";
130
+		nvmem-cells = <&cpu_leakage>, <&core_pvtm>, <&mbist_vmin>, <&cpu_opp_info>,
131
+			      <&specification_serial_number>, <&remark_spec_serial_number>;
132
+		nvmem-cell-names = "leakage", "pvtm", "mbist-vmin", "opp-info",
133
+				   "specification_serial_number", "remark_spec_serial_number";
134
+		rockchip,supported-hw;
131135 		rockchip,max-volt = <1150000>;
132136 		rockchip,pvtm-voltage-sel = <
133137 			0        84000   0
....@@ -151,23 +155,28 @@
151155 			   0      1992   75000
152156 		>;
153157 
158
+		/* RK3568 && RK3568M cpu OPPs */
154159 		opp-408000000 {
160
+			opp-supported-hw = <0xfb 0xffff>;
155161 			opp-hz = /bits/ 64 <408000000>;
156162 			opp-microvolt = <850000 850000 1150000>;
157163 			clock-latency-ns = <40000>;
158164 		};
159165 		opp-600000000 {
166
+			opp-supported-hw = <0xfb 0xffff>;
160167 			opp-hz = /bits/ 64 <600000000>;
161168 			opp-microvolt = <850000 850000 1150000>;
162169 			clock-latency-ns = <40000>;
163170 		};
164171 		opp-816000000 {
172
+			opp-supported-hw = <0xfb 0xffff>;
165173 			opp-hz = /bits/ 64 <816000000>;
166174 			opp-microvolt = <850000 850000 1150000>;
167175 			clock-latency-ns = <40000>;
168176 			opp-suspend;
169177 		};
170178 		opp-1104000000 {
179
+			opp-supported-hw = <0xfb 0xffff>;
171180 			opp-hz = /bits/ 64 <1104000000>;
172181 			opp-microvolt = <900000 900000 1150000>;
173182 			opp-microvolt-L0 = <900000 900000 1150000>;
....@@ -177,6 +186,7 @@
177186 			clock-latency-ns = <40000>;
178187 		};
179188 		opp-1416000000 {
189
+			opp-supported-hw = <0xfb 0xffff>;
180190 			opp-hz = /bits/ 64 <1416000000>;
181191 			opp-microvolt = <1025000 1025000 1150000>;
182192 			opp-microvolt-L0 = <1025000 1025000 1150000>;
....@@ -186,6 +196,7 @@
186196 			clock-latency-ns = <40000>;
187197 		};
188198 		opp-1608000000 {
199
+			opp-supported-hw = <0xf9 0xffff>;
189200 			opp-hz = /bits/ 64 <1608000000>;
190201 			opp-microvolt = <1100000 1100000 1150000>;
191202 			opp-microvolt-L0 = <1100000 1100000 1150000>;
....@@ -195,6 +206,7 @@
195206 			clock-latency-ns = <40000>;
196207 		};
197208 		opp-1800000000 {
209
+			opp-supported-hw = <0xf9 0xffff>;
198210 			opp-hz = /bits/ 64 <1800000000>;
199211 			opp-microvolt = <1150000 1150000 1150000>;
200212 			opp-microvolt-L0 = <1150000 1150000 1150000>;
....@@ -204,6 +216,7 @@
204216 			clock-latency-ns = <40000>;
205217 		};
206218 		opp-1992000000 {
219
+			opp-supported-hw = <0xf9 0xffff>;
207220 			opp-hz = /bits/ 64 <1992000000>;
208221 			opp-microvolt = <1150000 1150000 1150000>;
209222 			opp-microvolt-L0 = <1150000 1150000 1150000>;
....@@ -212,9 +225,31 @@
212225 			opp-microvolt-L3 = <1100000 1100000 1150000>;
213226 			clock-latency-ns = <40000>;
214227 		};
228
+
229
+		/* RK3568J cpu OPPs */
230
+		opp-j-1008000000 {
231
+			opp-supported-hw = <0x04 0xffff>;
232
+			opp-hz = /bits/ 64 <1008000000>;
233
+			opp-microvolt = <850000 850000 1150000>;
234
+			clock-latency-ns = <40000>;
235
+		};
236
+		opp-j-1416000000 {
237
+			opp-supported-hw = <0x04 0xffff>;
238
+			opp-hz = /bits/ 64 <1416000000>;
239
+			opp-microvolt = <900000 900000 1150000>;
240
+			clock-latency-ns = <40000>;
241
+		};
242
+
243
+		/* RK3568M cpu OPPs */
244
+		opp-m-1608000000 {
245
+			opp-supported-hw = <0x02 0xffff>;
246
+			opp-hz = /bits/ 64 <1608000000>;
247
+			opp-microvolt = <1000000 1000000 1150000>;
248
+			clock-latency-ns = <40000>;
249
+		};
215250 	};
216251 
217
-	arm-pmu {
252
+	arm_pmu: arm-pmu {
218253 		compatible = "arm,cortex-a55-pmu", "arm,armv8-pmuv3";
219254 		interrupts = <GIC_SPI 228 IRQ_TYPE_LEVEL_HIGH>,
220255 			     <GIC_SPI 229 IRQ_TYPE_LEVEL_HIGH>,
....@@ -251,7 +286,7 @@
251286 				logo,kernel = "logo_kernel.bmp";
252287 				logo,mode = "center";
253288 				charge_logo,mode = "center";
254
-				connect = <&vp0_out_dsi1>;
289
+				connect = <&vp1_out_dsi1>;
255290 			};
256291 			route_edp: route-edp {
257292 				status = "disabled";
....@@ -259,7 +294,7 @@
259294 				logo,kernel = "logo_kernel.bmp";
260295 				logo,mode = "center";
261296 				charge_logo,mode = "center";
262
-				connect = <&vp0_out_edp>;
297
+				connect = <&vp1_out_edp>;
263298 			};
264299 			route_hdmi: route-hdmi {
265300 				status = "disabled";
....@@ -267,7 +302,7 @@
267302 				logo,kernel = "logo_kernel.bmp";
268303 				logo,mode = "center";
269304 				charge_logo,mode = "center";
270
-				connect = <&vp1_out_hdmi>;
305
+				connect = <&vp0_out_hdmi>;
271306 			};
272307 			route_lvds: route-lvds {
273308 				status = "disabled";
....@@ -288,12 +323,15 @@
288323 		};
289324 	};
290325 
291
-	firmware {
292
-		optee: optee {
293
-			compatible = "linaro,optee-tz";
294
-			method = "smc";
295
-		};
326
+	edac: edac {
327
+		compatible = "rockchip,rk3568-edac";
328
+		interrupts = <GIC_SPI 173 IRQ_TYPE_LEVEL_HIGH>,
329
+			     <GIC_SPI 175 IRQ_TYPE_LEVEL_HIGH>;
330
+		interrupt-names = "ce", "ue";
331
+		status = "disabled";
332
+	};
296333 
334
+	firmware {
297335 		scmi: scmi {
298336 			compatible = "arm,scmi-smc";
299337 			shmem = <&scmi_shmem>;
....@@ -313,6 +351,12 @@
313351 			compatible = "arm,sdei-1.0";
314352 			method = "smc";
315353 		};
354
+	};
355
+
356
+	mipi_csi2: mipi-csi2 {
357
+		compatible = "rockchip,rk3568-mipi-csi2";
358
+		rockchip,hw = <&mipi_csi2_hw>;
359
+		status = "disabled";
316360 	};
317361 
318362 	mpp_srv: mpp-srv {
....@@ -580,12 +624,15 @@
580624 			resets = <&cru SRST_USB3OTG0>;
581625 			reset-names = "usb3-otg";
582626 			snps,dis_enblslpm_quirk;
583
-			snps,dis-u1u2-quirk;
627
+			snps,dis-u1-entry-quirk;
628
+			snps,dis-u2-entry-quirk;
584629 			snps,dis-u2-freeclk-exists-quirk;
585630 			snps,dis-del-phy-power-chg-quirk;
586631 			snps,dis-tx-ipgap-linecheck-quirk;
587632 			snps,dis_rxdet_inp3_quirk;
588633 			snps,xhci-trb-ent-quirk;
634
+			snps,parkmode-disable-hs-quirk;
635
+			snps,parkmode-disable-ss-quirk;
589636 			quirk-skip-phy-init;
590637 			status = "disabled";
591638 		};
....@@ -619,6 +666,8 @@
619666 			snps,dis-tx-ipgap-linecheck-quirk;
620667 			snps,dis_rxdet_inp3_quirk;
621668 			snps,xhci-trb-ent-quirk;
669
+			snps,parkmode-disable-hs-quirk;
670
+			snps,parkmode-disable-ss-quirk;
622671 			status = "disabled";
623672 		};
624673 	};
....@@ -759,6 +808,34 @@
759808 						reg = <2>;
760809 						remote-endpoint = <&vp2_out_lvds>;
761810 						status = "disabled";
811
+					};
812
+				};
813
+			};
814
+		};
815
+
816
+		lvds1: lvds1 {
817
+			compatible = "rockchip,rk3568-lvds";
818
+			phys = <&video_phy1>;
819
+			phy-names = "phy";
820
+			status = "disabled";
821
+
822
+			ports {
823
+				#address-cells = <1>;
824
+				#size-cells = <0>;
825
+
826
+				port@0 {
827
+					reg = <0>;
828
+					#address-cells = <1>;
829
+					#size-cells = <0>;
830
+
831
+					lvds1_in_vp1: endpoint@0 {
832
+						reg = <0>;
833
+						remote-endpoint = <&vp1_out_lvds1>;
834
+					};
835
+
836
+					lvds1_in_vp2: endpoint@1 {
837
+						reg = <1>;
838
+						remote-endpoint = <&vp2_out_lvds1>;
762839 					};
763840 				};
764841 			};
....@@ -1107,8 +1184,11 @@
11071184 		compatible = "operating-points-v2";
11081185 
11091186 		mbist-vmin = <825000 900000 950000>;
1110
-		nvmem-cells = <&npu_leakage>, <&core_pvtm>, <&mbist_vmin>, <&npu_opp_info>;
1111
-		nvmem-cell-names = "leakage", "pvtm", "mbist-vmin", "opp-info";
1187
+		nvmem-cells = <&npu_leakage>, <&core_pvtm>, <&mbist_vmin>, <&npu_opp_info>,
1188
+			      <&specification_serial_number>, <&remark_spec_serial_number>;
1189
+		nvmem-cell-names = "leakage", "pvtm", "mbist-vmin", "opp-info",
1190
+				   "specification_serial_number", "remark_spec_serial_number";
1191
+		rockchip,supported-hw;
11121192 		rockchip,max-volt = <1000000>;
11131193 		rockchip,temp-hysteresis = <5000>;
11141194 		rockchip,low-temp = <0>;
....@@ -1124,23 +1204,29 @@
11241204 		>;
11251205 		rockchip,pvtm-ch = <0 5>;
11261206 
1207
+		/* RK3568 && RK3568M npu OPPs */
11271208 		opp-200000000 {
1209
+			opp-supported-hw = <0xfb 0xffff>;
11281210 			opp-hz = /bits/ 64 <200000000>;
11291211 			opp-microvolt = <850000 850000 1000000>;
11301212 		};
11311213 		opp-300000000 {
1214
+			opp-supported-hw = <0xfb 0xffff>;
11321215 			opp-hz = /bits/ 64 <297000000>;
11331216 			opp-microvolt = <850000 850000 1000000>;
11341217 		};
11351218 		opp-400000000 {
1219
+			opp-supported-hw = <0xfb 0xffff>;
11361220 			opp-hz = /bits/ 64 <400000000>;
11371221 			opp-microvolt = <850000 850000 1000000>;
11381222 		};
11391223 		opp-600000000 {
1224
+			opp-supported-hw = <0xfb 0xffff>;
11401225 			opp-hz = /bits/ 64 <600000000>;
11411226 			opp-microvolt = <850000 850000 1000000>;
11421227 		};
11431228 		opp-700000000 {
1229
+			opp-supported-hw = <0xfb 0xffff>;
11441230 			opp-hz = /bits/ 64 <700000000>;
11451231 			opp-microvolt = <875000 875000 1000000>;
11461232 			opp-microvolt-L0 = <875000 875000 1000000>;
....@@ -1149,6 +1235,7 @@
11491235 			opp-microvolt-L3 = <850000 850000 1000000>;
11501236 		};
11511237 		opp-800000000 {
1238
+			opp-supported-hw = <0xfb 0xffff>;
11521239 			opp-hz = /bits/ 64 <800000000>;
11531240 			opp-microvolt = <925000 925000 1000000>;
11541241 			opp-microvolt-L0 = <925000 925000 1000000>;
....@@ -1157,6 +1244,7 @@
11571244 			opp-microvolt-L3 = <875000 875000 1000000>;
11581245 		};
11591246 		opp-900000000 {
1247
+			opp-supported-hw = <0xf9 0xffff>;
11601248 			opp-hz = /bits/ 64 <900000000>;
11611249 			opp-microvolt = <975000 975000 1000000>;
11621250 			opp-microvolt-L0 = <975000 975000 1000000>;
....@@ -1165,6 +1253,7 @@
11651253 			opp-microvolt-L3 = <900000 900000 1000000>;
11661254 		};
11671255 		opp-1000000000 {
1256
+			opp-supported-hw = <0xf9 0xffff>;
11681257 			opp-hz = /bits/ 64 <1000000000>;
11691258 			opp-microvolt = <1000000 1000000 1000000>;
11701259 			opp-microvolt-L0 = <1000000 1000000 1000000>;
....@@ -1172,6 +1261,20 @@
11721261 			opp-microvolt-L2 = <950000 950000 1000000>;
11731262 			opp-microvolt-L3 = <925000 925000 1000000>;
11741263 			status = "disabled";
1264
+		};
1265
+
1266
+		/* RK3568J npu OPPs */
1267
+		opp-j-600000000 {
1268
+			opp-supported-hw = <0x04 0xffff>;
1269
+			opp-hz = /bits/ 64 <600000000>;
1270
+			opp-microvolt = <900000 900000 1000000>;
1271
+		};
1272
+
1273
+		/* RK3568M npu OPPs */
1274
+		opp-m-900000000 {
1275
+			opp-supported-hw = <0x02 0xffff>;
1276
+			opp-hz = /bits/ 64 <900000000>;
1277
+			opp-microvolt = <925000 925000 1000000>;
11751278 		};
11761279 	};
11771280 
....@@ -1263,8 +1366,11 @@
12631366 		compatible = "operating-points-v2";
12641367 
12651368 		mbist-vmin = <825000 900000 950000>;
1266
-		nvmem-cells = <&gpu_leakage>, <&core_pvtm>, <&mbist_vmin>, <&gpu_opp_info>;
1267
-		nvmem-cell-names = "leakage", "pvtm", "mbist-vmin", "opp-info";
1369
+		nvmem-cells = <&gpu_leakage>, <&core_pvtm>, <&mbist_vmin>, <&gpu_opp_info>,
1370
+			      <&specification_serial_number>, <&remark_spec_serial_number>;
1371
+		nvmem-cell-names = "leakage", "pvtm", "mbist-vmin", "opp-info",
1372
+				   "specification_serial_number", "remark_spec_serial_number";
1373
+		rockchip,supported-hw;
12681374 		rockchip,max-volt = <1000000>;
12691375 		rockchip,temp-hysteresis = <5000>;
12701376 		rockchip,low-temp = <0>;
....@@ -1280,19 +1386,24 @@
12801386 		>;
12811387 		rockchip,pvtm-ch = <0 5>;
12821388 
1389
+		/* RK3568 && RK3568M gpu OPPs */
12831390 		opp-200000000 {
1391
+			opp-supported-hw = <0xfb 0xffff>;
12841392 			opp-hz = /bits/ 64 <200000000>;
12851393 			opp-microvolt = <850000 850000 1000000>;
12861394 		};
12871395 		opp-300000000 {
1396
+			opp-supported-hw = <0xfb 0xffff>;
12881397 			opp-hz = /bits/ 64 <300000000>;
12891398 			opp-microvolt = <850000 850000 1000000>;
12901399 		};
12911400 		opp-400000000 {
1401
+			opp-supported-hw = <0xfb 0xffff>;
12921402 			opp-hz = /bits/ 64 <400000000>;
12931403 			opp-microvolt = <850000 850000 1000000>;
12941404 		};
12951405 		opp-600000000 {
1406
+			opp-supported-hw = <0xfb 0xffff>;
12961407 			opp-hz = /bits/ 64 <600000000>;
12971408 			opp-microvolt = <900000 900000 1000000>;
12981409 			opp-microvolt-L0 = <900000 900000 1000000>;
....@@ -1301,6 +1412,7 @@
13011412 			opp-microvolt-L3 = <850000 850000 1000000>;
13021413 		};
13031414 		opp-700000000 {
1415
+			opp-supported-hw = <0xfb 0xffff>;
13041416 			opp-hz = /bits/ 64 <700000000>;
13051417 			opp-microvolt = <950000 950000 1000000>;
13061418 			opp-microvolt-L0 = <950000 950000 1000000>;
....@@ -1309,6 +1421,7 @@
13091421 			opp-microvolt-L3 = <875000 875000 1000000>;
13101422 		};
13111423 		opp-800000000 {
1424
+			opp-supported-hw = <0xf9 0xffff>;
13121425 			opp-hz = /bits/ 64 <800000000>;
13131426 			opp-microvolt = <1000000 1000000 1000000>;
13141427 			opp-microvolt-L0 = <1000000 1000000 1000000>;
....@@ -1316,6 +1429,21 @@
13161429 			opp-microvolt-L2 = <950000 950000 1000000>;
13171430 			opp-microvolt-L3 = <925000 925000 1000000>;
13181431 		};
1432
+
1433
+		/* RK3568J gpu OPPs */
1434
+		opp-j-600000000 {
1435
+			opp-supported-hw = <0x04 0xffff>;
1436
+			opp-hz = /bits/ 64 <600000000>;
1437
+			opp-microvolt = <900000 900000 1000000>;
1438
+		};
1439
+
1440
+		/* RK3568M gpu OPPs */
1441
+		opp-m-800000000 {
1442
+			opp-supported-hw = <0x02 0xffff>;
1443
+			opp-hz = /bits/ 64 <800000000>;
1444
+			opp-microvolt = <950000 950000 1000000>;
1445
+		};
1446
+
13191447 	};
13201448 
13211449 	pvtm@fde80000 {
....@@ -1374,7 +1502,6 @@
13741502 		clock-names = "aclk", "iface";
13751503 		clocks = <&cru ACLK_VPU>, <&cru HCLK_VPU>;
13761504 		power-domains = <&power RK3568_PD_VPU>;
1377
-		rockchip,shootdown-entire;
13781505 		#iommu-cells = <0>;
13791506 		status = "disabled";
13801507 	};
....@@ -1427,7 +1554,6 @@
14271554 		clock-names = "aclk", "iface";
14281555 		clocks = <&cru ACLK_JDEC>, <&cru HCLK_JDEC>;
14291556 		power-domains = <&power RK3568_PD_RGA>;
1430
-		rockchip,shootdown-entire;
14311557 		#iommu-cells = <0>;
14321558 		status = "disabled";
14331559 	};
....@@ -1457,7 +1583,6 @@
14571583 		clock-names = "aclk", "iface";
14581584 		clocks = <&cru ACLK_JENC>, <&cru HCLK_JENC>;
14591585 		power-domains = <&power RK3568_PD_RGA>;
1460
-		rockchip,shootdown-entire;
14611586 		#iommu-cells = <0>;
14621587 		status = "disabled";
14631588 	};
....@@ -1488,7 +1613,6 @@
14881613 		clock-names = "aclk", "iface";
14891614 		#iommu-cells = <0>;
14901615 		power-domains = <&power RK3568_PD_RGA>;
1491
-		rockchip,shootdown-entire;
14921616 		//rockchip,disable-device-link-resume;
14931617 		status = "disabled";
14941618 	};
....@@ -1564,7 +1688,6 @@
15641688 		clock-names = "aclk", "iface";
15651689 		rockchip,disable-mmu-reset;
15661690 		rockchip,enable-cmd-retry;
1567
-		rockchip,shootdown-entire;
15681691 		#iommu-cells = <0>;
15691692 		power-domains = <&power RK3568_PD_RKVENC>;
15701693 		status = "disabled";
....@@ -1644,13 +1767,12 @@
16441767 		clocks = <&cru ACLK_RKVDEC>, <&cru HCLK_RKVDEC>;
16451768 		clock-names = "aclk", "iface";
16461769 		power-domains = <&power RK3568_PD_RKVDEC>;
1647
-		rockchip,shootdown-entire;
16481770 		#iommu-cells = <0>;
16491771 		status = "disabled";
16501772 	};
16511773 
1652
-	mipi_csi2: mipi-csi2@fdfb0000 {
1653
-		compatible = "rockchip,rk3568-mipi-csi2";
1774
+	mipi_csi2_hw: mipi-csi2-hw@fdfb0000 {
1775
+		compatible = "rockchip,rk3568-mipi-csi2-hw";
16541776 		reg = <0x0 0xfdfb0000 0x0 0x10000>;
16551777 		reg-names = "csihost_regs";
16561778 		interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>,
....@@ -1897,6 +2019,11 @@
18972019 					reg = <4>;
18982020 					remote-endpoint = <&lvds_in_vp1>;
18992021 				};
2022
+
2023
+				vp1_out_lvds1: endpoint@5 {
2024
+					reg = <5>;
2025
+					remote-endpoint = <&lvds1_in_vp1>;
2026
+				};
19002027 			};
19012028 
19022029 			vp2: port@2 {
....@@ -1914,6 +2041,11 @@
19142041 					reg = <1>;
19152042 					remote-endpoint = <&rgb_in_vp2>;
19162043 				};
2044
+
2045
+				vp2_out_lvds1: endpoint@2 {
2046
+					reg = <2>;
2047
+					remote-endpoint = <&lvds1_in_vp2>;
2048
+				};
19172049 			};
19182050 		};
19192051 	};
....@@ -1926,6 +2058,7 @@
19262058 		clocks = <&cru ACLK_VOP>, <&cru HCLK_VOP>;
19272059 		clock-names = "aclk", "iface";
19282060 		#iommu-cells = <0>;
2061
+		rockchip,disable-device-link-resume;
19292062 		status = "disabled";
19302063 	};
19312064 
....@@ -1933,12 +2066,12 @@
19332066 		compatible = "rockchip,rk3568-mipi-dsi";
19342067 		reg = <0x0 0xfe060000 0x0 0x10000>;
19352068 		interrupts = <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>;
1936
-		clocks = <&cru PCLK_DSITX_0>, <&cru HCLK_VO>, <&video_phy0>;
1937
-		clock-names = "pclk", "hclk", "hs_clk";
2069
+		clocks = <&cru PCLK_DSITX_0>, <&cru HCLK_VO>;
2070
+		clock-names = "pclk", "hclk";
19382071 		resets = <&cru SRST_P_DSITX_0>;
19392072 		reset-names = "apb";
19402073 		phys = <&video_phy0>;
1941
-		phy-names = "mipi_dphy";
2074
+		phy-names = "dphy";
19422075 		power-domains = <&power RK3568_PD_VO>;
19432076 		rockchip,grf = <&grf>;
19442077 		#address-cells = <1>;
....@@ -1973,12 +2106,12 @@
19732106 		compatible = "rockchip,rk3568-mipi-dsi";
19742107 		reg = <0x0 0xfe070000 0x0 0x10000>;
19752108 		interrupts = <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>;
1976
-		clocks = <&cru PCLK_DSITX_1>, <&cru HCLK_VO>, <&video_phy1>;
1977
-		clock-names = "pclk", "hclk", "hs_clk";
2109
+		clocks = <&cru PCLK_DSITX_1>, <&cru HCLK_VO>;
2110
+		clock-names = "pclk", "hclk";
19782111 		resets = <&cru SRST_P_DSITX_1>;
19792112 		reset-names = "apb";
19802113 		phys = <&video_phy1>;
1981
-		phy-names = "mipi_dphy";
2114
+		phy-names = "dphy";
19822115 		power-domains = <&power RK3568_PD_VO>;
19832116 		rockchip,grf = <&grf>;
19842117 		#address-cells = <1>;
....@@ -2012,8 +2145,7 @@
20122145 	hdmi: hdmi@fe0a0000 {
20132146 		compatible = "rockchip,rk3568-dw-hdmi";
20142147 		reg = <0x0 0xfe0a0000 0x0 0x20000>;
2015
-		interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>;
2016
-		interrupt-names = "hdmi", "hdmi_wakeup";
2148
+		interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>;
20172149 		clocks = <&cru PCLK_HDMI_HOST>,
20182150 			 <&cru CLK_HDMI_SFR>,
20192151 			 <&cru CLK_HDMI_CEC>,
....@@ -2032,7 +2164,7 @@
20322164 			#address-cells = <1>;
20332165 			#size-cells = <0>;
20342166 
2035
-			hdmi_in: port {
2167
+			port@0 {
20362168 				reg = <0>;
20372169 				#address-cells = <1>;
20382170 				#size-cells = <0>;
....@@ -2042,6 +2174,7 @@
20422174 					remote-endpoint = <&vp0_out_hdmi>;
20432175 					status = "disabled";
20442176 				};
2177
+
20452178 				hdmi_in_vp1: endpoint@1 {
20462179 					reg = <1>;
20472180 					remote-endpoint = <&vp1_out_hdmi>;
....@@ -2332,8 +2465,11 @@
23322465 		compatible = "operating-points-v2";
23332466 
23342467 		mbist-vmin = <825000 900000 950000>;
2335
-		nvmem-cells = <&log_leakage>, <&core_pvtm>, <&mbist_vmin>, <&dmc_opp_info>;
2336
-		nvmem-cell-names = "leakage", "pvtm", "mbist-vmin", "opp-info";
2468
+		nvmem-cells = <&log_leakage>, <&core_pvtm>, <&mbist_vmin>, <&dmc_opp_info>,
2469
+			      <&specification_serial_number>, <&remark_spec_serial_number>;
2470
+		nvmem-cell-names = "leakage", "pvtm", "mbist-vmin", "opp-info",
2471
+				   "specification_serial_number", "remark_spec_serial_number";
2472
+		rockchip,supported-hw;
23372473 		rockchip,max-volt = <1000000>;
23382474 		rockchip,temp-hysteresis = <5000>;
23392475 		rockchip,low-temp = <0>;
....@@ -2351,17 +2487,21 @@
23512487 		>;
23522488 		rockchip,pvtm-ch = <0 5>;
23532489 
2490
+		/* RK3568 dmc OPPs */
23542491 		opp-1560000000 {
2492
+			opp-supported-hw = <0xf9 0xffff>;
23552493 			opp-hz = /bits/ 64 <1560000000>;
23562494 			opp-microvolt = <900000 900000 1000000>;
23572495 			opp-microvolt-L0 = <900000 900000 1000000>;
23582496 			opp-microvolt-L1 = <875000 875000 1000000>;
23592497 		};
2360
-	};
23612498 
2362
-	dmcdbg: dmcdbg {
2363
-		compatible = "rockchip,rk3568-dmcdbg";
2364
-		status = "disabled";
2499
+		/* RK3568J/M dmc OPPs */
2500
+		opp-j-m-1560000000 {
2501
+			opp-supported-hw = <0x06 0xffff>;
2502
+			opp-hz = /bits/ 64 <1560000000>;
2503
+			opp-microvolt = <875000 875000 1000000>;
2504
+		};
23652505 	};
23662506 
23672507 	pcie2x1: pcie@fe260000 {
....@@ -2613,7 +2753,7 @@
26132753 		status = "disabled";
26142754 	};
26152755 
2616
-	sfc: sfc@fe300000 {
2756
+	sfc: spi@fe300000 {
26172757 		compatible = "rockchip,sfc";
26182758 		reg = <0x0 0xfe300000 0x0 0x4000>;
26192759 		interrupts = <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>;
....@@ -2621,11 +2761,13 @@
26212761 		clock-names = "clk_sfc", "hclk_sfc";
26222762 		assigned-clocks = <&cru SCLK_SFC>;
26232763 		assigned-clock-rates = <100000000>;
2764
+		#address-cells = <1>;
2765
+		#size-cells = <0>;
26242766 		status = "disabled";
26252767 	};
26262768 
26272769 	sdhci: sdhci@fe310000 {
2628
-		compatible = "rockchip,dwcmshc-sdhci", "snps,dwcmshc-sdhci";
2770
+		compatible = "rockchip,rk3568-dwcmshc", "rockchip,dwcmshc-sdhci";
26292771 		reg = <0x0 0xfe310000 0x0 0x10000>;
26302772 		interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>;
26312773 		assigned-clocks = <&cru BCLK_EMMC>, <&cru TCLK_EMMC>,
....@@ -2635,6 +2777,10 @@
26352777 			 <&cru ACLK_EMMC>, <&cru BCLK_EMMC>,
26362778 			 <&cru TCLK_EMMC>;
26372779 		clock-names = "core", "bus", "axi", "block", "timer";
2780
+		resets = <&cru SRST_C_EMMC>, <&cru SRST_H_EMMC>,
2781
+			 <&cru SRST_A_EMMC>, <&cru SRST_B_EMMC>,
2782
+			 <&cru SRST_T_EMMC>;
2783
+		reset-names = "core", "bus", "axi", "block", "timer";
26382784 		status = "disabled";
26392785 	};
26402786 
....@@ -2686,6 +2832,10 @@
26862832 		/* Data cells */
26872833 		cpu_code: cpu-code@2 {
26882834 			reg = <0x02 0x2>;
2835
+		};
2836
+		specification_serial_number: specification-serial-number@7 {
2837
+			reg = <0x07 0x1>;
2838
+			bits = <0 5>;
26892839 		};
26902840 		otp_cpu_version: cpu-version@8 {
26912841 			reg = <0x08 0x1>;
....@@ -2745,6 +2895,10 @@
27452895 		};
27462896 		dmc_opp_info: dmc-opp-info@48 {
27472897 			reg = <0x48 0x6>;
2898
+		};
2899
+		remark_spec_serial_number: remark-spec-serial-number@56 {
2900
+			reg = <0x56 0x1>;
2901
+			bits = <0 5>;
27482902 		};
27492903 	};
27502904 
....@@ -2837,7 +2991,7 @@
28372991 	};
28382992 
28392993 	pdm: pdm@fe440000 {
2840
-		compatible = "rockchip,rk3568-pdm";
2994
+		compatible = "rockchip,rk3568-pdm", "rockchip,pdm";
28412995 		reg = <0x0 0xfe440000 0x0 0x1000>;
28422996 		clocks = <&cru MCLK_PDM>, <&cru HCLK_PDM>;
28432997 		clock-names = "pdm_clk", "pdm_hclk";
....@@ -3077,6 +3231,7 @@
30773231 		pinctrl-names = "default", "high_speed";
30783232 		pinctrl-0 = <&spi0m0_cs0 &spi0m0_cs1 &spi0m0_pins>;
30793233 		pinctrl-1 = <&spi0m0_cs0 &spi0m0_cs1 &spi0m0_pins_hs>;
3234
+		num-cs = <2>;
30803235 		status = "disabled";
30813236 	};
30823237 
....@@ -3093,6 +3248,7 @@
30933248 		pinctrl-names = "default", "high_speed";
30943249 		pinctrl-0 = <&spi1m0_cs0 &spi1m0_cs1 &spi1m0_pins>;
30953250 		pinctrl-1 = <&spi1m0_cs0 &spi1m0_cs1 &spi1m0_pins_hs>;
3251
+		num-cs = <2>;
30963252 		status = "disabled";
30973253 	};
30983254 
....@@ -3109,6 +3265,7 @@
31093265 		pinctrl-names = "default", "high_speed";
31103266 		pinctrl-0 = <&spi2m0_cs0 &spi2m0_cs1 &spi2m0_pins>;
31113267 		pinctrl-1 = <&spi2m0_cs0 &spi2m0_cs1 &spi2m0_pins_hs>;
3268
+		num-cs = <2>;
31123269 		status = "disabled";
31133270 	};
31143271 
....@@ -3125,6 +3282,7 @@
31253282 		pinctrl-names = "default", "high_speed";
31263283 		pinctrl-0 = <&spi3m0_cs0 &spi3m0_cs1 &spi3m0_pins>;
31273284 		pinctrl-1 = <&spi3m0_cs0 &spi3m0_cs1 &spi3m0_pins_hs>;
3285
+		num-cs = <2>;
31283286 		status = "disabled";
31293287 	};
31303288 
....@@ -3503,31 +3661,33 @@
35033661 		status = "disabled";
35043662 	};
35053663 
3506
-	video_phy0: video-phy@fe850000 {
3507
-		compatible = "rockchip,rk3568-video-phy";
3664
+	video_phy0: phy@fe850000 {
3665
+		compatible = "rockchip,rk3568-dsi-dphy", "rockchip,rk3568-video-phy";
35083666 		reg = <0x0 0xfe850000  0x0 0x10000>,
35093667 		      <0x0 0xfe060000 0x0 0x10000>;
3668
+		reg-names = "phy", "host";
35103669 		clocks = <&pmucru CLK_MIPIDSIPHY0_REF>,
35113670 			 <&cru PCLK_MIPIDSIPHY0>, <&cru PCLK_DSITX_0>;
3512
-		clock-names = "ref", "pclk_phy", "pclk_host";
3671
+		clock-names = "ref", "pclk", "pclk_host";
35133672 		#clock-cells = <0>;
35143673 		resets = <&cru SRST_P_MIPIDSIPHY0>;
3515
-		reset-names = "rst";
3674
+		reset-names = "apb";
35163675 		power-domains = <&power RK3568_PD_VO>;
35173676 		#phy-cells = <0>;
35183677 		status = "disabled";
35193678 	};
35203679 
3521
-	video_phy1: video-phy@fe860000 {
3522
-		compatible = "rockchip,rk3568-video-phy";
3680
+	video_phy1: phy@fe860000 {
3681
+		compatible = "rockchip,rk3568-dsi-dphy", "rockchip,rk3568-video-phy";
35233682 		reg = <0x0 0xfe860000  0x0 0x10000>,
35243683 		      <0x0 0xfe070000 0x0 0x10000>;
3684
+		reg-names = "phy", "host";
35253685 		clocks = <&pmucru CLK_MIPIDSIPHY1_REF>,
35263686 			 <&cru PCLK_MIPIDSIPHY1>, <&cru PCLK_DSITX_1>;
3527
-		clock-names = "ref", "pclk_phy", "pclk_host";
3687
+		clock-names = "ref", "pclk", "pclk_host";
35283688 		#clock-cells = <0>;
35293689 		resets = <&cru SRST_P_MIPIDSIPHY1>;
3530
-		reset-names = "rst";
3690
+		reset-names = "apb";
35313691 		power-domains = <&power RK3568_PD_VO>;
35323692 		#phy-cells = <0>;
35333693 		status = "disabled";
....@@ -3637,7 +3797,7 @@
36373797 		#size-cells = <2>;
36383798 		ranges;
36393799 
3640
-		gpio0: gpio@fdd60000 {
3800
+		gpio0: gpio0@fdd60000 {
36413801 			compatible = "rockchip,gpio-bank";
36423802 			reg = <0x0 0xfdd60000 0x0 0x100>;
36433803 			interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
....@@ -3645,12 +3805,11 @@
36453805 
36463806 			gpio-controller;
36473807 			#gpio-cells = <2>;
3648
-			gpio-ranges = <&pinctrl 0 0 32>;
36493808 			interrupt-controller;
36503809 			#interrupt-cells = <2>;
36513810 		};
36523811 
3653
-		gpio1: gpio@fe740000 {
3812
+		gpio1: gpio1@fe740000 {
36543813 			compatible = "rockchip,gpio-bank";
36553814 			reg = <0x0 0xfe740000 0x0 0x100>;
36563815 			interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>;
....@@ -3658,12 +3817,11 @@
36583817 
36593818 			gpio-controller;
36603819 			#gpio-cells = <2>;
3661
-			gpio-ranges = <&pinctrl 0 32 32>;
36623820 			interrupt-controller;
36633821 			#interrupt-cells = <2>;
36643822 		};
36653823 
3666
-		gpio2: gpio@fe750000 {
3824
+		gpio2: gpio2@fe750000 {
36673825 			compatible = "rockchip,gpio-bank";
36683826 			reg = <0x0 0xfe750000 0x0 0x100>;
36693827 			interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
....@@ -3671,12 +3829,11 @@
36713829 
36723830 			gpio-controller;
36733831 			#gpio-cells = <2>;
3674
-			gpio-ranges = <&pinctrl 0 64 32>;
36753832 			interrupt-controller;
36763833 			#interrupt-cells = <2>;
36773834 		};
36783835 
3679
-		gpio3: gpio@fe760000 {
3836
+		gpio3: gpio3@fe760000 {
36803837 			compatible = "rockchip,gpio-bank";
36813838 			reg = <0x0 0xfe760000 0x0 0x100>;
36823839 			interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
....@@ -3684,12 +3841,11 @@
36843841 
36853842 			gpio-controller;
36863843 			#gpio-cells = <2>;
3687
-			gpio-ranges = <&pinctrl 0 96 32>;
36883844 			interrupt-controller;
36893845 			#interrupt-cells = <2>;
36903846 		};
36913847 
3692
-		gpio4: gpio@fe770000 {
3848
+		gpio4: gpio4@fe770000 {
36933849 			compatible = "rockchip,gpio-bank";
36943850 			reg = <0x0 0xfe770000 0x0 0x100>;
36953851 			interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
....@@ -3697,7 +3853,6 @@
36973853 
36983854 			gpio-controller;
36993855 			#gpio-cells = <2>;
3700
-			gpio-ranges = <&pinctrl 0 128 32>;
37013856 			interrupt-controller;
37023857 			#interrupt-cells = <2>;
37033858 		};