~hc/RK356X_SDK_RELEASE.git

..	..	@@ -10,7 +10,10 @@
10	10	#include <dt-bindings/pinctrl/rockchip.h>
11	11	#include <dt-bindings/power/rk3328-power.h>
12	12	#include <dt-bindings/soc/rockchip,boot-mode.h>
	13	+#include <dt-bindings/soc/rockchip-system-status.h>
	14	+#include <dt-bindings/suspend/rockchip-rk3328.h>
13	15	#include <dt-bindings/thermal/thermal.h>
	16	+#include "rk3328-dram-default-timing.dtsi"
14	17
15	18	/ {
16	19	compatible = "rockchip,rk3328";
..	..	@@ -20,19 +23,19 @@
20	23	#size-cells = <2>;
21	24
22	25	aliases {
	26	+ ethernet0 = &gmac2io;
	27	+ ethernet1 = &gmac2phy;
23	28	gpio0 = &gpio0;
24	29	gpio1 = &gpio1;
25	30	gpio2 = &gpio2;
26	31	gpio3 = &gpio3;
27		- serial0 = &uart0;
28		- serial1 = &uart1;
29		- serial2 = &uart2;
30	32	i2c0 = &i2c0;
31	33	i2c1 = &i2c1;
32	34	i2c2 = &i2c2;
33	35	i2c3 = &i2c3;
34		- ethernet0 = &gmac2io;
35		- ethernet1 = &gmac2phy;
	36	+ serial0 = &uart0;
	37	+ serial1 = &uart1;
	38	+ serial2 = &uart2;
36	39	};
37	40
38	41	cpus {
..	..	@@ -109,58 +112,144 @@
109	112	};
110	113	};
111	114
112		- cpu0_opp_table: opp_table0 {
	115	+ cpu0_opp_table: cpu0-opp-table {
113	116	compatible = "operating-points-v2";
114	117	opp-shared;
115	118
	119	+ rockchip,video-4k-freq = <1008000>;
	120	+
	121	+ rockchip,leakage-voltage-sel = <
	122	+ 1 10 0
	123	+ 11 254 1
	124	+ >;
	125	+ nvmem-cells = <&cpu_leakage>;
	126	+ nvmem-cell-names = "cpu_leakage";
	127	+
116	128	opp-408000000 {
117	129	opp-hz = /bits/ 64 <408000000>;
118		- opp-microvolt = <950000>;
	130	+ opp-microvolt = <950000 950000 1350000>;
	131	+ opp-microvolt-L0 = <950000 950000 1350000>;
	132	+ opp-microvolt-L1 = <950000 950000 1350000>;
119	133	clock-latency-ns = <40000>;
120	134	opp-suspend;
121	135	};
122	136	opp-600000000 {
123	137	opp-hz = /bits/ 64 <600000000>;
124		- opp-microvolt = <950000>;
	138	+ opp-microvolt = <950000 950000 1350000>;
	139	+ opp-microvolt-L0 = <950000 950000 1350000>;
	140	+ opp-microvolt-L1 = <950000 950000 1350000>;
125	141	clock-latency-ns = <40000>;
126	142	};
127	143	opp-816000000 {
128	144	opp-hz = /bits/ 64 <816000000>;
129		- opp-microvolt = <1000000>;
	145	+ opp-microvolt = <1050000 1050000 1350000>;
	146	+ opp-microvolt-L0 = <1050000 1050000 1350000>;
	147	+ opp-microvolt-L1 = <1000000 1000000 1350000>;
130	148	clock-latency-ns = <40000>;
131	149	};
132	150	opp-1008000000 {
133	151	opp-hz = /bits/ 64 <1008000000>;
134		- opp-microvolt = <1100000>;
	152	+ opp-microvolt = <1150000 1150000 1350000>;
	153	+ opp-microvolt-L0 = <1150000 1150000 1350000>;
	154	+ opp-microvolt-L1 = <1100000 1100000 1350000>;
135	155	clock-latency-ns = <40000>;
136	156	};
137	157	opp-1200000000 {
138	158	opp-hz = /bits/ 64 <1200000000>;
139		- opp-microvolt = <1225000>;
	159	+ opp-microvolt = <1275000 1275000 1350000>;
	160	+ opp-microvolt-L0 = <1275000 1275000 1350000>;
	161	+ opp-microvolt-L1 = <1225000 1225000 1350000>;
140	162	clock-latency-ns = <40000>;
141	163	};
142	164	opp-1296000000 {
143	165	opp-hz = /bits/ 64 <1296000000>;
144		- opp-microvolt = <1300000>;
	166	+ opp-microvolt = <1350000 1350000 1350000>;
	167	+ opp-microvolt-L0 = <1350000 1350000 1350000>;
	168	+ opp-microvolt-L1 = <1300000 1300000 1350000>;
145	169	clock-latency-ns = <40000>;
146	170	};
147	171	};
148	172
149		- amba: bus {
150		- compatible = "simple-bus";
151		- #address-cells = <2>;
152		- #size-cells = <2>;
153		- ranges;
	173	+ dmc: dmc {
	174	+ compatible = "rockchip,rk3328-dmc";
	175	+ devfreq-events = <&dfi>;
	176	+ clocks = <&cru SCLK_DDRCLK>;
	177	+ clock-names = "dmc_clk";
	178	+ operating-points-v2 = <&dmc_opp_table>;
	179	+ ddr_timing = <&ddr_timing>;
	180	+ upthreshold = <40>;
	181	+ downdifferential = <20>;
	182	+ system-status-freq = <
	183	+ /system status freq(KHz)/
	184	+ SYS_STATUS_NORMAL 786000
	185	+ SYS_STATUS_REBOOT 786000
	186	+ SYS_STATUS_SUSPEND 786000
	187	+ SYS_STATUS_VIDEO_1080P 786000
	188	+ SYS_STATUS_VIDEO_4K 786000
	189	+ SYS_STATUS_VIDEO_4K_10B 924000
	190	+ SYS_STATUS_PERFORMANCE 924000
	191	+ SYS_STATUS_BOOST 924000
	192	+ >;
	193	+ auto-min-freq = <786000>;
	194	+ auto-freq-en = <0>;
	195	+ #cooling-cells = <2>;
	196	+ status = "disabled";
	197	+ };
154	198
155		- dmac: dmac@ff1f0000 {
156		- compatible = "arm,pl330", "arm,primecell";
157		- reg = <0x0 0xff1f0000 0x0 0x4000>;
158		- interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
159		- <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>;
160		- arm,pl330-periph-burst;
161		- clocks = <&cru ACLK_DMAC>;
162		- clock-names = "apb_pclk";
163		- #dma-cells = <1>;
	199	+ dmc_opp_table: dmc-opp-table {
	200	+ compatible = "operating-points-v2";
	201	+ rockchip,leakage-voltage-sel = <
	202	+ 1 10 0
	203	+ 11 254 1
	204	+ >;
	205	+ nvmem-cells = <&logic_leakage>;
	206	+ nvmem-cell-names = "ddr_leakage";
	207	+
	208	+ opp-400000000 {
	209	+ opp-hz = /bits/ 64 <400000000>;
	210	+ opp-microvolt = <950000>;
	211	+ opp-microvolt-L0 = <950000>;
	212	+ opp-microvolt-L1 = <950000>;
	213	+ status = "disabled";
	214	+ };
	215	+ opp-600000000 {
	216	+ opp-hz = /bits/ 64 <600000000>;
	217	+ opp-microvolt = <1025000>;
	218	+ opp-microvolt-L0 = <1025000>;
	219	+ opp-microvolt-L1 = <1000000>;
	220	+ status = "disabled";
	221	+ };
	222	+ opp-786000000 {
	223	+ opp-hz = /bits/ 64 <786000000>;
	224	+ opp-microvolt = <1075000>;
	225	+ opp-microvolt-L0 = <1075000>;
	226	+ opp-microvolt-L1 = <1050000>;
	227	+ };
	228	+ opp-798000000 {
	229	+ opp-hz = /bits/ 64 <798000000>;
	230	+ opp-microvolt = <1075000>;
	231	+ opp-microvolt-L0 = <1075000>;
	232	+ opp-microvolt-L1 = <1050000>;
	233	+ };
	234	+ opp-840000000 {
	235	+ opp-hz = /bits/ 64 <840000000>;
	236	+ opp-microvolt = <1075000>;
	237	+ opp-microvolt-L0 = <1075000>;
	238	+ opp-microvolt-L1 = <1050000>;
	239	+ };
	240	+ opp-924000000 {
	241	+ opp-hz = /bits/ 64 <924000000>;
	242	+ opp-microvolt = <1125000>;
	243	+ opp-microvolt-L0 = <1125000>;
	244	+ opp-microvolt-L1 = <1100000>;
	245	+ };
	246	+ /* 1056M is only for ddr4 */
	247	+ opp-1056000000 {
	248	+ opp-hz = /bits/ 64 <1056000000>;
	249	+ opp-microvolt = <1175000>;
	250	+ opp-microvolt-L0 = <1175000>;
	251	+ opp-microvolt-L1 = <1150000>;
	252	+ status = "disabled";
164	253	};
165	254	};
166	255
..	..	@@ -168,8 +257,7 @@
168	257	compatible = "simple-audio-card";
169	258	simple-audio-card,format = "i2s";
170	259	simple-audio-card,mclk-fs = <256>;
171		- simple-audio-card,name = "Analog";
172		- status = "disabled";
	260	+ simple-audio-card,name = "rockchip,rk3328";
173	261
174	262	simple-audio-card,cpu {
175	263	sound-dai = <&i2s1>;
..	..	@@ -189,17 +277,37 @@
189	277	interrupt-affinity = <&cpu0>, <&cpu1>, <&cpu2>, <&cpu3>;
190	278	};
191	279
	280	+ cpuinfo {
	281	+ compatible = "rockchip,cpuinfo";
	282	+ nvmem-cells = <&efuse_id>, <&efuse_cpu_version>;
	283	+ nvmem-cell-names = "id", "cpu-version";
	284	+ };
	285	+
192	286	display_subsystem: display-subsystem {
193	287	compatible = "rockchip,display-subsystem";
194	288	ports = <&vop_out>;
	289	+ status = "disabled";
	290	+ };
	291	+
	292	+ firmware {
	293	+ optee {
	294	+ compatible = "linaro,optee-tz";
	295	+ method = "smc";
	296	+ };
	297	+ };
	298	+
	299	+ gmac_clkin: external-gmac-clock {
	300	+ compatible = "fixed-clock";
	301	+ clock-frequency = <125000000>;
	302	+ clock-output-names = "gmac_clkin";
	303	+ #clock-cells = <0>;
195	304	};
196	305
197	306	hdmi_sound: hdmi-sound {
198	307	compatible = "simple-audio-card";
199	308	simple-audio-card,format = "i2s";
200	309	simple-audio-card,mclk-fs = <128>;
201		- simple-audio-card,name = "HDMI";
202		- status = "disabled";
	310	+ simple-audio-card,name = "rockchip,hdmi";
203	311
204	312	simple-audio-card,cpu {
205	313	sound-dai = <&i2s0>;
..	..	@@ -213,6 +321,38 @@
213	321	psci {
214	322	compatible = "arm,psci-1.0", "arm,psci-0.2";
215	323	method = "smc";
	324	+ };
	325	+
	326	+ rockchip_suspend: rockchip-suspend {
	327	+ compatible = "rockchip,pm-rk3328";
	328	+ rockchip,sleep-mode-config = <0>;
	329	+ rockchip,virtual-poweroff = <0>;
	330	+ status = "disabled";
	331	+ };
	332	+
	333	+ rockchip_system_monitor: rockchip-system-monitor {
	334	+ compatible = "rockchip,system-monitor";
	335	+ rockchip,thermal-zone = "soc-thermal";
	336	+ rockchip,polling-delay = <200>; /* milliseconds */
	337	+ rockchip,video-4k-offline-cpus = "3";
	338	+ };
	339	+
	340	+ spdif_out: spdif-out {
	341	+ compatible = "linux,spdif-dit";
	342	+ #sound-dai-cells = <0>;
	343	+ };
	344	+
	345	+ spdif_sound: spdif-sound {
	346	+ compatible = "simple-audio-card";
	347	+ simple-audio-card,name = "rockchip,spdif";
	348	+
	349	+ simple-audio-card,cpu {
	350	+ sound-dai = <&spdif>;
	351	+ };
	352	+
	353	+ simple-audio-card,codec {
	354	+ sound-dai = <&spdif_out>;
	355	+ };
216	356	};
217	357
218	358	timer {
..	..	@@ -230,6 +370,13 @@
230	370	clock-output-names = "xin24m";
231	371	};
232	372
	373	+ xin32k: xin32k {
	374	+ compatible = "fixed-clock";
	375	+ clock-frequency = <32768>;
	376	+ clock-output-names = "xin32k";
	377	+ #clock-cells = <0>;
	378	+ };
	379	+
233	380	i2s0: i2s@ff000000 {
234	381	compatible = "rockchip,rk3328-i2s", "rockchip,rk3066-i2s";
235	382	reg = <0x0 0xff000000 0x0 0x1000>;
..	..	@@ -238,6 +385,8 @@
238	385	clock-names = "i2s_clk", "i2s_hclk";
239	386	dmas = <&dmac 11>, <&dmac 12>;
240	387	dma-names = "tx", "rx";
	388	+ resets = <&cru SRST_I2S0>, <&cru SRST_I2S0_H>;
	389	+ reset-names = "reset-m", "reset-h";
241	390	#sound-dai-cells = <0>;
242	391	status = "disabled";
243	392	};
..	..	@@ -250,6 +399,8 @@
250	399	clock-names = "i2s_clk", "i2s_hclk";
251	400	dmas = <&dmac 14>, <&dmac 15>;
252	401	dma-names = "tx", "rx";
	402	+ resets = <&cru SRST_I2S1>, <&cru SRST_I2S1_H>;
	403	+ reset-names = "reset-m", "reset-h";
253	404	#sound-dai-cells = <0>;
254	405	status = "disabled";
255	406	};
..	..	@@ -262,6 +413,16 @@
262	413	clock-names = "i2s_clk", "i2s_hclk";
263	414	dmas = <&dmac 0>, <&dmac 1>;
264	415	dma-names = "tx", "rx";
	416	+ resets = <&cru SRST_I2S2>, <&cru SRST_I2S2_H>;
	417	+ reset-names = "reset-m", "reset-h";
	418	+ pinctrl-names = "default", "sleep";
	419	+ pinctrl-0 = <&i2s2m0_mclk
	420	+ &i2s2m0_sclk
	421	+ &i2s2m0_lrcktx
	422	+ &i2s2m0_lrckrx
	423	+ &i2s2m0_sdo
	424	+ &i2s2m0_sdi>;
	425	+ pinctrl-1 = <&i2s2m0_sleep>;
265	426	#sound-dai-cells = <0>;
266	427	status = "disabled";
267	428	};
..	..	@@ -275,7 +436,7 @@
275	436	dmas = <&dmac 10>;
276	437	dma-names = "tx";
277	438	pinctrl-names = "default";
278		- pinctrl-0 = <&spdifm2_tx>;
	439	+ pinctrl-0 = <&spdifm0_tx>;
279	440	#sound-dai-cells = <0>;
280	441	status = "disabled";
281	442	};
..	..	@@ -289,15 +450,52 @@
289	450	dma-names = "rx";
290	451	pinctrl-names = "default", "sleep";
291	452	pinctrl-0 = <&pdmm0_clk
	453	+ &pdmm0_fsync
292	454	&pdmm0_sdi0
293	455	&pdmm0_sdi1
294	456	&pdmm0_sdi2
295	457	&pdmm0_sdi3>;
296	458	pinctrl-1 = <&pdmm0_clk_sleep
	459	+ &pdmm0_fsync_sleep
297	460	&pdmm0_sdi0_sleep
298	461	&pdmm0_sdi1_sleep
299	462	&pdmm0_sdi2_sleep
300	463	&pdmm0_sdi3_sleep>;
	464	+ status = "disabled";
	465	+ };
	466	+
	467	+ tsp: tsp@ff050000 {
	468	+ compatible = "rockchip,rk3328-tsp";
	469	+ reg = <0x0 0xff050000 0x0 0x10000>;
	470	+ rockchip,grf = <&grf>;
	471	+ interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>;
	472	+ interrupt-names = "irq_tsp";
	473	+ clocks = <&cru SCLK_TSP>, <&cru ACLK_TSP>, <&cru HCLK_TSP>;
	474	+ clock-names = "clk_tsp", "aclk_tsp", "hclk_tsp";
	475	+ pinctrl-names = "default";
	476	+ pinctrl-0 = <&tsp_d0
	477	+ &tsp_d1
	478	+ &tsp_d2
	479	+ &tsp_d3
	480	+ &tsp_d4
	481	+ &tsp_d5
	482	+ &tsp_d6
	483	+ &tsp_d7
	484	+ &tsp_sync
	485	+ &tsp_clk
	486	+ &tsp_fail
	487	+ &tsp_valid>;
	488	+ status = "disabled";
	489	+ };
	490	+
	491	+ rng: rng@ff060000 {
	492	+ compatible = "rockchip,cryptov1-rng";
	493	+ reg = <0x0 0xff060000 0x0 0x4000>;
	494	+
	495	+ clocks = <&cru SCLK_CRYPTO>, <&cru HCLK_CRYPTO_SLV>;
	496	+ clock-names = "clk_crypto", "hclk_crypto";
	497	+ assigned-clocks = <&cru SCLK_CRYPTO>, <&cru HCLK_CRYPTO_SLV>;
	498	+ assigned-clock-rates = <150000000>, <100000000>;
301	499	status = "disabled";
302	500	};
303	501
..	..	@@ -321,26 +519,88 @@
321	519	#power-domain-cells = <1>;
322	520	#address-cells = <1>;
323	521	#size-cells = <0>;
	522	+ status = "okay";
324	523
325	524	power-domain@RK3328_PD_HEVC {
326	525	reg = <RK3328_PD_HEVC>;
327	526	};
328	527	power-domain@RK3328_PD_VIDEO {
329	528	reg = <RK3328_PD_VIDEO>;
	529	+ clocks = <&cru ACLK_RKVDEC>,
	530	+ <&cru HCLK_RKVDEC>,
	531	+ <&cru SCLK_VDEC_CABAC>,
	532	+ <&cru SCLK_VDEC_CORE>;
	533	+ pm_qos = <&qos_rkvdec_r>, <&qos_rkvdec_w>;
330	534	};
331	535	power-domain@RK3328_PD_VPU {
332	536	reg = <RK3328_PD_VPU>;
333		- clocks = <&cru ACLK_VPU>, <&cru HCLK_VPU>;
	537	+ clocks = <&cru ACLK_VPU>,
	538	+ <&cru HCLK_VPU>;
	539	+ pm_qos = <&qos_vpu>;
334	540	};
335	541	};
336	542
337		- reboot-mode {
	543	+ reboot_mode: reboot-mode {
338	544	compatible = "syscon-reboot-mode";
339	545	offset = <0x5c8>;
	546	+ mode-bootloader = <BOOT_BL_DOWNLOAD>;
	547	+ mode-charge = <BOOT_CHARGING>;
	548	+ mode-fastboot = <BOOT_FASTBOOT>;
	549	+ mode-loader = <BOOT_BL_DOWNLOAD>;
340	550	mode-normal = <BOOT_NORMAL>;
341	551	mode-recovery = <BOOT_RECOVERY>;
342		- mode-bootloader = <BOOT_FASTBOOT>;
343		- mode-loader = <BOOT_BL_DOWNLOAD>;
	552	+ mode-ums = <BOOT_UMS>;
	553	+ };
	554	+ };
	555	+
	556	+ thermal-zones {
	557	+ soc_thermal: soc-thermal {
	558	+ polling-delay-passive = <20>; /* milliseconds */
	559	+ polling-delay = <1000>; /* milliseconds */
	560	+ sustainable-power = <1000>; /* milliwatts */
	561	+
	562	+ thermal-sensors = <&tsadc 0>;
	563	+
	564	+ trips {
	565	+ threshold: trip-point-0 {
	566	+ temperature = <70000>; /* millicelsius */
	567	+ hysteresis = <2000>; /* millicelsius */
	568	+ type = "passive";
	569	+ };
	570	+ target: trip-point-1 {
	571	+ temperature = <85000>; /* millicelsius */
	572	+ hysteresis = <2000>; /* millicelsius */
	573	+ type = "passive";
	574	+ };
	575	+ soc_crit: soc-crit {
	576	+ temperature = <115000>; /* millicelsius */
	577	+ hysteresis = <2000>; /* millicelsius */
	578	+ type = "critical";
	579	+ };
	580	+ };
	581	+
	582	+ cooling-maps {
	583	+ map0 {
	584	+ trip = <&target>;
	585	+ cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
	586	+ contribution = <4096>;
	587	+ };
	588	+ map1 {
	589	+ trip = <&target>;
	590	+ cooling-device = <&gpu THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
	591	+ contribution = <4096>;
	592	+ };
	593	+ map2 {
	594	+ trip = <&target>;
	595	+ cooling-device = <&rkvdec THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
	596	+ contribution = <1024>;
	597	+ };
	598	+ map3 {
	599	+ trip = <&target>;
	600	+ cooling-device = <&dmc THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
	601	+ contribution = <1024>;
	602	+ };
	603	+ };
344	604	};
345	605	};
346	606
..	..	@@ -387,6 +647,11 @@
387	647	reg-io-width = <4>;
388	648	reg-shift = <2>;
389	649	status = "disabled";
	650	+ };
	651	+
	652	+ pmu: power-management@ff140000 {
	653	+ compatible = "rockchip,rk3328-pmu", "syscon", "simple-mfd";
	654	+ reg = <0x0 0xff140000 0x0 0x1000>;
390	655	};
391	656
392	657	i2c0: i2c@ff150000 {
..	..	@@ -461,11 +726,13 @@
461	726	reg = <0x0 0xff1a0000 0x0 0x100>;
462	727	interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>;
463	728	clocks = <&cru PCLK_BUS_PRE>;
	729	+ status = "disabled";
464	730	};
465	731
466	732	pwm0: pwm@ff1b0000 {
467	733	compatible = "rockchip,rk3328-pwm";
468	734	reg = <0x0 0xff1b0000 0x0 0x10>;
	735	+ interrupts = <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>;
469	736	clocks = <&cru SCLK_PWM>, <&cru PCLK_PWM>;
470	737	clock-names = "pwm", "pclk";
471	738	pinctrl-names = "active";
..	..	@@ -477,6 +744,7 @@
477	744	pwm1: pwm@ff1b0010 {
478	745	compatible = "rockchip,rk3328-pwm";
479	746	reg = <0x0 0xff1b0010 0x0 0x10>;
	747	+ interrupts = <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>;
480	748	clocks = <&cru SCLK_PWM>, <&cru PCLK_PWM>;
481	749	clock-names = "pwm", "pclk";
482	750	pinctrl-names = "active";
..	..	@@ -488,6 +756,7 @@
488	756	pwm2: pwm@ff1b0020 {
489	757	compatible = "rockchip,rk3328-pwm";
490	758	reg = <0x0 0xff1b0020 0x0 0x10>;
	759	+ interrupts = <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>;
491	760	clocks = <&cru SCLK_PWM>, <&cru PCLK_PWM>;
492	761	clock-names = "pwm", "pclk";
493	762	pinctrl-names = "active";
..	..	@@ -508,44 +777,15 @@
508	777	status = "disabled";
509	778	};
510	779
511		- thermal-zones {
512		- soc_thermal: soc-thermal {
513		- polling-delay-passive = <20>;
514		- polling-delay = <1000>;
515		- sustainable-power = <1000>;
516		-
517		- thermal-sensors = <&tsadc 0>;
518		-
519		- trips {
520		- threshold: trip-point0 {
521		- temperature = <70000>;
522		- hysteresis = <2000>;
523		- type = "passive";
524		- };
525		- target: trip-point1 {
526		- temperature = <85000>;
527		- hysteresis = <2000>;
528		- type = "passive";
529		- };
530		- soc_crit: soc-crit {
531		- temperature = <95000>;
532		- hysteresis = <2000>;
533		- type = "critical";
534		- };
535		- };
536		-
537		- cooling-maps {
538		- map0 {
539		- trip = <&target>;
540		- cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
541		- <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
542		- <&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
543		- <&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
544		- contribution = <4096>;
545		- };
546		- };
547		- };
548		-
	780	+ dmac: dma-controller@ff1f0000 {
	781	+ compatible = "arm,pl330", "arm,primecell";
	782	+ reg = <0x0 0xff1f0000 0x0 0x4000>;
	783	+ interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
	784	+ <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>;
	785	+ arm,pl330-periph-burst;
	786	+ clocks = <&cru ACLK_DMAC>;
	787	+ clock-names = "apb_pclk";
	788	+ #dma-cells = <1>;
549	789	};
550	790
551	791	tsadc: tsadc@ff250000 {
..	..	@@ -605,7 +845,7 @@
605	845	};
606	846
607	847	gpu: gpu@ff300000 {
608		- compatible = "rockchip,rk3328-mali", "arm,mali-450";
	848	+ compatible = "arm,mali-450";
609	849	reg = <0x0 0xff300000 0x0 0x30000>;
610	850	interrupts = <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>,
611	851	<GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>,
..	..	@@ -614,26 +854,92 @@
614	854	<GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>,
615	855	<GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>,
616	856	<GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>;
617		- interrupt-names = "gp",
618		- "gpmmu",
619		- "pp",
620		- "pp0",
621		- "ppmmu0",
622		- "pp1",
623		- "ppmmu1";
624		- clocks = <&cru ACLK_GPU>, <&cru ACLK_GPU>;
625		- clock-names = "bus", "core";
	857	+ interrupt-names = "Mali_GP_IRQ",
	858	+ "Mali_GP_MMU_IRQ",
	859	+ "IRQPP",
	860	+ "Mali_PP0_IRQ",
	861	+ "Mali_PP0_MMU_IRQ",
	862	+ "Mali_PP1_IRQ",
	863	+ "Mali_PP1_MMU_IRQ";
	864	+ clocks = <&cru ACLK_GPU>;
	865	+ clock-names = "clk_mali";
	866	+ #cooling-cells = <2>; /* min followed by max */
	867	+ operating-points-v2 = <&gpu_opp_table>;
626	868	resets = <&cru SRST_GPU_A>;
	869	+ status = "disabled";
	870	+
	871	+ gpu_power_model: power_model {
	872	+ compatible = "arm,mali-simple-power-model";
	873	+ voltage = <900>;
	874	+ frequency = <500>;
	875	+ static-power = <300>;
	876	+ dynamic-power = <396>;
	877	+ ts = <32000 4700 (-80) 2>;
	878	+ thermal-zone = "soc-thermal";
	879	+ };
627	880	};
628	881
629		- h265e_mmu: iommu@ff330200 {
630		- compatible = "rockchip,iommu";
631		- reg = <0x0 0xff330200 0 0x100>;
632		- interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>;
633		- interrupt-names = "h265e_mmu";
634		- clocks = <&cru ACLK_H265>, <&cru PCLK_H265>;
635		- clock-names = "aclk", "iface";
636		- #iommu-cells = <0>;
	882	+ gpu_opp_table: gpu-opp-table {
	883	+ compatible = "operating-points-v2";
	884	+
	885	+ rockchip,leakage-voltage-sel = <
	886	+ 1 10 0
	887	+ 11 254 1
	888	+ >;
	889	+ nvmem-cells = <&logic_leakage>;
	890	+ nvmem-cell-names = "gpu_leakage";
	891	+
	892	+ opp-200000000 {
	893	+ opp-hz = /bits/ 64 <200000000>;
	894	+ opp-microvolt = <950000>;
	895	+ opp-microvolt-L0 = <950000>;
	896	+ opp-microvolt-L1 = <950000>;
	897	+ };
	898	+ opp-300000000 {
	899	+ opp-hz = /bits/ 64 <300000000>;
	900	+ opp-microvolt = <975000>;
	901	+ opp-microvolt-L0 = <975000>;
	902	+ opp-microvolt-L1 = <950000>;
	903	+ };
	904	+ opp-400000000 {
	905	+ opp-hz = /bits/ 64 <400000000>;
	906	+ opp-microvolt = <1050000>;
	907	+ opp-microvolt-L0 = <1050000>;
	908	+ opp-microvolt-L1 = <1025000>;
	909	+ };
	910	+ opp-500000000 {
	911	+ opp-hz = /bits/ 64 <500000000>;
	912	+ opp-microvolt = <1150000>;
	913	+ opp-microvolt-L0 = <1150000>;
	914	+ opp-microvolt-L1 = <1100000>;
	915	+ };
	916	+ };
	917	+
	918	+ mpp_srv: mpp-srv {
	919	+ compatible = "rockchip,mpp-service";
	920	+ rockchip,taskqueue-count = <3>;
	921	+ rockchip,resetgroup-count = <4>;
	922	+ rockchip,grf = <&grf>;
	923	+ rockchip,grf-offset = <0x040c>;
	924	+ rockchip,grf-values = <0x8000000>;
	925	+ rockchip,grf-names = "grf_vepu2";
	926	+ status = "disabled";
	927	+ };
	928	+
	929	+ vepu: vepu@ff340000 {
	930	+ compatible = "rockchip,vpu-encoder-v2";
	931	+ reg = <0x0 0xff340000 0x0 0x400>;
	932	+ interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>;
	933	+ clocks = <&cru ACLK_H264>, <&cru HCLK_H264>;
	934	+ clock-names = "aclk_vcodec", "hclk_vcodec";
	935	+ resets = <&cru SRST_RKVENC_H264_A>,
	936	+ <&cru SRST_RKVENC_H264_H>;
	937	+ reset-names = "video_a", "video_h";
	938	+ iommus = <&vepu_mmu>;
	939	+ rockchip,srv = <&mpp_srv>;
	940	+ rockchip,taskqueue-node = <0>;
	941	+ rockchip,resetgroup-node = <3>;
	942	+ power-domains = <&power RK3328_PD_HEVC>;
637	943	status = "disabled";
638	944	};
639	945
..	..	@@ -642,21 +948,28 @@
642	948	reg = <0x0 0xff340800 0x0 0x40>;
643	949	interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>;
644	950	interrupt-names = "vepu_mmu";
645		- clocks = <&cru ACLK_VPU>, <&cru HCLK_VPU>;
	951	+ clocks = <&cru ACLK_H264>, <&cru HCLK_H264>;
646	952	clock-names = "aclk", "iface";
	953	+ power-domains = <&power RK3328_PD_HEVC>;
647	954	#iommu-cells = <0>;
648	955	status = "disabled";
649	956	};
650	957
651		- vpu: video-codec@ff350000 {
652		- compatible = "rockchip,rk3328-vpu";
653		- reg = <0x0 0xff350000 0x0 0x800>;
	958	+ vdpu: vdpu@ff350000 {
	959	+ compatible = "rockchip,vpu-decoder-v2";
	960	+ reg = <0x0 0xff350400 0x0 0x400>;
654	961	interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
655		- interrupt-names = "vdpu";
	962	+ interrupt-names = "irq_dec";
656	963	clocks = <&cru ACLK_VPU>, <&cru HCLK_VPU>;
657		- clock-names = "aclk", "hclk";
	964	+ clock-names = "aclk_vcodec", "hclk_vcodec";
	965	+ resets = <&cru SRST_VCODEC_A>, <&cru SRST_VCODEC_H>;
	966	+ reset-names = "shared_video_a", "shared_video_h";
658	967	iommus = <&vpu_mmu>;
659	968	power-domains = <&power RK3328_PD_VPU>;
	969	+ rockchip,srv = <&mpp_srv>;
	970	+ rockchip,taskqueue-node = <0>;
	971	+ rockchip,resetgroup-node = <0>;
	972	+ status = "disabled";
660	973	};
661	974
662	975	vpu_mmu: iommu@ff350800 {
..	..	@@ -668,6 +981,90 @@
668	981	clock-names = "aclk", "iface";
669	982	#iommu-cells = <0>;
670	983	power-domains = <&power RK3328_PD_VPU>;
	984	+ status = "disabled";
	985	+ };
	986	+
	987	+ avsd: avsd_plus@ff351000 {
	988	+ compatible = "rockchip,avs-plus-decoder";
	989	+ reg = <0x0 0xff351000 0x0 0x200>;
	990	+ interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
	991	+ interrupt-names = "irq_dec";
	992	+ clocks = <&cru ACLK_VPU>, <&cru HCLK_VPU>;
	993	+ clock-names = "aclk_vcodec", "hclk_vcodec";
	994	+ resets = <&cru SRST_VCODEC_A>, <&cru SRST_VCODEC_H>;
	995	+ reset-names = "shared_video_a", "shared_video_h";
	996	+ iommus = <&vpu_mmu>;
	997	+ power-domains = <&power RK3328_PD_VPU>;
	998	+ rockchip,srv = <&mpp_srv>;
	999	+ rockchip,taskqueue-node = <0>;
	1000	+ rockchip,resetgroup-node = <0>;
	1001	+ status = "disabled";
	1002	+ };
	1003	+
	1004	+ rkvdec: rkvdec@ff36000 {
	1005	+ compatible = "rockchip,rkv-decoder-rk3328", "rockchip,rkv-decoder-v2";
	1006	+ reg = <0x0 0xff360000 0x0 0x400>;
	1007	+ interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>;
	1008	+ interrupt-names = "irq_dec";
	1009	+ clocks = <&cru ACLK_RKVDEC>, <&cru HCLK_RKVDEC>,
	1010	+ <&cru SCLK_VDEC_CABAC>, <&cru SCLK_VDEC_CORE>;
	1011	+ clock-names = "aclk_vcodec", "hclk_vcodec", "clk_cabac",
	1012	+ "clk_core";
	1013	+ rockchip,normal-rates = <300000000>, <0>, <300000000>, <300000000>;
	1014	+ rockchip,advanced-rates = <400000000>, <0>, <400000000>, <300000000>;
	1015	+ rockchip,default-max-load = <2088960>;
	1016	+ resets = <&cru SRST_VDEC_A>, <&cru SRST_VDEC_H>,
	1017	+ <&cru SRST_VDEC_NIU_A>, <&cru SRST_VDEC_NIU_H>,
	1018	+ <&cru SRST_VDEC_CABAC>, <&cru SRST_VDEC_CORE>;
	1019	+ reset-names = "video_a", "video_h", "niu_a", "niu_h",
	1020	+ "video_cabac", "video_core";
	1021	+ iommus = <&rkvdec_mmu>;
	1022	+ rockchip,srv = <&mpp_srv>;
	1023	+ rockchip,taskqueue-node = <1>;
	1024	+ rockchip,resetgroup-node = <1>;
	1025	+ power-domains = <&power RK3328_PD_VIDEO>;
	1026	+ operating-points-v2 = <&rkvdec_opp_table>;
	1027	+ #cooling-cells = <2>;
	1028	+ devfreq = <&dmc>;
	1029	+ status = "disabled";
	1030	+
	1031	+ vcodec_power_model: vcodec_power_model {
	1032	+ compatible = "vcodec_power_model";
	1033	+ dynamic-power-coefficient = <120>;
	1034	+ static-power-coefficient = <200>;
	1035	+ ts = <32000 4700 (-80) 2>;
	1036	+ thermal-zone = "soc-thermal";
	1037	+ };
	1038	+ };
	1039	+
	1040	+ rkvdec_opp_table: rkvdec-opp-table {
	1041	+ compatible = "operating-points-v2";
	1042	+
	1043	+ rockchip,leakage-voltage-sel = <
	1044	+ 1 10 0
	1045	+ 11 254 1
	1046	+ >;
	1047	+ nvmem-cells = <&logic_leakage>;
	1048	+ nvmem-cell-names = "rkvdec_leakage";
	1049	+
	1050	+ opp-100000000 {
	1051	+ opp-hz = /bits/ 64 <100000000>;
	1052	+ opp-microvolt = <975000>;
	1053	+ opp-microvolt-L0 = <975000>;
	1054	+ opp-microvolt-L1 = <950000>;
	1055	+ };
	1056	+ opp-200000000 {
	1057	+ opp-hz = /bits/ 64 <200000000>;
	1058	+ opp-microvolt = <975000>;
	1059	+ opp-microvolt-L0 = <975000>;
	1060	+ opp-microvolt-L1 = <950000>;
	1061	+ };
	1062	+ opp-500000000 {
	1063	+ opp-hz = /bits/ 64 <500000000>;
	1064	+ opp-microvolt = <1075000>;
	1065	+ opp-microvolt-L0 = <1075000>;
	1066	+ opp-microvolt-L1 = <1050000>;
	1067	+ };
671	1068	};
672	1069
673	1070	rkvdec_mmu: iommu@ff360480 {
..	..	@@ -678,6 +1075,7 @@
678	1075	clocks = <&cru ACLK_RKVDEC>, <&cru HCLK_RKVDEC>;
679	1076	clock-names = "aclk", "iface";
680	1077	#iommu-cells = <0>;
	1078	+ power-domains = <&power RK3328_PD_VIDEO>;
681	1079	status = "disabled";
682	1080	};
683	1081
..	..	@@ -687,6 +1085,8 @@
687	1085	interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
688	1086	clocks = <&cru ACLK_VOP>, <&cru DCLK_LCDC>, <&cru HCLK_VOP>;
689	1087	clock-names = "aclk_vop", "dclk_vop", "hclk_vop";
	1088	+ assigned-clocks = <&cru DCLK_LCDC>;
	1089	+ assigned-clock-parents = <&cru HDMIPHY>;
690	1090	resets = <&cru SRST_VOP_A>, <&cru SRST_VOP_H>, <&cru SRST_VOP_D>;
691	1091	reset-names = "axi", "ahb", "dclk";
692	1092	iommus = <&vop_mmu>;
..	..	@@ -700,6 +1100,36 @@
700	1100	reg = <0>;
701	1101	remote-endpoint = <&hdmi_in_vop>;
702	1102	};
	1103	+ vop_out_tve: endpoint@1 {
	1104	+ reg = <1>;
	1105	+ remote-endpoint = <&tve_in_vop>;
	1106	+ };
	1107	+ };
	1108	+ };
	1109	+
	1110	+ tve: tve@ff373e00 {
	1111	+ compatible = "rockchip,rk3328-tve";
	1112	+ reg = <0x0 0xff373e00 0x0 0x100>,
	1113	+ <0x0 0xff420000 0x0 0x10000>;
	1114	+ rockchip,saturation = <0x00376749>;
	1115	+ rockchip,brightcontrast = <0x0000a305>;
	1116	+ rockchip,adjtiming = <0xb6c00880>;
	1117	+ rockchip,lumafilter0 = <0x01ff0000>;
	1118	+ rockchip,lumafilter1 = <0xf40200fe>;
	1119	+ rockchip,lumafilter2 = <0xf332d70c>;
	1120	+ rockchip,daclevel = <0x22>;
	1121	+ rockchip,dac1level = <0x7>;
	1122	+ status = "disabled";
	1123	+
	1124	+ ports {
	1125	+ tve_in: port {
	1126	+ #address-cells = <1>;
	1127	+ #size-cells = <0>;
	1128	+ tve_in_vop: endpoint@0 {
	1129	+ reg = <0>;
	1130	+ remote-endpoint = <&vop_out_tve>;
	1131	+ };
	1132	+ };
703	1133	};
704	1134	};
705	1135
..	..	@@ -710,6 +1140,53 @@
710	1140	interrupt-names = "vop_mmu";
711	1141	clocks = <&cru ACLK_VOP>, <&cru HCLK_VOP>;
712	1142	clock-names = "aclk", "iface";
	1143	+ #iommu-cells = <0>;
	1144	+ status = "disabled";
	1145	+ };
	1146	+
	1147	+ cif: cif@ff380000 {
	1148	+ compatible = "rockchip,cif", "rockchip,rk3328-cif";
	1149	+ reg = <0x0 0xff380000 0x0 0x400>;
	1150	+ interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>;
	1151	+ clocks = <&cru ACLK_CIF>, <&cru HCLK_CIF>;
	1152	+ clock-names = "aclk_cif", "hclk_cif";
	1153	+ resets = <&cru SRST_CIF_A>, <&cru SRST_CIF_H>, <&cru SRST_CIF_P>;
	1154	+ reset-names = "rst_cif_a", "rst_cif_h", "rst_cif_p";
	1155	+ status = "disabled";
	1156	+ };
	1157	+
	1158	+ rga: rga@ff3900000 {
	1159	+ compatible = "rockchip,rga2";
	1160	+ dev_mode = <1>;
	1161	+ reg = <0x0 0xff390000 0x0 0x1000>;
	1162	+ interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
	1163	+ clocks = <&cru ACLK_RGA>, <&cru HCLK_RGA>, <&cru SCLK_RGA>;
	1164	+ clock-names = "aclk_rga", "hclk_rga", "clk_rga";
	1165	+ status = "disabled";
	1166	+ };
	1167	+
	1168	+ iep: iep@ff3a0000 {
	1169	+ compatible = "rockchip,iep";
	1170	+ iommu_enabled = <1>;
	1171	+ iommus = <&iep_mmu>;
	1172	+ reg = <0x0 0xff3a0000 0x0 0x800>;
	1173	+ interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>;
	1174	+ clocks = <&cru ACLK_IEP>, <&cru HCLK_IEP>;
	1175	+ clock-names = "aclk_iep", "hclk_iep";
	1176	+ power-domains = <&power RK3328_PD_VIDEO>;
	1177	+ allocator = <1>;
	1178	+ version = <2>;
	1179	+ status = "disabled";
	1180	+ };
	1181	+
	1182	+ iep_mmu: iommu@ff3a0800 {
	1183	+ compatible = "rockchip,iommu";
	1184	+ reg = <0x0 0xff3a0800 0x0 0x40>;
	1185	+ interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>;
	1186	+ interrupt-names = "iep_mmu";
	1187	+ clocks = <&cru ACLK_IEP>, <&cru HCLK_IEP>;
	1188	+ clock-names = "aclk", "hclk";
	1189	+ power-domains = <&power RK3328_PD_VIDEO>;
713	1190	#iommu-cells = <0>;
714	1191	status = "disabled";
715	1192	};
..	..	@@ -728,15 +1205,23 @@
728	1205	"cec";
729	1206	phys = <&hdmiphy>;
730	1207	phy-names = "hdmi";
731		- pinctrl-names = "default";
	1208	+ pinctrl-names = "default", "pin";
732	1209	pinctrl-0 = <&hdmi_cec &hdmii2c_xfer &hdmi_hpd>;
	1210	+ pinctrl-1 = <&i2c3_pins>;
	1211	+ resets = <&cru SRST_HDMI_P>,
	1212	+ <&cru SRST_HDMIPHY>;
	1213	+ reset-names = "hdmi",
	1214	+ "hdmiphy";
733	1215	rockchip,grf = <&grf>;
734	1216	#sound-dai-cells = <0>;
735	1217	status = "disabled";
736	1218
737	1219	ports {
738	1220	hdmi_in: port {
739		- hdmi_in_vop: endpoint {
	1221	+ #address-cells = <1>;
	1222	+ #size-cells = <0>;
	1223	+ hdmi_in_vop: endpoint@0 {
	1224	+ reg = <0>;
740	1225	remote-endpoint = <&vop_out_hdmi>;
741	1226	};
742	1227	};
..	..	@@ -758,7 +1243,7 @@
758	1243	reg = <0x0 0xff430000 0x0 0x10000>;
759	1244	interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
760	1245	clocks = <&cru PCLK_HDMIPHY>, <&xin24m>, <&cru DCLK_HDMIPHY>;
761		- clock-names = "sysclk", "refoclk", "refpclk";
	1246	+ clock-names = "sysclk", "refclk", "refpclk";
762	1247	clock-output-names = "hdmi_phy";
763	1248	#clock-cells = <0>;
764	1249	nvmem-cells = <&efuse_cpu_version>;
..	..	@@ -856,6 +1341,47 @@
856	1341	};
857	1342	};
858	1343
	1344	+ usb3phy_grf: syscon@ff460000 {
	1345	+ compatible = "rockchip,usb3phy-grf", "syscon";
	1346	+ reg = <0x0 0xff460000 0x0 0x1000>;
	1347	+ };
	1348	+
	1349	+ u3phy: usb3-phy@ff470000 {
	1350	+ compatible = "rockchip,rk3328-u3phy";
	1351	+ reg = <0x0 0xff470000 0x0 0x0>;
	1352	+ rockchip,u3phygrf = <&usb3phy_grf>;
	1353	+ rockchip,grf = <&grf>;
	1354	+ interrupts = <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>;
	1355	+ interrupt-names = "linestate";
	1356	+ clocks = <&cru PCLK_USB3PHY_OTG>, <&cru PCLK_USB3PHY_PIPE>;
	1357	+ clock-names = "u3phy-otg", "u3phy-pipe";
	1358	+ resets = <&cru SRST_USB3PHY_U2>,
	1359	+ <&cru SRST_USB3PHY_U3>,
	1360	+ <&cru SRST_USB3PHY_PIPE>,
	1361	+ <&cru SRST_USB3OTG_UTMI>,
	1362	+ <&cru SRST_USB3PHY_OTG_P>,
	1363	+ <&cru SRST_USB3PHY_PIPE_P>;
	1364	+ reset-names = "u3phy-u2-por", "u3phy-u3-por",
	1365	+ "u3phy-pipe-mac", "u3phy-utmi-mac",
	1366	+ "u3phy-utmi-apb", "u3phy-pipe-apb";
	1367	+ #address-cells = <2>;
	1368	+ #size-cells = <2>;
	1369	+ ranges;
	1370	+ status = "disabled";
	1371	+
	1372	+ u3phy_utmi: utmi@ff470000 {
	1373	+ reg = <0x0 0xff470000 0x0 0x8000>;
	1374	+ #phy-cells = <0>;
	1375	+ status = "disabled";
	1376	+ };
	1377	+
	1378	+ u3phy_pipe: pipe@ff478000 {
	1379	+ reg = <0x0 0xff478000 0x0 0x8000>;
	1380	+ #phy-cells = <0>;
	1381	+ status = "disabled";
	1382	+ };
	1383	+ };
	1384	+
859	1385	sdmmc: mmc@ff500000 {
860	1386	compatible = "rockchip,rk3328-dw-mshc", "rockchip,rk3288-dw-mshc";
861	1387	reg = <0x0 0xff500000 0x0 0x4000>;
..	..	@@ -930,8 +1456,6 @@
930	1456	reset-names = "stmmaceth", "mac-phy";
931	1457	phy-mode = "rmii";
932	1458	phy-handle = <&phy>;
933		- snps,txpbl = <0x4>;
934		- clock_in_out = "output";
935	1459	status = "disabled";
936	1460
937	1461	mdio {
..	..	@@ -956,8 +1480,8 @@
956	1480	"snps,dwc2";
957	1481	reg = <0x0 0xff580000 0x0 0x40000>;
958	1482	interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;
959		- clocks = <&cru HCLK_OTG>;
960		- clock-names = "otg";
	1483	+ clocks = <&cru HCLK_OTG>, <&cru HCLK_OTG_PMU>;
	1484	+ clock-names = "otg", "otg_pmu";
961	1485	dr_mode = "otg";
962	1486	g-np-tx-fifo-size = <16>;
963	1487	g-rx-fifo-size = <280>;
..	..	@@ -971,7 +1495,9 @@
971	1495	compatible = "generic-ehci";
972	1496	reg = <0x0 0xff5c0000 0x0 0x10000>;
973	1497	interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>;
974		- clocks = <&cru HCLK_HOST0>, <&u2phy>;
	1498	+ clocks = <&cru HCLK_HOST0>, <&cru HCLK_HOST0_ARB>,
	1499	+ <&u2phy>;
	1500	+ clock-names = "usbhost", "arbiter", "utmi";
975	1501	phys = <&u2phy_host>;
976	1502	phy-names = "usb";
977	1503	status = "disabled";
..	..	@@ -981,30 +1507,76 @@
981	1507	compatible = "generic-ohci";
982	1508	reg = <0x0 0xff5d0000 0x0 0x10000>;
983	1509	interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
984		- clocks = <&cru HCLK_HOST0>, <&u2phy>;
	1510	+ clocks = <&cru HCLK_HOST0>, <&cru HCLK_HOST0_ARB>,
	1511	+ <&u2phy>;
	1512	+ clock-names = "usbhost", "arbiter", "utmi";
985	1513	phys = <&u2phy_host>;
986	1514	phy-names = "usb";
987	1515	status = "disabled";
988	1516	};
989	1517
990		- usbdrd3: usb@ff600000 {
	1518	+ sdmmc_ext: mmc@ff5f0000 {
	1519	+ compatible = "rockchip,rk3328-dw-mshc", "rockchip,rk3288-dw-mshc";
	1520	+ reg = <0x0 0xff5f0000 0x0 0x4000>;
	1521	+ clock-freq-min-max = <400000 150000000>;
	1522	+ clocks = <&cru HCLK_SDMMC_EXT>, <&cru SCLK_SDMMC_EXT>,
	1523	+ <&cru SCLK_SDMMC_EXT_DRV>, <&cru SCLK_SDMMC_EXT_SAMPLE>;
	1524	+ clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
	1525	+ fifo-depth = <0x100>;
	1526	+ interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>;
	1527	+ status = "disabled";
	1528	+ };
	1529	+
	1530	+ usbdrd3: usbdrd {
991	1531	compatible = "rockchip,rk3328-dwc3", "snps,dwc3";
992		- reg = <0x0 0xff600000 0x0 0x100000>;
993		- interrupts = <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>;
994	1532	clocks = <&cru SCLK_USB3OTG_REF>, <&cru SCLK_USB3OTG_SUSPEND>,
995	1533	<&cru ACLK_USB3OTG>;
996	1534	clock-names = "ref_clk", "suspend_clk",
997	1535	"bus_clk";
998		- dr_mode = "otg";
999		- phy_type = "utmi_wide";
1000		- snps,dis-del-phy-power-chg-quirk;
1001		- snps,dis_enblslpm_quirk;
1002		- snps,dis-tx-ipgap-linecheck-quirk;
1003		- snps,dis-u2-freeclk-exists-quirk;
1004		- snps,dis_u2_susphy_quirk;
1005		- snps,dis_u3_susphy_quirk;
1006		- snps,parkmode-disable-hs-quirk;
1007		- snps,parkmode-disable-ss-quirk;
	1536	+ #address-cells = <2>;
	1537	+ #size-cells = <2>;
	1538	+ ranges;
	1539	+ status = "disabled";
	1540	+
	1541	+ usbdrd_dwc3: dwc3@ff600000 {
	1542	+ compatible = "snps,dwc3";
	1543	+ reg = <0x0 0xff600000 0x0 0x100000>;
	1544	+ interrupts = <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>;
	1545	+ dr_mode = "host";
	1546	+ phys = <&u3phy_utmi>, <&u3phy_pipe>;
	1547	+ phy-names = "usb2-phy", "usb3-phy";
	1548	+ phy_type = "utmi_wide";
	1549	+ snps,dis-del-phy-power-chg-quirk;
	1550	+ snps,dis_enblslpm_quirk;
	1551	+ snps,dis-tx-ipgap-linecheck-quirk;
	1552	+ snps,dis-u2-freeclk-exists-quirk;
	1553	+ snps,dis_u2_susphy_quirk;
	1554	+ snps,dis_u3_susphy_quirk;
	1555	+ snps,parkmode-disable-hs-quirk;
	1556	+ snps,parkmode-disable-ss-quirk;
	1557	+ status = "disabled";
	1558	+ };
	1559	+ };
	1560	+
	1561	+ qos_rkvdec_r: qos@ff750000 {
	1562	+ compatible = "syscon";
	1563	+ reg = <0x0 0xff750000 0x0 0x20>;
	1564	+ };
	1565	+
	1566	+ qos_rkvdec_w: qos@ff750080 {
	1567	+ compatible = "syscon";
	1568	+ reg = <0x0 0xff750080 0x0 0x20>;
	1569	+ };
	1570	+
	1571	+ qos_vpu: qos@ff778000 {
	1572	+ compatible = "syscon";
	1573	+ reg = <0x0 0xff778000 0x0 0x20>;
	1574	+ };
	1575	+
	1576	+ dfi: dfi@ff790000 {
	1577	+ compatible = "rockchip,rk3328-dfi";
	1578	+ reg = <0x00 0xff790000 0x00 0x400>;
	1579	+ rockchip,grf = <&grf>;
1008	1580	status = "disabled";
1009	1581	};
1010	1582
..	..	@@ -1028,7 +1600,7 @@
1028	1600	#size-cells = <2>;
1029	1601	ranges;
1030	1602
1031		- gpio0: gpio0@ff210000 {
	1603	+ gpio0: gpio@ff210000 {
1032	1604	compatible = "rockchip,gpio-bank";
1033	1605	reg = <0x0 0xff210000 0x0 0x100>;
1034	1606	interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>;
..	..	@@ -1041,7 +1613,7 @@
1041	1613	#interrupt-cells = <2>;
1042	1614	};
1043	1615
1044		- gpio1: gpio1@ff220000 {
	1616	+ gpio1: gpio@ff220000 {
1045	1617	compatible = "rockchip,gpio-bank";
1046	1618	reg = <0x0 0xff220000 0x0 0x100>;
1047	1619	interrupts = <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>;
..	..	@@ -1054,7 +1626,7 @@
1054	1626	#interrupt-cells = <2>;
1055	1627	};
1056	1628
1057		- gpio2: gpio2@ff230000 {
	1629	+ gpio2: gpio@ff230000 {
1058	1630	compatible = "rockchip,gpio-bank";
1059	1631	reg = <0x0 0xff230000 0x0 0x100>;
1060	1632	interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>;
..	..	@@ -1067,7 +1639,7 @@
1067	1639	#interrupt-cells = <2>;
1068	1640	};
1069	1641
1070		- gpio3: gpio3@ff240000 {
	1642	+ gpio3: gpio@ff240000 {
1071	1643	compatible = "rockchip,gpio-bank";
1072	1644	reg = <0x0 0xff240000 0x0 0x100>;
1073	1645	interrupts = <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>;
..	..	@@ -1187,6 +1759,45 @@
1187	1759	};
1188	1760	};
1189	1761
	1762	+ tsp {
	1763	+ tsp_d0: tsp-d0 {
	1764	+ rockchip,pins = <3 RK_PA4 1 &pcfg_pull_none>;
	1765	+ };
	1766	+ tsp_d1: tsp-d1 {
	1767	+ rockchip,pins = <3 RK_PA5 1 &pcfg_pull_none>;
	1768	+ };
	1769	+ tsp_d2: tsp-d2 {
	1770	+ rockchip,pins = <3 RK_PA6 1 &pcfg_pull_none>;
	1771	+ };
	1772	+ tsp_d3: tsp-d3 {
	1773	+ rockchip,pins = <3 RK_PA7 1 &pcfg_pull_none>;
	1774	+ };
	1775	+ tsp_d4: tsp-d4 {
	1776	+ rockchip,pins = <3 RK_PB0 1 &pcfg_pull_none>;
	1777	+ };
	1778	+ tsp_d5: tsp-d5 {
	1779	+ rockchip,pins = <2 RK_PC0 3 &pcfg_pull_none>;
	1780	+ };
	1781	+ tsp_d6: tsp-d6 {
	1782	+ rockchip,pins = <2 RK_PC1 3 &pcfg_pull_none>;
	1783	+ };
	1784	+ tsp_d7: tsp-d7 {
	1785	+ rockchip,pins = <2 RK_PC2 3 &pcfg_pull_none>;
	1786	+ };
	1787	+ tsp_sync: tsp-sync {
	1788	+ rockchip,pins = <2 RK_PB7 3 &pcfg_pull_none>;
	1789	+ };
	1790	+ tsp_clk: tsp-clk {
	1791	+ rockchip,pins = <3 RK_PA2 1 &pcfg_pull_none>;
	1792	+ };
	1793	+ tsp_fail: tsp-fail {
	1794	+ rockchip,pins = <3 RK_PA1 1 &pcfg_pull_none>;
	1795	+ };
	1796	+ tsp_valid: tsp-valid {
	1797	+ rockchip,pins = <3 RK_PA0 1 &pcfg_pull_none>;
	1798	+ };
	1799	+ };
	1800	+
1190	1801	hdmi_i2c {
1191	1802	hdmii2c_xfer: hdmii2c-xfer {
1192	1803	rockchip,pins = <0 RK_PA5 1 &pcfg_pull_none>,
..	..	@@ -1262,7 +1873,7 @@
1262	1873
1263	1874	uart0 {
1264	1875	uart0_xfer: uart0-xfer {
1265		- rockchip,pins = <1 RK_PB1 1 &pcfg_pull_none>,
	1876	+ rockchip,pins = <1 RK_PB1 1 &pcfg_pull_up>,
1266	1877	<1 RK_PB0 1 &pcfg_pull_up>;
1267	1878	};
1268	1879
..	..	@@ -1281,7 +1892,7 @@
1281	1892
1282	1893	uart1 {
1283	1894	uart1_xfer: uart1-xfer {
1284		- rockchip,pins = <3 RK_PA4 4 &pcfg_pull_none>,
	1895	+ rockchip,pins = <3 RK_PA4 4 &pcfg_pull_up>,
1285	1896	<3 RK_PA6 4 &pcfg_pull_up>;
1286	1897	};
1287	1898
..	..	@@ -1300,14 +1911,14 @@
1300	1911
1301	1912	uart2-0 {
1302	1913	uart2m0_xfer: uart2m0-xfer {
1303		- rockchip,pins = <1 RK_PA0 2 &pcfg_pull_none>,
	1914	+ rockchip,pins = <1 RK_PA0 2 &pcfg_pull_up>,
1304	1915	<1 RK_PA1 2 &pcfg_pull_up>;
1305	1916	};
1306	1917	};
1307	1918
1308	1919	uart2-1 {
1309	1920	uart2m1_xfer: uart2m1-xfer {
1310		- rockchip,pins = <2 RK_PA0 1 &pcfg_pull_none>,
	1921	+ rockchip,pins = <2 RK_PA0 1 &pcfg_pull_up>,
1311	1922	<2 RK_PA1 1 &pcfg_pull_up>;
1312	1923	};
1313	1924	};
..	..	@@ -1709,11 +2320,17 @@
1709	2320	pwm0_pin: pwm0-pin {
1710	2321	rockchip,pins = <2 RK_PA4 1 &pcfg_pull_none>;
1711	2322	};
	2323	+ pwm0_pin_pull_up: pwm0-pin-pull-up {
	2324	+ rockchip,pins = <2 RK_PA4 1 &pcfg_pull_up>;
	2325	+ };
1712	2326	};
1713	2327
1714	2328	pwm1 {
1715	2329	pwm1_pin: pwm1-pin {
1716	2330	rockchip,pins = <2 RK_PA5 1 &pcfg_pull_none>;
	2331	+ };
	2332	+ pwm1_pin_pull_up: pwm1-pin-pull-up {
	2333	+ rockchip,pins = <2 RK_PA5 1 &pcfg_pull_up>;
1717	2334	};
1718	2335	};
1719	2336
..	..	@@ -1822,10 +2439,26 @@
1822	2439	rockchip,pins = <0 RK_PD6 1 &pcfg_pull_none>;
1823	2440	};
1824	2441
	2442	+ fephyled_speed100: fephyled-speed100 {
	2443	+ rockchip,pins = <0 RK_PD7 1 &pcfg_pull_none>;
	2444	+ };
	2445	+
1825	2446	fephyled_duplex: fephyled-duplex {
1826	2447	rockchip,pins = <0 RK_PD6 2 &pcfg_pull_none>;
1827	2448	};
1828	2449
	2450	+ fephyled_rxm0: fephyled-rxm0 {
	2451	+ rockchip,pins = <0 RK_PD5 1 &pcfg_pull_none>;
	2452	+ };
	2453	+
	2454	+ fephyled_txm0: fephyled-txm0 {
	2455	+ rockchip,pins = <0 RK_PD5 2 &pcfg_pull_none>;
	2456	+ };
	2457	+
	2458	+ fephyled_linkm0: fephyled-linkm0 {
	2459	+ rockchip,pins = <0 RK_PD4 1 &pcfg_pull_none>;
	2460	+ };
	2461	+
1829	2462	fephyled_rxm1: fephyled-rxm1 {
1830	2463	rockchip,pins = <2 RK_PD1 2 &pcfg_pull_none>;
1831	2464	};