~hc/RK356X_SDK_RELEASE.git

..	..	@@ -1,7 +1,7 @@
	1	+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
1	2	/*
2		- * Copyright (c) 2017 Fuzhou Rockchip Electronics Co., Ltd
	3	+ * Copyright (c) 2019 Fuzhou Rockchip Electronics Co., Ltd
3	4	*
4		- * SPDX-License-Identifier: (GPL-2.0+ OR MIT)
5	5	*/
6	6
7	7	#include <dt-bindings/clock/rk3308-cru.h>
..	..	@@ -23,6 +23,11 @@
23	23
24	24	aliases {
25	25	ethernet0 = &mac;
	26	+ gpio0 = &gpio0;
	27	+ gpio1 = &gpio1;
	28	+ gpio2 = &gpio2;
	29	+ gpio3 = &gpio3;
	30	+ gpio4 = &gpio4;
26	31	i2c0 = &i2c0;
27	32	i2c1 = &i2c1;
28	33	i2c2 = &i2c2;
..	..	@@ -43,13 +48,13 @@
43	48
44	49	cpu0: cpu@0 {
45	50	device_type = "cpu";
46		- compatible = "arm,cortex-a35", "arm,armv8";
	51	+ compatible = "arm,cortex-a35";
47	52	reg = <0x0 0x0>;
48	53	enable-method = "psci";
49	54	clocks = <&cru ARMCLK>;
50	55	#cooling-cells = <2>;
51	56	dynamic-power-coefficient = <83>;
52		- operating-points-v2 = <&cpu0_opp_table>;
	57	+ operating-points-v2 = <&cpu0_opp_table>, <&rk3308bs_cpu0_opp_table>;
53	58	cpu-idle-states = <&CPU_SLEEP>;
54	59	next-level-cache = <&l2>;
55	60	power-model {
..	..	@@ -64,30 +69,30 @@
64	69
65	70	cpu1: cpu@1 {
66	71	device_type = "cpu";
67		- compatible = "arm,cortex-a35", "arm,armv8";
	72	+ compatible = "arm,cortex-a35";
68	73	reg = <0x0 0x1>;
69	74	enable-method = "psci";
70		- operating-points-v2 = <&cpu0_opp_table>;
	75	+ operating-points-v2 = <&cpu0_opp_table>, <&rk3308bs_cpu0_opp_table>;
71	76	cpu-idle-states = <&CPU_SLEEP>;
72	77	next-level-cache = <&l2>;
73	78	};
74	79
75	80	cpu2: cpu@2 {
76	81	device_type = "cpu";
77		- compatible = "arm,cortex-a35", "arm,armv8";
	82	+ compatible = "arm,cortex-a35";
78	83	reg = <0x0 0x2>;
79	84	enable-method = "psci";
80		- operating-points-v2 = <&cpu0_opp_table>;
	85	+ operating-points-v2 = <&cpu0_opp_table>, <&rk3308bs_cpu0_opp_table>;
81	86	cpu-idle-states = <&CPU_SLEEP>;
82	87	next-level-cache = <&l2>;
83	88	};
84	89
85	90	cpu3: cpu@3 {
86	91	device_type = "cpu";
87		- compatible = "arm,cortex-a35", "arm,armv8";
	92	+ compatible = "arm,cortex-a35";
88	93	reg = <0x0 0x3>;
89	94	enable-method = "psci";
90		- operating-points-v2 = <&cpu0_opp_table>;
	95	+ operating-points-v2 = <&cpu0_opp_table>, <&rk3308bs_cpu0_opp_table>;
91	96	cpu-idle-states = <&CPU_SLEEP>;
92	97	next-level-cache = <&l2>;
93	98	};
..	..	@@ -117,7 +122,7 @@
117	122	rockchip,temp-hysteresis = <5000>;
118	123	rockchip,low-temp = <0>;
119	124	rockchip,low-temp-min-volt = <1000000>;
120		- rockchip,max-volt = <1340000>;
	125	+ rockchip,max-volt = <1325000>;
121	126	rockchip,low-temp-adjust-volt = <
122	127	/* MHz MHz uV */
123	128	0 1296 50000
..	..	@@ -147,65 +152,112 @@
147	152
148	153	opp-408000000 {
149	154	opp-hz = /bits/ 64 <408000000>;
150		- opp-microvolt = <950000 950000 1340000>;
	155	+ opp-microvolt = <950000 950000 1325000>;
151	156	clock-latency-ns = <40000>;
152	157	opp-suspend;
153	158	};
154	159	opp-600000000 {
155	160	opp-hz = /bits/ 64 <600000000>;
156		- opp-microvolt = <950000 950000 1340000>;
	161	+ opp-microvolt = <950000 950000 1325000>;
157	162	clock-latency-ns = <40000>;
158	163	};
159	164	opp-816000000 {
160	165	opp-hz = /bits/ 64 <816000000>;
161		- opp-microvolt = <1025000 1025000 1340000>;
162		- opp-microvolt-L0 = <1025000 1025000 1340000>;
163		- opp-microvolt-L1 = <1025000 1025000 1340000>;
164		- opp-microvolt-L2 = <1025000 1025000 1340000>;
165		- opp-microvolt-L3 = <1000000 1000000 1340000>;
166		- opp-microvolt-L4 = <975000 975000 1340000>;
167		- opp-microvolt-L5 = <950000 950000 1340000>;
	166	+ opp-microvolt = <1025000 1025000 1325000>;
	167	+ opp-microvolt-L0 = <1025000 1025000 1325000>;
	168	+ opp-microvolt-L1 = <1025000 1025000 1325000>;
	169	+ opp-microvolt-L2 = <1025000 1025000 1325000>;
	170	+ opp-microvolt-L3 = <1000000 1000000 1325000>;
	171	+ opp-microvolt-L4 = <975000 975000 1325000>;
	172	+ opp-microvolt-L5 = <950000 950000 1325000>;
168	173	clock-latency-ns = <40000>;
169	174	};
170	175	opp-1008000000 {
171	176	opp-hz = /bits/ 64 <1008000000>;
172		- opp-microvolt = <1125000 1125000 1340000>;
173		- opp-microvolt-L0 = <1125000 1125000 1340000>;
174		- opp-microvolt-L1 = <1100000 1100000 1340000>;
175		- opp-microvolt-L2 = <1100000 1100000 1340000>;
176		- opp-microvolt-L3 = <1075000 1075000 1340000>;
177		- opp-microvolt-L4 = <1050000 1050000 1340000>;
178		- opp-microvolt-L5 = <1025000 1025000 1340000>;
	177	+ opp-microvolt = <1125000 1125000 1325000>;
	178	+ opp-microvolt-L0 = <1125000 1125000 1325000>;
	179	+ opp-microvolt-L1 = <1100000 1100000 1325000>;
	180	+ opp-microvolt-L2 = <1100000 1100000 1325000>;
	181	+ opp-microvolt-L3 = <1075000 1075000 1325000>;
	182	+ opp-microvolt-L4 = <1050000 1050000 1325000>;
	183	+ opp-microvolt-L5 = <1025000 1025000 1325000>;
179	184	clock-latency-ns = <40000>;
180	185	};
181	186	opp-1200000000 {
182	187	opp-hz = /bits/ 64 <1200000000>;
183		- opp-microvolt = <1250000 1250000 1340000>;
184		- opp-microvolt-L0 = <1250000 1250000 1340000>;
185		- opp-microvolt-L1 = <1225000 1225000 1340000>;
186		- opp-microvolt-L2 = <1200000 1200000 1340000>;
187		- opp-microvolt-L3 = <1175000 1175000 1340000>;
188		- opp-microvolt-L4 = <1150000 1150000 1340000>;
189		- opp-microvolt-L5 = <1125000 1125000 1340000>;
	188	+ opp-microvolt = <1250000 1250000 1325000>;
	189	+ opp-microvolt-L0 = <1250000 1250000 1325000>;
	190	+ opp-microvolt-L1 = <1225000 1225000 1325000>;
	191	+ opp-microvolt-L2 = <1200000 1200000 1325000>;
	192	+ opp-microvolt-L3 = <1175000 1175000 1325000>;
	193	+ opp-microvolt-L4 = <1150000 1150000 1325000>;
	194	+ opp-microvolt-L5 = <1125000 1125000 1325000>;
190	195	clock-latency-ns = <40000>;
191	196	status = "disabled";
192	197	};
193	198	opp-1296000000 {
194	199	opp-hz = /bits/ 64 <1296000000>;
195		- opp-microvolt = <1300000 1300000 1340000>;
196		- opp-microvolt-L0 = <1300000 1300000 1340000>;
197		- opp-microvolt-L1 = <1275000 1275000 1340000>;
198		- opp-microvolt-L2 = <1250000 1250000 1340000>;
199		- opp-microvolt-L3 = <1225000 1225000 1340000>;
200		- opp-microvolt-L4 = <1200000 1200000 1340000>;
201		- opp-microvolt-L5 = <1175000 1175000 1340000>;
	200	+ opp-microvolt = <1300000 1300000 1325000>;
	201	+ opp-microvolt-L0 = <1300000 1300000 1325000>;
	202	+ opp-microvolt-L1 = <1275000 1275000 1325000>;
	203	+ opp-microvolt-L2 = <1250000 1250000 1325000>;
	204	+ opp-microvolt-L3 = <1225000 1225000 1325000>;
	205	+ opp-microvolt-L4 = <1200000 1200000 1325000>;
	206	+ opp-microvolt-L5 = <1175000 1175000 1325000>;
	207	+ clock-latency-ns = <40000>;
	208	+ status = "disabled";
	209	+ };
	210	+ };
	211	+
	212	+ rk3308bs_cpu0_opp_table: rk3308bs-cpu0-opp-table {
	213	+ compatible = "operating-points-v2";
	214	+ opp-shared;
	215	+
	216	+ rockchip,temp-hysteresis = <5000>;
	217	+ rockchip,low-temp = <0>;
	218	+ rockchip,low-temp-min-volt = <900000>;
	219	+ rockchip,max-volt = <1200000>;
	220	+ rockchip,low-temp-adjust-volt = <
	221	+ /* MHz MHz uV */
	222	+ 0 1200 50000
	223	+ >;
	224	+
	225	+ rockchip,evb-irdrop = <25000>;
	226	+ nvmem-cells = <&cpu_leakage>;
	227	+ nvmem-cell-names = "leakage";
	228	+
	229	+ opp-408000000 {
	230	+ opp-hz = /bits/ 64 <408000000>;
	231	+ opp-microvolt = <850000 850000 1200000>;
	232	+ clock-latency-ns = <40000>;
	233	+ opp-suspend;
	234	+ };
	235	+ opp-600000000 {
	236	+ opp-hz = /bits/ 64 <600000000>;
	237	+ opp-microvolt = <900000 900000 1200000>;
	238	+ clock-latency-ns = <40000>;
	239	+ };
	240	+ opp-816000000 {
	241	+ opp-hz = /bits/ 64 <816000000>;
	242	+ opp-microvolt = <1000000 1000000 1200000>;
	243	+ clock-latency-ns = <40000>;
	244	+ };
	245	+ opp-1008000000 {
	246	+ opp-hz = /bits/ 64 <1008000000>;
	247	+ opp-microvolt = <1125000 1125000 1200000>;
	248	+ clock-latency-ns = <40000>;
	249	+ status = "disabled";
	250	+ };
	251	+ opp-1104000000 {
	252	+ opp-hz = /bits/ 64 <1104000000>;
	253	+ opp-microvolt = <1200000 1200000 1200000>;
202	254	clock-latency-ns = <40000>;
203	255	status = "disabled";
204	256	};
205	257	};
206	258
207	259	arm-pmu {
208		- compatible = "arm,cortex-a53-pmu";
	260	+ compatible = "arm,cortex-a35-pmu";
209	261	interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>,
210	262	<GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>,
211	263	<GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>,
..	..	@@ -229,7 +281,7 @@
229	281	route_rgb: route-rgb {
230	282	status = "disabled";
231	283	logo,uboot = "logo.bmp";
232		- /* logo,kernel = "logo_kernel.bmp"; */
	284	+ logo,kernel = "logo_kernel.bmp";
233	285	logo,mode = "center";
234	286	charge_logo,mode = "center";
235	287	connect = <&vop_out_rgb>;
..	..	@@ -241,7 +293,7 @@
241	293	compatible = "rockchip,rk3308-dmc";
242	294	clocks = <&cru SCLK_DDRCLK>;
243	295	clock-names = "dmc_clk";
244		- operating-points-v2 = <&dmc_opp_table>;
	296	+ operating-points-v2 = <&dmc_opp_table>, <&rk3308bs_dmc_opp_table>;
245	297	status = "disabled";
246	298	};
247	299
..	..	@@ -264,22 +316,31 @@
264	316	};
265	317	};
266	318
	319	+ rk3308bs_dmc_opp_table: rk3308bs-dmc-opp-table {
	320	+ compatible = "operating-points-v2";
	321	+
	322	+ opp-394000000 {
	323	+ opp-hz = /bits/ 64 <394000000>;
	324	+ opp-microvolt = <900000>;
	325	+ };
	326	+ opp-452000000 {
	327	+ opp-hz = /bits/ 64 <452000000>;
	328	+ opp-microvolt = <900000>;
	329	+ };
	330	+ opp-590000000 {
	331	+ opp-hz = /bits/ 64 <590000000>;
	332	+ opp-microvolt = <900000>;
	333	+ };
	334	+ };
	335	+
267	336	fiq_debugger: fiq-debugger {
268	337	compatible = "rockchip,fiq-debugger";
269	338	rockchip,serial-id = <2>;
270	339	rockchip,wake-irq = <0>;
271		- rockchip,irq-mode-enable = <0>;
	340	+ rockchip,irq-mode-enable = <1>;
272	341	rockchip,baudrate = <1500000>; /* Only 115200 and 1500000 */
273	342	interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>;
274	343	status = "disabled";
275		- };
276		-
277		- firmware {
278		- optee: optee {
279		- compatible = "linaro,optee-tz";
280		- method = "smc";
281		- status = "disabled";
282		- };
283	344	};
284	345
285	346	mac_clkin: external-mac-clock {
..	..	@@ -292,6 +353,20 @@
292	353	psci {
293	354	compatible = "arm,psci-1.0";
294	355	method = "smc";
	356	+ };
	357	+
	358	+ ramoops_mem: ramoops_mem {
	359	+ reg = <0x0 0x110000 0x0 0xf0000>;
	360	+ reg-names = "ramoops_mem";
	361	+ };
	362	+
	363	+ ramoops: ramoops {
	364	+ compatible = "ramoops";
	365	+ record-size = <0x0 0x30000>;
	366	+ console-size = <0x0 0xc0000>;
	367	+ ftrace-size = <0x0 0x00000>;
	368	+ pmsg-size = <0x0 0x00000>;
	369	+ memory-region = <&ramoops_mem>;
295	370	};
296	371
297	372	rgb: rgb {
..	..	@@ -327,15 +402,6 @@
327	402	drm_logo: drm-logo@00000000 {
328	403	compatible = "rockchip,drm-logo";
329	404	reg = <0x0 0x0 0x0 0x0>;
330		- };
331		-
332		- ramoops: ramoops@110000 {
333		- compatible = "ramoops";
334		- reg = <0x0 0x110000 0x0 0xf0000>;
335		- record-size = <0x30000>;
336		- console-size = <0xc0000>;
337		- ftrace-size = <0x00000>;
338		- pmsg-size = <0x00000>;
339	405	};
340	406	};
341	407
..	..	@@ -380,14 +446,8 @@
380	446
381	447	pmu_pvtm: pmu-pvtm {
382	448	compatible = "rockchip,rk3308-pmu-pvtm";
383		- #address-cells = <1>;
384		- #size-cells = <0>;
385		-
386		- pvtm@1 {
387		- reg = <1>;
388		- clocks = <&cru SCLK_PVTM_PMU>;
389		- clock-names = "clk";
390		- };
	449	+ clocks = <&cru SCLK_PVTM_PMU>;
	450	+ clock-names = "pmu";
391	451	};
392	452
393	453	reboot-mode {
..	..	@@ -398,37 +458,69 @@
398	458	mode-normal = <BOOT_NORMAL>;
399	459	mode-recovery = <BOOT_RECOVERY>;
400	460	mode-fastboot = <BOOT_FASTBOOT>;
	461	+ mode-panic = <BOOT_PANIC>;
	462	+ mode-watchdog = <BOOT_WATCHDOG>;
	463	+ };
	464	+ };
	465	+
	466	+ usb2phy_grf: syscon@ff008000 {
	467	+ compatible = "rockchip,rk3308-usb2phy-grf", "syscon", "simple-mfd";
	468	+ reg = <0x0 0xff008000 0x0 0x4000>;
	469	+ #address-cells = <1>;
	470	+ #size-cells = <1>;
	471	+
	472	+ u2phy: usb2phy@100 {
	473	+ compatible = "rockchip,rk3308-usb2phy";
	474	+ reg = <0x100 0x10>;
	475	+ assigned-clocks = <&cru USB480M>;
	476	+ assigned-clock-parents = <&u2phy>;
	477	+ clocks = <&cru SCLK_USBPHY_REF>;
	478	+ clock-names = "phyclk";
	479	+ clock-output-names = "usb480m_phy";
	480	+ #clock-cells = <0>;
	481	+ status = "disabled";
	482	+
	483	+ u2phy_otg: otg-port {
	484	+ interrupts = <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>,
	485	+ <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>,
	486	+ <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>;
	487	+ interrupt-names = "otg-bvalid", "otg-id",
	488	+ "linestate";
	489	+ #phy-cells = <0>;
	490	+ status = "disabled";
	491	+ };
	492	+
	493	+ u2phy_host: host-port {
	494	+ interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>;
	495	+ interrupt-names = "linestate";
	496	+ #phy-cells = <0>;
	497	+ status = "disabled";
	498	+ };
401	499	};
402	500	};
403	501
404	502	detect_grf: syscon@ff00b000 {
405		- compatible = "syscon", "simple-mfd";
	503	+ compatible = "rockchip,rk3308-detect-grf", "syscon", "simple-mfd";
406	504	reg = <0x0 0xff00b000 0x0 0x1000>;
407	505	#address-cells = <1>;
408	506	#size-cells = <1>;
409	507	};
410	508
411	509	core_grf: syscon@ff00c000 {
412		- compatible = "syscon", "simple-mfd";
	510	+ compatible = "rockchip,rk3308-core-grf", "syscon", "simple-mfd";
413	511	reg = <0x0 0xff00c000 0x0 0x1000>;
414	512	#address-cells = <1>;
415	513	#size-cells = <1>;
416	514
417	515	pvtm: pvtm {
418	516	compatible = "rockchip,rk3308-pvtm";
419		- #address-cells = <1>;
420		- #size-cells = <0>;
421		-
422		- pvtm@0 {
423		- reg = <0>;
424		- clocks = <&cru SCLK_PVTM_CORE>;
425		- clock-names = "clk";
426		- };
	517	+ clocks = <&cru SCLK_PVTM_CORE>;
	518	+ clock-names = "core";
427	519	};
428	520	};
429	521
430	522	i2c0: i2c@ff040000 {
431		- compatible = "rockchip,rk3399-i2c";
	523	+ compatible = "rockchip,rk3308-i2c", "rockchip,rk3399-i2c";
432	524	reg = <0x0 0xff040000 0x0 0x1000>;
433	525	clocks = <&cru SCLK_I2C0>, <&cru PCLK_I2C0>;
434	526	clock-names = "i2c", "pclk";
..	..	@@ -441,7 +533,7 @@
441	533	};
442	534
443	535	i2c1: i2c@ff050000 {
444		- compatible = "rockchip,rk3399-i2c";
	536	+ compatible = "rockchip,rk3308-i2c", "rockchip,rk3399-i2c";
445	537	reg = <0x0 0xff050000 0x0 0x1000>;
446	538	clocks = <&cru SCLK_I2C1>, <&cru PCLK_I2C1>;
447	539	clock-names = "i2c", "pclk";
..	..	@@ -454,7 +546,7 @@
454	546	};
455	547
456	548	i2c2: i2c@ff060000 {
457		- compatible = "rockchip,rk3399-i2c";
	549	+ compatible = "rockchip,rk3308-i2c", "rockchip,rk3399-i2c";
458	550	reg = <0x0 0xff060000 0x0 0x1000>;
459	551	clocks = <&cru SCLK_I2C2>, <&cru PCLK_I2C2>;
460	552	clock-names = "i2c", "pclk";
..	..	@@ -467,7 +559,7 @@
467	559	};
468	560
469	561	i2c3: i2c@ff070000 {
470		- compatible = "rockchip,rk3399-i2c";
	562	+ compatible = "rockchip,rk3308-i2c", "rockchip,rk3399-i2c";
471	563	reg = <0x0 0xff070000 0x0 0x1000>;
472	564	clocks = <&cru SCLK_I2C3>, <&cru PCLK_I2C3>;
473	565	clock-names = "i2c", "pclk";
..	..	@@ -479,45 +571,8 @@
479	571	status = "disabled";
480	572	};
481	573
482		- usb2phy_grf: syscon@ff008000 {
483		- compatible = "rockchip,rk3308-usb2phy-grf", "syscon",
484		- "simple-mfd";
485		- reg = <0x0 0xff008000 0x0 0x4000>;
486		- #address-cells = <1>;
487		- #size-cells = <1>;
488		-
489		- u2phy: usb2-phy@100 {
490		- compatible = "rockchip,rk3308-usb2phy";
491		- reg = <0x100 0x10>;
492		- clocks = <&cru SCLK_USBPHY_REF>;
493		- clock-names = "phyclk";
494		- #clock-cells = <0>;
495		- assigned-clocks = <&cru USB480M>;
496		- assigned-clock-parents = <&u2phy>;
497		- clock-output-names = "usb480m_phy";
498		- status = "disabled";
499		-
500		- u2phy_otg: otg-port {
501		- #phy-cells = <0>;
502		- interrupts = <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>,
503		- <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>,
504		- <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>;
505		- interrupt-names = "otg-bvalid", "otg-id",
506		- "linestate";
507		- status = "disabled";
508		- };
509		-
510		- u2phy_host: host-port {
511		- #phy-cells = <0>;
512		- interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>;
513		- interrupt-names = "linestate";
514		- status = "disabled";
515		- };
516		- };
517		- };
518		-
519	574	wdt: watchdog@ff080000 {
520		- compatible = "snps,dw-wdt";
	575	+ compatible = "rockchip,rk3308-wdt", "snps,dw-wdt";
521	576	reg = <0x0 0xff080000 0x0 0x100>;
522	577	clocks = <&cru PCLK_WDT>;
523	578	interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
..	..	@@ -650,132 +705,144 @@
650	705	pwm8: pwm@ff160000 {
651	706	compatible = "rockchip,rk3308-pwm", "rockchip,rk3328-pwm";
652	707	reg = <0x0 0xff160000 0x0 0x10>;
653		- #pwm-cells = <3>;
654		- pinctrl-names = "active";
655		- pinctrl-0 = <&pwm8_pin>;
	708	+ interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>;
656	709	clocks = <&cru SCLK_PWM2>, <&cru PCLK_PWM2>;
657	710	clock-names = "pwm", "pclk";
	711	+ pinctrl-names = "active";
	712	+ pinctrl-0 = <&pwm8_pin>;
	713	+ #pwm-cells = <3>;
658	714	status = "disabled";
659	715	};
660	716
661	717	pwm9: pwm@ff160010 {
662	718	compatible = "rockchip,rk3308-pwm", "rockchip,rk3328-pwm";
663	719	reg = <0x0 0xff160010 0x0 0x10>;
664		- #pwm-cells = <3>;
665		- pinctrl-names = "active";
666		- pinctrl-0 = <&pwm9_pin>;
	720	+ interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>;
667	721	clocks = <&cru SCLK_PWM2>, <&cru PCLK_PWM2>;
668	722	clock-names = "pwm", "pclk";
	723	+ pinctrl-names = "active";
	724	+ pinctrl-0 = <&pwm9_pin>;
	725	+ #pwm-cells = <3>;
669	726	status = "disabled";
670	727	};
671	728
672	729	pwm10: pwm@ff160020 {
673	730	compatible = "rockchip,rk3308-pwm", "rockchip,rk3328-pwm";
674	731	reg = <0x0 0xff160020 0x0 0x10>;
675		- #pwm-cells = <3>;
676		- pinctrl-names = "active";
677		- pinctrl-0 = <&pwm10_pin>;
	732	+ interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>;
678	733	clocks = <&cru SCLK_PWM2>, <&cru PCLK_PWM2>;
679	734	clock-names = "pwm", "pclk";
	735	+ pinctrl-names = "active";
	736	+ pinctrl-0 = <&pwm10_pin>;
	737	+ #pwm-cells = <3>;
680	738	status = "disabled";
681	739	};
682	740
683	741	pwm11: pwm@ff160030 {
684	742	compatible = "rockchip,rk3308-pwm", "rockchip,rk3328-pwm";
685	743	reg = <0x0 0xff160030 0x0 0x10>;
686		- #pwm-cells = <3>;
687		- pinctrl-names = "active";
688		- pinctrl-0 = <&pwm11_pin>;
	744	+ interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>;
689	745	clocks = <&cru SCLK_PWM2>, <&cru PCLK_PWM2>;
690	746	clock-names = "pwm", "pclk";
	747	+ pinctrl-names = "active";
	748	+ pinctrl-0 = <&pwm11_pin>;
	749	+ #pwm-cells = <3>;
691	750	status = "disabled";
692	751	};
693	752
694	753	pwm4: pwm@ff170000 {
695	754	compatible = "rockchip,rk3308-pwm", "rockchip,rk3328-pwm";
696	755	reg = <0x0 0xff170000 0x0 0x10>;
697		- #pwm-cells = <3>;
698		- pinctrl-names = "active";
699		- pinctrl-0 = <&pwm4_pin>;
	756	+ interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>;
700	757	clocks = <&cru SCLK_PWM1>, <&cru PCLK_PWM1>;
701	758	clock-names = "pwm", "pclk";
	759	+ pinctrl-names = "active";
	760	+ pinctrl-0 = <&pwm4_pin>;
	761	+ #pwm-cells = <3>;
702	762	status = "disabled";
703	763	};
704	764
705	765	pwm5: pwm@ff170010 {
706	766	compatible = "rockchip,rk3308-pwm", "rockchip,rk3328-pwm";
707	767	reg = <0x0 0xff170010 0x0 0x10>;
708		- #pwm-cells = <3>;
709		- pinctrl-names = "active";
710		- pinctrl-0 = <&pwm5_pin>;
	768	+ interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>;
711	769	clocks = <&cru SCLK_PWM1>, <&cru PCLK_PWM1>;
712	770	clock-names = "pwm", "pclk";
	771	+ pinctrl-names = "active";
	772	+ pinctrl-0 = <&pwm5_pin>;
	773	+ #pwm-cells = <3>;
713	774	status = "disabled";
714	775	};
715	776
716	777	pwm6: pwm@ff170020 {
717	778	compatible = "rockchip,rk3308-pwm", "rockchip,rk3328-pwm";
718	779	reg = <0x0 0xff170020 0x0 0x10>;
719		- #pwm-cells = <3>;
720		- pinctrl-names = "active";
721		- pinctrl-0 = <&pwm6_pin>;
	780	+ interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>;
722	781	clocks = <&cru SCLK_PWM1>, <&cru PCLK_PWM1>;
723	782	clock-names = "pwm", "pclk";
	783	+ pinctrl-names = "active";
	784	+ pinctrl-0 = <&pwm6_pin>;
	785	+ #pwm-cells = <3>;
724	786	status = "disabled";
725	787	};
726	788
727	789	pwm7: pwm@ff170030 {
728	790	compatible = "rockchip,rk3308-pwm", "rockchip,rk3328-pwm";
729	791	reg = <0x0 0xff170030 0x0 0x10>;
730		- #pwm-cells = <3>;
731		- pinctrl-names = "active";
732		- pinctrl-0 = <&pwm7_pin>;
	792	+ interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>;
733	793	clocks = <&cru SCLK_PWM1>, <&cru PCLK_PWM1>;
734	794	clock-names = "pwm", "pclk";
	795	+ pinctrl-names = "active";
	796	+ pinctrl-0 = <&pwm7_pin>;
	797	+ #pwm-cells = <3>;
735	798	status = "disabled";
736	799	};
737	800
738	801	pwm0: pwm@ff180000 {
739	802	compatible = "rockchip,rk3308-pwm", "rockchip,rk3328-pwm";
740	803	reg = <0x0 0xff180000 0x0 0x10>;
741		- #pwm-cells = <3>;
742		- pinctrl-names = "active";
743		- pinctrl-0 = <&pwm0_pin>;
	804	+ interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;
744	805	clocks = <&cru SCLK_PWM0>, <&cru PCLK_PWM0>;
745	806	clock-names = "pwm", "pclk";
	807	+ pinctrl-names = "active";
	808	+ pinctrl-0 = <&pwm0_pin>;
	809	+ #pwm-cells = <3>;
746	810	status = "disabled";
747	811	};
748	812
749	813	pwm1: pwm@ff180010 {
750	814	compatible = "rockchip,rk3308-pwm", "rockchip,rk3328-pwm";
751	815	reg = <0x0 0xff180010 0x0 0x10>;
752		- #pwm-cells = <3>;
753		- pinctrl-names = "active";
754		- pinctrl-0 = <&pwm1_pin>;
	816	+ interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;
755	817	clocks = <&cru SCLK_PWM0>, <&cru PCLK_PWM0>;
756	818	clock-names = "pwm", "pclk";
	819	+ pinctrl-names = "active";
	820	+ pinctrl-0 = <&pwm1_pin>;
	821	+ #pwm-cells = <3>;
757	822	status = "disabled";
758	823	};
759	824
760	825	pwm2: pwm@ff180020 {
761	826	compatible = "rockchip,rk3308-pwm", "rockchip,rk3328-pwm";
762	827	reg = <0x0 0xff180020 0x0 0x10>;
763		- #pwm-cells = <3>;
764		- pinctrl-names = "active";
765		- pinctrl-0 = <&pwm2_pin>;
	828	+ interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;
766	829	clocks = <&cru SCLK_PWM0>, <&cru PCLK_PWM0>;
767	830	clock-names = "pwm", "pclk";
	831	+ pinctrl-names = "active";
	832	+ pinctrl-0 = <&pwm2_pin>;
	833	+ #pwm-cells = <3>;
768	834	status = "disabled";
769	835	};
770	836
771	837	pwm3: pwm@ff180030 {
772	838	compatible = "rockchip,rk3308-pwm", "rockchip,rk3328-pwm";
773	839	reg = <0x0 0xff180030 0x0 0x10>;
774		- #pwm-cells = <3>;
775		- pinctrl-names = "active";
776		- pinctrl-0 = <&pwm3_pin>;
	840	+ interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;
777	841	clocks = <&cru SCLK_PWM0>, <&cru PCLK_PWM0>;
778	842	clock-names = "pwm", "pclk";
	843	+ pinctrl-names = "active";
	844	+ pinctrl-0 = <&pwm3_pin>;
	845	+ #pwm-cells = <3>;
779	846	status = "disabled";
780	847	};
781	848
..	..	@@ -800,9 +867,9 @@
800	867	compatible = "rockchip,rk3308-saradc", "rockchip,rk3399-saradc";
801	868	reg = <0x0 0xff1e0000 0x0 0x100>;
802	869	interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
803		- #io-channel-cells = <1>;
804	870	clocks = <&cru SCLK_SARADC>, <&cru PCLK_SARADC>;
805	871	clock-names = "saradc", "apb_pclk";
	872	+ #io-channel-cells = <1>;
806	873	resets = <&cru SRST_SARADC_P>;
807	874	reset-names = "saradc-apb";
808	875	status = "disabled";
..	..	@@ -818,12 +885,12 @@
818	885	thermal-sensors = <&tsadc 0>;
819	886
820	887	trips {
821		- threshold: trip-point-0 {
	888	+ threshold: trip-point@0 {
822	889	temperature = <70000>;
823	890	hysteresis = <2000>;
824	891	type = "passive";
825	892	};
826		- target: trip-point-1 {
	893	+ target: trip-point@1 {
827	894	temperature = <85000>;
828	895	hysteresis = <2000>;
829	896	type = "passive";
..	..	@@ -842,10 +909,9 @@
842	909	contribution = <4096>;
843	910	};
844	911	};
845		-
846	912	};
847	913
848		- logic_thermal: logic-thermal {
	914	+ gpu_thermal: gpu-thermal {
849	915	polling-delay-passive = <100>; /* milliseconds */
850	916	polling-delay = <1000>; /* milliseconds */
851	917
..	..	@@ -865,7 +931,7 @@
865	931	resets = <&cru SRST_TSADC>;
866	932	reset-names = "tsadc-apb";
867	933	pinctrl-names = "gpio", "otpout";
868		- pinctrl-0 = <&tsadc_otp_gpio>;
	934	+ pinctrl-0 = <&tsadc_otp_pin>;
869	935	pinctrl-1 = <&tsadc_otp_out>;
870	936	#thermal-sensor-cells = <1>;
871	937	rockchip,hw-tshut-temp = <120000>;
..	..	@@ -895,33 +961,26 @@
895	961	};
896	962	};
897	963
898		- amba {
899		- compatible = "arm,amba-bus";
900		- #address-cells = <2>;
901		- #size-cells = <2>;
902		- ranges;
	964	+ dmac0: dma-controller@ff2c0000 {
	965	+ compatible = "arm,pl330", "arm,primecell";
	966	+ reg = <0x0 0xff2c0000 0x0 0x4000>;
	967	+ interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
	968	+ <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>;
	969	+ arm,pl330-periph-burst;
	970	+ clocks = <&cru ACLK_DMAC0>;
	971	+ clock-names = "apb_pclk";
	972	+ #dma-cells = <1>;
	973	+ };
903	974
904		- dmac0: dma-controller@ff2c0000 {
905		- compatible = "arm,pl330", "arm,primecell";
906		- reg = <0x0 0xff2c0000 0x0 0x4000>;
907		- interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
908		- <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>;
909		- #dma-cells = <1>;
910		- clocks = <&cru ACLK_DMAC0>;
911		- clock-names = "apb_pclk";
912		- arm,pl330-periph-burst;
913		- };
914		-
915		- dmac1: dma-controller@ff2d0000 {
916		- compatible = "arm,pl330", "arm,primecell";
917		- reg = <0x0 0xff2d0000 0x0 0x4000>;
918		- interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>,
919		- <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>;
920		- #dma-cells = <1>;
921		- clocks = <&cru ACLK_DMAC1>;
922		- clock-names = "apb_pclk";
923		- arm,pl330-periph-burst;
924		- };
	975	+ dmac1: dma-controller@ff2d0000 {
	976	+ compatible = "arm,pl330", "arm,primecell";
	977	+ reg = <0x0 0xff2d0000 0x0 0x4000>;
	978	+ interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>,
	979	+ <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>;
	980	+ arm,pl330-periph-burst;
	981	+ clocks = <&cru ACLK_DMAC1>;
	982	+ clock-names = "apb_pclk";
	983	+ #dma-cells = <1>;
925	984	};
926	985
927	986	vop: vop@ff2e0000 {
..	..	@@ -945,17 +1004,17 @@
945	1004	};
946	1005	};
947	1006
948		- rng: rng@ff2f0000 {
	1007	+ rng: rng@ff2f0400 {
949	1008	compatible = "rockchip,cryptov2-rng";
950		- reg = <0x0 0xff2f0000 0x0 0x4000>;
	1009	+ reg = <0x0 0xff2f0400 0x0 0x80>;
951	1010	clocks = <&cru SCLK_CRYPTO>, <&cru SCLK_CRYPTO_APK>,
952		- <&cru ACLK_CRYPTO>, <&cru HCLK_CRYPTO>;
	1011	+ <&cru ACLK_CRYPTO>, <&cru HCLK_CRYPTO>;
953	1012	clock-names = "clk_crypto", "clk_crypto_apk",
954		- "aclk_crypto", "hclk_crypto";
	1013	+ "aclk_crypto", "hclk_crypto";
955	1014	assigned-clocks = <&cru SCLK_CRYPTO>, <&cru SCLK_CRYPTO_APK>,
956		- <&cru ACLK_CRYPTO>, <&cru HCLK_CRYPTO>;
	1015	+ <&cru ACLK_CRYPTO>, <&cru HCLK_CRYPTO>;
957	1016	assigned-clock-rates = <150000000>, <150000000>,
958		- <200000000>, <100000000>;
	1017	+ <200000000>, <100000000>;
959	1018	resets = <&cru SRST_CRYPTO>;
960	1019	reset-names = "reset";
961	1020	status = "disabled";
..	..	@@ -1016,6 +1075,7 @@
1016	1075	rockchip,cru = <&cru>;
1017	1076	rockchip,grf = <&grf>;
1018	1077	rockchip,mclk-calibrate;
	1078	+ rockchip,io-multiplex;
1019	1079	status = "disabled";
1020	1080	};
1021	1081
..	..	@@ -1096,7 +1156,7 @@
1096	1156	};
1097	1157
1098	1158	pdm_8ch: pdm@ff380000 {
1099		- compatible = "rockchip,rk3308-pdm";
	1159	+ compatible = "rockchip,rk3308-pdm", "rockchip,pdm";
1100	1160	reg = <0x0 0xff380000 0x0 0x1000>;
1101	1161	clocks = <&cru SCLK_PDM>, <&cru HCLK_PDM>;
1102	1162	clock-names = "pdm_clk", "pdm_hclk";
..	..	@@ -1114,7 +1174,7 @@
1114	1174	};
1115	1175
1116	1176	spdif_tx: spdif-tx@ff3a0000 {
1117		- compatible = "rockchip,rk3308-spdif", "rockchip,rk3328-spdif";
	1177	+ compatible = "rockchip,rk3308-spdif", "rockchip,rk3066-spdif";
1118	1178	reg = <0x0 0xff3a0000 0x0 0x1000>;
1119	1179	interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>;
1120	1180	clocks = <&cru SCLK_SPDIF_TX>, <&cru HCLK_SPDIFTX>;
..	..	@@ -1156,7 +1216,8 @@
1156	1216	};
1157	1217
1158	1218	usb20_otg: usb@ff400000 {
1159		- compatible = "rockchip,rk3066-usb", "snps,dwc2";
	1219	+ compatible = "rockchip,rk3308-usb", "rockchip,rk3066-usb",
	1220	+ "snps,dwc2";
1160	1221	reg = <0x0 0xff400000 0x0 0x40000>;
1161	1222	interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>;
1162	1223	clocks = <&cru HCLK_OTG>;
..	..	@@ -1165,7 +1226,6 @@
1165	1226	g-np-tx-fifo-size = <16>;
1166	1227	g-rx-fifo-size = <280>;
1167	1228	g-tx-fifo-size = <256 128 128 64 32 16>;
1168		- g-use-dma;
1169	1229	phys = <&u2phy_otg>;
1170	1230	phy-names = "usb2-phy";
1171	1231	status = "disabled";
..	..	@@ -1193,46 +1253,61 @@
1193	1253	status = "disabled";
1194	1254	};
1195	1255
1196		- sdmmc: dwmmc@ff480000 {
	1256	+ sdmmc: mmc@ff480000 {
1197	1257	compatible = "rockchip,rk3308-dw-mshc", "rockchip,rk3288-dw-mshc";
1198	1258	reg = <0x0 0xff480000 0x0 0x4000>;
1199		- max-frequency = <150000000>;
	1259	+ interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>;
1200	1260	bus-width = <4>;
1201	1261	clocks = <&cru HCLK_SDMMC>, <&cru SCLK_SDMMC>,
1202	1262	<&cru SCLK_SDMMC_DRV>, <&cru SCLK_SDMMC_SAMPLE>;
1203		- clock-names = "biu", "ciu", "ciu-drv", "ciu-sample";
	1263	+ clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
1204	1264	fifo-depth = <0x100>;
1205		- interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>;
	1265	+ max-frequency = <150000000>;
1206	1266	pinctrl-names = "default";
1207	1267	pinctrl-0 = <&sdmmc_clk &sdmmc_cmd &sdmmc_det &sdmmc_bus4>;
1208	1268	status = "disabled";
1209	1269	};
1210	1270
1211		- emmc: dwmmc@ff490000 {
	1271	+ emmc: mmc@ff490000 {
1212	1272	compatible = "rockchip,rk3308-dw-mshc", "rockchip,rk3288-dw-mshc";
1213	1273	reg = <0x0 0xff490000 0x0 0x4000>;
1214		- max-frequency = <150000000>;
	1274	+ interrupts = <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>;
1215	1275	bus-width = <8>;
1216	1276	clocks = <&cru HCLK_EMMC>, <&cru SCLK_EMMC>,
1217	1277	<&cru SCLK_EMMC_DRV>, <&cru SCLK_EMMC_SAMPLE>;
1218		- clock-names = "biu", "ciu", "ciu-drv", "ciu-sample";
	1278	+ clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
1219	1279	fifo-depth = <0x100>;
1220		- interrupts = <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>;
	1280	+ max-frequency = <150000000>;
1221	1281	status = "disabled";
1222	1282	};
1223	1283
1224		- sdio: dwmmc@ff4a0000 {
	1284	+ sdio: mmc@ff4a0000 {
1225	1285	compatible = "rockchip,rk3308-dw-mshc", "rockchip,rk3288-dw-mshc";
1226	1286	reg = <0x0 0xff4a0000 0x0 0x4000>;
1227		- max-frequency = <150000000>;
	1287	+ interrupts = <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>;
1228	1288	bus-width = <4>;
1229	1289	clocks = <&cru HCLK_SDIO>, <&cru SCLK_SDIO>,
1230	1290	<&cru SCLK_SDIO_DRV>, <&cru SCLK_SDIO_SAMPLE>;
1231		- clock-names = "biu", "ciu", "ciu-drv", "ciu-sample";
	1291	+ clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
1232	1292	fifo-depth = <0x100>;
1233		- interrupts = <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>;
	1293	+ max-frequency = <150000000>;
1234	1294	pinctrl-names = "default";
1235	1295	pinctrl-0 = <&sdio_bus4 &sdio_cmd &sdio_clk>;
	1296	+ status = "disabled";
	1297	+ };
	1298	+
	1299	+ nfc: nand-controller@ff4b0000 {
	1300	+ compatible = "rockchip,rk3308-nfc",
	1301	+ "rockchip,rv1108-nfc";
	1302	+ reg = <0x0 0xff4b0000 0x0 0x4000>;
	1303	+ interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>;
	1304	+ clocks = <&cru HCLK_NANDC>, <&cru SCLK_NANDC>;
	1305	+ clock-names = "ahb", "nfc";
	1306	+ assigned-clocks = <&cru SCLK_NANDC>;
	1307	+ assigned-clock-rates = <150000000>;
	1308	+ pinctrl-0 = <&flash_ale &flash_bus8 &flash_cle &flash_csn0
	1309	+ &flash_rdn &flash_rdy &flash_wrn>;
	1310	+ pinctrl-names = "default";
1236	1311	status = "disabled";
1237	1312	};
1238	1313
..	..	@@ -1246,21 +1321,9 @@
1246	1321	status = "disabled";
1247	1322	};
1248	1323
1249		- sfc: sfc@ff4c0000 {
1250		- compatible = "rockchip,sfc";
1251		- reg = <0x0 0xff4c0000 0x0 0x4000>;
1252		- interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>;
1253		- clocks = <&cru SCLK_SFC>, <&cru HCLK_SFC>;
1254		- clock-names = "clk_sfc", "hclk_sfc";
1255		- assigned-clocks = <&cru SCLK_SFC>;
1256		- assigned-clock-rates = <100000000>;
1257		- status = "disabled";
1258		- };
1259		-
1260	1324	mac: ethernet@ff4e0000 {
1261	1325	compatible = "rockchip,rk3308-mac";
1262	1326	reg = <0x0 0xff4e0000 0x0 0x10000>;
1263		- rockchip,grf = <&grf>;
1264	1327	interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>;
1265	1328	interrupt-names = "macirq";
1266	1329	clocks = <&cru SCLK_MAC>, <&cru SCLK_MAC_RX_TX>,
..	..	@@ -1276,6 +1339,18 @@
1276	1339	pinctrl-0 = <&rmii_pins &mac_refclk_12ma>;
1277	1340	resets = <&cru SRST_MAC_A>;
1278	1341	reset-names = "stmmaceth";
	1342	+ rockchip,grf = <&grf>;
	1343	+ status = "disabled";
	1344	+ };
	1345	+
	1346	+ sfc: spi@ff4c0000 {
	1347	+ compatible = "rockchip,sfc";
	1348	+ reg = <0x0 0xff4c0000 0x0 0x4000>;
	1349	+ interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>;
	1350	+ clocks = <&cru SCLK_SFC>, <&cru HCLK_SFC>;
	1351	+ clock-names = "clk_sfc", "hclk_sfc";
	1352	+ assigned-clocks = <&cru SCLK_SFC>;
	1353	+ assigned-clock-rates = <100000000>;
1279	1354	status = "disabled";
1280	1355	};
1281	1356
..	..	@@ -1286,7 +1361,6 @@
1286	1361	rockchip,boost = <&cpu_boost>;
1287	1362	#clock-cells = <1>;
1288	1363	#reset-cells = <1>;
1289		-
1290	1364	assigned-clocks = <&cru SCLK_RTC32K>;
1291	1365	assigned-clock-rates = <32768>;
1292	1366	};
..	..	@@ -1309,32 +1383,34 @@
1309	1383	clock-names = "acodec", "mclk_tx", "mclk_rx";
1310	1384	resets = <&cru SRST_ACODEC_P>;
1311	1385	reset-names = "acodec-reset";
	1386	+ spk_ctl-gpios = <&gpio0 RK_PA5 GPIO_ACTIVE_HIGH>;
1312	1387	status = "disabled";
1313	1388	};
1314	1389
1315	1390	gic: interrupt-controller@ff580000 {
1316	1391	compatible = "arm,gic-400";
1317		- #interrupt-cells = <3>;
1318		- #address-cells = <0>;
1319		- interrupt-controller;
1320		-
1321	1392	reg = <0x0 0xff581000 0x0 0x1000>,
1322	1393	<0x0 0xff582000 0x0 0x2000>,
1323	1394	<0x0 0xff584000 0x0 0x2000>,
1324	1395	<0x0 0xff586000 0x0 0x2000>;
1325	1396	interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;
	1397	+ #interrupt-cells = <3>;
	1398	+ interrupt-controller;
	1399	+ #address-cells = <0>;
1326	1400	};
1327	1401
1328	1402	sram: sram@fff80000 {
1329	1403	compatible = "mmio-sram";
1330	1404	reg = <0x0 0xfff80000 0x0 0x40000>;
	1405	+ ranges = <0 0x0 0xfff80000 0x40000>;
1331	1406	#address-cells = <1>;
1332	1407	#size-cells = <1>;
1333		- ranges = <0 0x0 0xfff80000 0x40000>;
	1408	+
1334	1409	/* reserved for ddr dvfs and system suspend/resume */
1335	1410	ddr-sram@0 {
1336	1411	reg = <0x0 0x8000>;
1337	1412	};
	1413	+
1338	1414	/* reserved for vad audio buffer */
1339	1415	vad_sram: vad-sram@8000 {
1340	1416	reg = <0x8000 0x38000>;
..	..	@@ -1362,7 +1438,6 @@
1362	1438	clocks = <&cru PCLK_GPIO0>;
1363	1439	gpio-controller;
1364	1440	#gpio-cells = <2>;
1365		-
1366	1441	interrupt-controller;
1367	1442	#interrupt-cells = <2>;
1368	1443	};
..	..	@@ -1374,7 +1449,6 @@
1374	1449	clocks = <&cru PCLK_GPIO1>;
1375	1450	gpio-controller;
1376	1451	#gpio-cells = <2>;
1377		-
1378	1452	interrupt-controller;
1379	1453	#interrupt-cells = <2>;
1380	1454	};
..	..	@@ -1386,7 +1460,6 @@
1386	1460	clocks = <&cru PCLK_GPIO2>;
1387	1461	gpio-controller;
1388	1462	#gpio-cells = <2>;
1389		-
1390	1463	interrupt-controller;
1391	1464	#interrupt-cells = <2>;
1392	1465	};
..	..	@@ -1398,7 +1471,6 @@
1398	1471	clocks = <&cru PCLK_GPIO3>;
1399	1472	gpio-controller;
1400	1473	#gpio-cells = <2>;
1401		-
1402	1474	interrupt-controller;
1403	1475	#interrupt-cells = <2>;
1404	1476	};
..	..	@@ -1410,7 +1482,6 @@
1410	1482	clocks = <&cru PCLK_GPIO4>;
1411	1483	gpio-controller;
1412	1484	#gpio-cells = <2>;
1413		-
1414	1485	interrupt-controller;
1415	1486	#interrupt-cells = <2>;
1416	1487	};
..	..	@@ -1494,6 +1565,202 @@
1494	1565	input-enable;
1495	1566	};
1496	1567
	1568	+ can-m0 {
	1569	+ canm0_pins: canm0-pins {
	1570	+ rockchip,pins =
	1571	+ /* can_rxd_m0 */
	1572	+ <0 RK_PB3 2 &pcfg_pull_none>,
	1573	+ /* can_txd_m0 */
	1574	+ <0 RK_PB4 2 &pcfg_pull_none>;
	1575	+ };
	1576	+ };
	1577	+
	1578	+ can-m1 {
	1579	+ canm1_pins: canm1-pins {
	1580	+ rockchip,pins =
	1581	+ /* can_rxd_m1 */
	1582	+ <1 RK_PC6 5 &pcfg_pull_none>,
	1583	+ /* can_txd_m1 */
	1584	+ <1 RK_PC7 5 &pcfg_pull_none>;
	1585	+ };
	1586	+ };
	1587	+
	1588	+ can-m2 {
	1589	+ canm2_pins: canm2-pins {
	1590	+ rockchip,pins =
	1591	+ /* can_rxd_m2 */
	1592	+ <2 RK_PA2 4 &pcfg_pull_none>,
	1593	+ /* can_txd_m2 */
	1594	+ <2 RK_PA3 4 &pcfg_pull_none>;
	1595	+ };
	1596	+ };
	1597	+
	1598	+ emmc {
	1599	+ emmc_clk: emmc-clk {
	1600	+ rockchip,pins =
	1601	+ <3 RK_PB1 2 &pcfg_pull_none_8ma>;
	1602	+ };
	1603	+
	1604	+ emmc_cmd: emmc-cmd {
	1605	+ rockchip,pins =
	1606	+ <3 RK_PB0 2 &pcfg_pull_up_8ma>;
	1607	+ };
	1608	+
	1609	+ emmc_pwren: emmc-pwren {
	1610	+ rockchip,pins =
	1611	+ <3 RK_PB3 2 &pcfg_pull_none>;
	1612	+ };
	1613	+
	1614	+ emmc_rstn: emmc-rstn {
	1615	+ rockchip,pins =
	1616	+ <3 RK_PB2 2 &pcfg_pull_none>;
	1617	+ };
	1618	+
	1619	+ emmc_bus1: emmc-bus1 {
	1620	+ rockchip,pins =
	1621	+ <3 RK_PA0 2 &pcfg_pull_up_8ma>;
	1622	+ };
	1623	+
	1624	+ emmc_bus4: emmc-bus4 {
	1625	+ rockchip,pins =
	1626	+ <3 RK_PA0 2 &pcfg_pull_up_8ma>,
	1627	+ <3 RK_PA1 2 &pcfg_pull_up_8ma>,
	1628	+ <3 RK_PA2 2 &pcfg_pull_up_8ma>,
	1629	+ <3 RK_PA3 2 &pcfg_pull_up_8ma>;
	1630	+ };
	1631	+
	1632	+ emmc_bus8: emmc-bus8 {
	1633	+ rockchip,pins =
	1634	+ <3 RK_PA0 2 &pcfg_pull_up_8ma>,
	1635	+ <3 RK_PA1 2 &pcfg_pull_up_8ma>,
	1636	+ <3 RK_PA2 2 &pcfg_pull_up_8ma>,
	1637	+ <3 RK_PA3 2 &pcfg_pull_up_8ma>,
	1638	+ <3 RK_PA4 2 &pcfg_pull_up_8ma>,
	1639	+ <3 RK_PA5 2 &pcfg_pull_up_8ma>,
	1640	+ <3 RK_PA6 2 &pcfg_pull_up_8ma>,
	1641	+ <3 RK_PA7 2 &pcfg_pull_up_8ma>;
	1642	+ };
	1643	+ };
	1644	+
	1645	+ ext_micbias {
	1646	+ ext_micbias_en: ext-micbias-en {
	1647	+ rockchip,pins =
	1648	+ <0 RK_PC2 RK_FUNC_GPIO &pcfg_pull_down>;
	1649	+ };
	1650	+ };
	1651	+
	1652	+ flash {
	1653	+ flash_csn0: flash-csn0 {
	1654	+ rockchip,pins =
	1655	+ <3 RK_PB5 1 &pcfg_pull_none>;
	1656	+ };
	1657	+
	1658	+ flash_rdy: flash-rdy {
	1659	+ rockchip,pins =
	1660	+ <3 RK_PB4 1 &pcfg_pull_none>;
	1661	+ };
	1662	+
	1663	+ flash_ale: flash-ale {
	1664	+ rockchip,pins =
	1665	+ <3 RK_PB3 1 &pcfg_pull_none>;
	1666	+ };
	1667	+
	1668	+ flash_cle: flash-cle {
	1669	+ rockchip,pins =
	1670	+ <3 RK_PB1 1 &pcfg_pull_none>;
	1671	+ };
	1672	+
	1673	+ flash_wrn: flash-wrn {
	1674	+ rockchip,pins =
	1675	+ <3 RK_PB0 1 &pcfg_pull_none>;
	1676	+ };
	1677	+
	1678	+ flash_rdn: flash-rdn {
	1679	+ rockchip,pins =
	1680	+ <3 RK_PB2 1 &pcfg_pull_none>;
	1681	+ };
	1682	+
	1683	+ flash_bus8: flash-bus8 {
	1684	+ rockchip,pins =
	1685	+ <3 RK_PA0 1 &pcfg_pull_up_12ma>,
	1686	+ <3 RK_PA1 1 &pcfg_pull_up_12ma>,
	1687	+ <3 RK_PA2 1 &pcfg_pull_up_12ma>,
	1688	+ <3 RK_PA3 1 &pcfg_pull_up_12ma>,
	1689	+ <3 RK_PA4 1 &pcfg_pull_up_12ma>,
	1690	+ <3 RK_PA5 1 &pcfg_pull_up_12ma>,
	1691	+ <3 RK_PA6 1 &pcfg_pull_up_12ma>,
	1692	+ <3 RK_PA7 1 &pcfg_pull_up_12ma>;
	1693	+ };
	1694	+ };
	1695	+
	1696	+ gmac {
	1697	+ rmii_pins: rmii-pins {
	1698	+ rockchip,pins =
	1699	+ /* mac_txen */
	1700	+ <1 RK_PC1 3 &pcfg_pull_none_12ma>,
	1701	+ /* mac_txd1 */
	1702	+ <1 RK_PC3 3 &pcfg_pull_none_12ma>,
	1703	+ /* mac_txd0 */
	1704	+ <1 RK_PC2 3 &pcfg_pull_none_12ma>,
	1705	+ /* mac_rxd0 */
	1706	+ <1 RK_PC4 3 &pcfg_pull_none>,
	1707	+ /* mac_rxd1 */
	1708	+ <1 RK_PC5 3 &pcfg_pull_none>,
	1709	+ /* mac_rxer */
	1710	+ <1 RK_PB7 3 &pcfg_pull_none>,
	1711	+ /* mac_rxdv */
	1712	+ <1 RK_PC0 3 &pcfg_pull_none>,
	1713	+ /* mac_mdio */
	1714	+ <1 RK_PB6 3 &pcfg_pull_none>,
	1715	+ /* mac_mdc */
	1716	+ <1 RK_PB5 3 &pcfg_pull_none>;
	1717	+ };
	1718	+
	1719	+ mac_refclk_12ma: mac-refclk-12ma {
	1720	+ rockchip,pins =
	1721	+ <1 RK_PB4 3 &pcfg_pull_none_12ma>;
	1722	+ };
	1723	+
	1724	+ mac_refclk: mac-refclk {
	1725	+ rockchip,pins =
	1726	+ <1 RK_PB4 3 &pcfg_pull_none>;
	1727	+ };
	1728	+ };
	1729	+
	1730	+ gmac-m1 {
	1731	+ rmiim1_pins: rmiim1-pins {
	1732	+ rockchip,pins =
	1733	+ /* mac_txen */
	1734	+ <4 RK_PB7 2 &pcfg_pull_none_12ma>,
	1735	+ /* mac_txd1 */
	1736	+ <4 RK_PA5 2 &pcfg_pull_none_12ma>,
	1737	+ /* mac_txd0 */
	1738	+ <4 RK_PA4 2 &pcfg_pull_none_12ma>,
	1739	+ /* mac_rxd0 */
	1740	+ <4 RK_PA2 2 &pcfg_pull_none>,
	1741	+ /* mac_rxd1 */
	1742	+ <4 RK_PA3 2 &pcfg_pull_none>,
	1743	+ /* mac_rxer */
	1744	+ <4 RK_PA0 2 &pcfg_pull_none>,
	1745	+ /* mac_rxdv */
	1746	+ <4 RK_PA1 2 &pcfg_pull_none>,
	1747	+ /* mac_mdio */
	1748	+ <4 RK_PB6 2 &pcfg_pull_none>,
	1749	+ /* mac_mdc */
	1750	+ <4 RK_PB5 2 &pcfg_pull_none>;
	1751	+ };
	1752	+
	1753	+ macm1_refclk_12ma: macm1-refclk-12ma {
	1754	+ rockchip,pins =
	1755	+ <4 RK_PB4 2 &pcfg_pull_none_12ma>;
	1756	+ };
	1757	+
	1758	+ macm1_refclk: macm1-refclk {
	1759	+ rockchip,pins =
	1760	+ <4 RK_PB4 2 &pcfg_pull_none>;
	1761	+ };
	1762	+ };
	1763	+
1497	1764	i2c0 {
1498	1765	i2c0_xfer: i2c0-xfer {
1499	1766	rockchip,pins =
..	..	@@ -1545,17 +1812,17 @@
1545	1812	i2s_2ch_0 {
1546	1813	i2s_2ch_0_mclk: i2s-2ch-0-mclk {
1547	1814	rockchip,pins =
1548		- <4 RK_PB4 1 &pcfg_pull_none>;
	1815	+ <4 RK_PB4 1 &pcfg_pull_none_smt>;
1549	1816	};
1550	1817
1551	1818	i2s_2ch_0_sclk: i2s-2ch-0-sclk {
1552	1819	rockchip,pins =
1553		- <4 RK_PB5 1 &pcfg_pull_none>;
	1820	+ <4 RK_PB5 1 &pcfg_pull_none_smt>;
1554	1821	};
1555	1822
1556	1823	i2s_2ch_0_lrck: i2s-2ch-0-lrck {
1557	1824	rockchip,pins =
1558		- <4 RK_PB6 1 &pcfg_pull_none>;
	1825	+ <4 RK_PB6 1 &pcfg_pull_none_smt>;
1559	1826	};
1560	1827
1561	1828	i2s_2ch_0_sdo: i2s-2ch-0-sdo {
..	..	@@ -1572,27 +1839,27 @@
1572	1839	i2s_8ch_0 {
1573	1840	i2s_8ch_0_mclk: i2s-8ch-0-mclk {
1574	1841	rockchip,pins =
1575		- <2 RK_PA4 1 &pcfg_pull_none>;
	1842	+ <2 RK_PA4 1 &pcfg_pull_none_smt>;
1576	1843	};
1577	1844
1578	1845	i2s_8ch_0_sclktx: i2s-8ch-0-sclktx {
1579	1846	rockchip,pins =
1580		- <2 RK_PA5 1 &pcfg_pull_none>;
	1847	+ <2 RK_PA5 1 &pcfg_pull_none_smt>;
1581	1848	};
1582	1849
1583	1850	i2s_8ch_0_sclkrx: i2s-8ch-0-sclkrx {
1584	1851	rockchip,pins =
1585		- <2 RK_PA6 1 &pcfg_pull_none>;
	1852	+ <2 RK_PA6 1 &pcfg_pull_none_smt>;
1586	1853	};
1587	1854
1588	1855	i2s_8ch_0_lrcktx: i2s-8ch-0-lrcktx {
1589	1856	rockchip,pins =
1590		- <2 RK_PA7 1 &pcfg_pull_none>;
	1857	+ <2 RK_PA7 1 &pcfg_pull_none_smt>;
1591	1858	};
1592	1859
1593	1860	i2s_8ch_0_lrckrx: i2s-8ch-0-lrckrx {
1594	1861	rockchip,pins =
1595		- <2 RK_PB0 1 &pcfg_pull_none>;
	1862	+ <2 RK_PB0 1 &pcfg_pull_none_smt>;
1596	1863	};
1597	1864
1598	1865	i2s_8ch_0_sdo0: i2s-8ch-0-sdo0 {
..	..	@@ -1639,27 +1906,27 @@
1639	1906	i2s_8ch_1_m0 {
1640	1907	i2s_8ch_1_m0_mclk: i2s-8ch-1-m0-mclk {
1641	1908	rockchip,pins =
1642		- <1 RK_PA2 2 &pcfg_pull_none>;
	1909	+ <1 RK_PA2 2 &pcfg_pull_none_smt>;
1643	1910	};
1644	1911
1645	1912	i2s_8ch_1_m0_sclktx: i2s-8ch-1-m0-sclktx {
1646	1913	rockchip,pins =
1647		- <1 RK_PA3 2 &pcfg_pull_none>;
	1914	+ <1 RK_PA3 2 &pcfg_pull_none_smt>;
1648	1915	};
1649	1916
1650	1917	i2s_8ch_1_m0_sclkrx: i2s-8ch-1-m0-sclkrx {
1651	1918	rockchip,pins =
1652		- <1 RK_PA4 2 &pcfg_pull_none>;
	1919	+ <1 RK_PA4 2 &pcfg_pull_none_smt>;
1653	1920	};
1654	1921
1655	1922	i2s_8ch_1_m0_lrcktx: i2s-8ch-1-m0-lrcktx {
1656	1923	rockchip,pins =
1657		- <1 RK_PA5 2 &pcfg_pull_none>;
	1924	+ <1 RK_PA5 2 &pcfg_pull_none_smt>;
1658	1925	};
1659	1926
1660	1927	i2s_8ch_1_m0_lrckrx: i2s-8ch-1-m0-lrckrx {
1661	1928	rockchip,pins =
1662		- <1 RK_PA6 2 &pcfg_pull_none>;
	1929	+ <1 RK_PA6 2 &pcfg_pull_none_smt>;
1663	1930	};
1664	1931
1665	1932	i2s_8ch_1_m0_sdo0: i2s-8ch-1-m0-sdo0 {
..	..	@@ -1691,27 +1958,27 @@
1691	1958	i2s_8ch_1_m1 {
1692	1959	i2s_8ch_1_m1_mclk: i2s-8ch-1-m1-mclk {
1693	1960	rockchip,pins =
1694		- <1 RK_PB4 2 &pcfg_pull_none>;
	1961	+ <1 RK_PB4 2 &pcfg_pull_none_smt>;
1695	1962	};
1696	1963
1697	1964	i2s_8ch_1_m1_sclktx: i2s-8ch-1-m1-sclktx {
1698	1965	rockchip,pins =
1699		- <1 RK_PB5 2 &pcfg_pull_none>;
	1966	+ <1 RK_PB5 2 &pcfg_pull_none_smt>;
1700	1967	};
1701	1968
1702	1969	i2s_8ch_1_m1_sclkrx: i2s-8ch-1-m1-sclkrx {
1703	1970	rockchip,pins =
1704		- <1 RK_PB6 2 &pcfg_pull_none>;
	1971	+ <1 RK_PB6 2 &pcfg_pull_none_smt>;
1705	1972	};
1706	1973
1707	1974	i2s_8ch_1_m1_lrcktx: i2s-8ch-1-m1-lrcktx {
1708	1975	rockchip,pins =
1709		- <1 RK_PB7 2 &pcfg_pull_none>;
	1976	+ <1 RK_PB7 2 &pcfg_pull_none_smt>;
1710	1977	};
1711	1978
1712	1979	i2s_8ch_1_m1_lrckrx: i2s-8ch-1-m1-lrckrx {
1713	1980	rockchip,pins =
1714		- <1 RK_PC0 2 &pcfg_pull_none>;
	1981	+ <1 RK_PC0 2 &pcfg_pull_none_smt>;
1715	1982	};
1716	1983
1717	1984	i2s_8ch_1_m1_sdo0: i2s-8ch-1-m1-sdo0 {
..	..	@@ -1744,81 +2011,105 @@
1744	2011	lcdc_ctl: lcdc-ctl {
1745	2012	rockchip,pins =
1746	2013	/* dclk */
1747		- <1 RK_PA0 1 &pcfg_pull_none>,
	2014	+ <1 RK_PA0 1 &pcfg_pull_none_4ma>,
1748	2015	/* hsync */
1749		- <1 RK_PA1 1 &pcfg_pull_none>,
	2016	+ <1 RK_PA1 1 &pcfg_pull_none_4ma>,
1750	2017	/* vsync */
1751		- <1 RK_PA2 1 &pcfg_pull_none>,
	2018	+ <1 RK_PA2 1 &pcfg_pull_none_4ma>,
1752	2019	/* den */
1753		- <1 RK_PA3 1 &pcfg_pull_none>,
	2020	+ <1 RK_PA3 1 &pcfg_pull_none_4ma>,
1754	2021	/* d0 */
1755		- <1 RK_PA4 1 &pcfg_pull_none>,
	2022	+ <1 RK_PA4 1 &pcfg_pull_none_4ma>,
1756	2023	/* d1 */
1757		- <1 RK_PA5 1 &pcfg_pull_none>,
	2024	+ <1 RK_PA5 1 &pcfg_pull_none_4ma>,
1758	2025	/* d2 */
1759		- <1 RK_PA6 1 &pcfg_pull_none>,
	2026	+ <1 RK_PA6 1 &pcfg_pull_none_4ma>,
1760	2027	/* d3 */
1761		- <1 RK_PA7 1 &pcfg_pull_none>,
	2028	+ <1 RK_PA7 1 &pcfg_pull_none_4ma>,
1762	2029	/* d4 */
1763		- <1 RK_PB0 1 &pcfg_pull_none>,
	2030	+ <1 RK_PB0 1 &pcfg_pull_none_4ma>,
1764	2031	/* d5 */
1765		- <1 RK_PB1 1 &pcfg_pull_none>,
	2032	+ <1 RK_PB1 1 &pcfg_pull_none_4ma>,
1766	2033	/* d6 */
1767		- <1 RK_PB2 1 &pcfg_pull_none>,
	2034	+ <1 RK_PB2 1 &pcfg_pull_none_4ma>,
1768	2035	/* d7 */
1769		- <1 RK_PB3 1 &pcfg_pull_none>,
	2036	+ <1 RK_PB3 1 &pcfg_pull_none_4ma>,
1770	2037	/* d8 */
1771		- <1 RK_PB4 1 &pcfg_pull_none>,
	2038	+ <1 RK_PB4 1 &pcfg_pull_none_4ma>,
1772	2039	/* d9 */
1773		- <1 RK_PB5 1 &pcfg_pull_none>,
	2040	+ <1 RK_PB5 1 &pcfg_pull_none_4ma>,
1774	2041	/* d10 */
1775		- <1 RK_PB6 1 &pcfg_pull_none>,
	2042	+ <1 RK_PB6 1 &pcfg_pull_none_4ma>,
1776	2043	/* d11 */
1777		- <1 RK_PB7 1 &pcfg_pull_none>,
	2044	+ <1 RK_PB7 1 &pcfg_pull_none_4ma>,
1778	2045	/* d12 */
1779		- <1 RK_PC0 1 &pcfg_pull_none>,
	2046	+ <1 RK_PC0 1 &pcfg_pull_none_4ma>,
1780	2047	/* d13 */
1781		- <1 RK_PC1 1 &pcfg_pull_none>,
	2048	+ <1 RK_PC1 1 &pcfg_pull_none_4ma>,
1782	2049	/* d14 */
1783		- <1 RK_PC2 1 &pcfg_pull_none>,
	2050	+ <1 RK_PC2 1 &pcfg_pull_none_4ma>,
1784	2051	/* d15 */
1785		- <1 RK_PC3 1 &pcfg_pull_none>,
	2052	+ <1 RK_PC3 1 &pcfg_pull_none_4ma>,
1786	2053	/* d16 */
1787		- <1 RK_PC4 1 &pcfg_pull_none>,
	2054	+ <1 RK_PC4 1 &pcfg_pull_none_4ma>,
1788	2055	/* d17 */
1789		- <1 RK_PC5 1 &pcfg_pull_none>;
	2056	+ <1 RK_PC5 1 &pcfg_pull_none_4ma>;
1790	2057	};
1791	2058
1792	2059	lcdc_rgb888_m0: lcdc-rgb888-m0 {
1793	2060	rockchip,pins =
1794	2061	/* d18 */
1795		- <1 RK_PC6 6 &pcfg_pull_none>,
	2062	+ <1 RK_PC6 6 &pcfg_pull_none_4ma>,
1796	2063	/* d19 */
1797		- <1 RK_PC7 6 &pcfg_pull_none>,
	2064	+ <1 RK_PC7 6 &pcfg_pull_none_4ma>,
1798	2065	/* d20 */
1799		- <2 RK_PB1 3 &pcfg_pull_none>,
	2066	+ <2 RK_PB1 3 &pcfg_pull_none_4ma>,
1800	2067	/* d21 */
1801		- <2 RK_PB2 3 &pcfg_pull_none>,
	2068	+ <2 RK_PB2 3 &pcfg_pull_none_4ma>,
1802	2069	/* d22 */
1803		- <2 RK_PB7 3 &pcfg_pull_none>,
	2070	+ <2 RK_PB7 3 &pcfg_pull_none_4ma>,
1804	2071	/* d23 */
1805		- <2 RK_PC0 3 &pcfg_pull_none>;
	2072	+ <2 RK_PC0 3 &pcfg_pull_none_4ma>;
1806	2073	};
1807	2074
1808	2075	lcdc_rgb888_m1: lcdc-rgb888-m1 {
1809	2076	rockchip,pins =
1810	2077	/* d18 */
1811		- <3 RK_PA6 3 &pcfg_pull_none>,
	2078	+ <3 RK_PA6 3 &pcfg_pull_none_4ma>,
1812	2079	/* d19 */
1813		- <3 RK_PA7 3 &pcfg_pull_none>,
	2080	+ <3 RK_PA7 3 &pcfg_pull_none_4ma>,
1814	2081	/* d20 */
1815		- <3 RK_PB0 3 &pcfg_pull_none>,
	2082	+ <3 RK_PB0 3 &pcfg_pull_none_4ma>,
1816	2083	/* d21 */
1817		- <3 RK_PB1 3 &pcfg_pull_none>,
	2084	+ <3 RK_PB1 3 &pcfg_pull_none_4ma>,
1818	2085	/* d22 */
1819		- <3 RK_PB2 4 &pcfg_pull_none>,
	2086	+ <3 RK_PB2 4 &pcfg_pull_none_4ma>,
1820	2087	/* d23 */
1821		- <3 RK_PB3 4 &pcfg_pull_none>;
	2088	+ <3 RK_PB3 4 &pcfg_pull_none_4ma>;
	2089	+ };
	2090	+ };
	2091	+
	2092	+ owire-m0 {
	2093	+ owirem0_pins: owirem0-pins {
	2094	+ rockchip,pins =
	2095	+ /* owire_m0 */
	2096	+ <0 RK_PB3 3 &pcfg_pull_none>;
	2097	+ };
	2098	+ };
	2099	+
	2100	+ owire-m1 {
	2101	+ owirem1_pins: owirem1-pins {
	2102	+ rockchip,pins =
	2103	+ /* owire_m1 */
	2104	+ <1 RK_PC6 7 &pcfg_pull_none>;
	2105	+ };
	2106	+ };
	2107	+
	2108	+ owire-m2 {
	2109	+ owirem2_pins: owirem2-pins {
	2110	+ rockchip,pins =
	2111	+ /* owire_m2 */
	2112	+ <2 RK_PA2 5 &pcfg_pull_none>;
1822	2113	};
1823	2114	};
1824	2115
..	..	@@ -1908,6 +2199,253 @@
1908	2199	};
1909	2200	};
1910	2201
	2202	+ pwm0 {
	2203	+ pwm0_pin: pwm0-pin {
	2204	+ rockchip,pins =
	2205	+ <0 RK_PB5 1 &pcfg_pull_none>;
	2206	+ };
	2207	+
	2208	+ pwm0_pin_pull_down: pwm0-pin-pull-down {
	2209	+ rockchip,pins =
	2210	+ <0 RK_PB5 1 &pcfg_pull_down>;
	2211	+ };
	2212	+ };
	2213	+
	2214	+ pwm1 {
	2215	+ pwm1_pin: pwm1-pin {
	2216	+ rockchip,pins =
	2217	+ <0 RK_PB6 1 &pcfg_pull_none>;
	2218	+ };
	2219	+
	2220	+ pwm1_pin_pull_down: pwm1-pin-pull-down {
	2221	+ rockchip,pins =
	2222	+ <0 RK_PB6 1 &pcfg_pull_down>;
	2223	+ };
	2224	+ };
	2225	+
	2226	+ pwm2 {
	2227	+ pwm2_pin: pwm2-pin {
	2228	+ rockchip,pins =
	2229	+ <0 RK_PB7 1 &pcfg_pull_none>;
	2230	+ };
	2231	+
	2232	+ pwm2_pin_pull_down: pwm2-pin-pull-down {
	2233	+ rockchip,pins =
	2234	+ <0 RK_PB7 1 &pcfg_pull_down>;
	2235	+ };
	2236	+ };
	2237	+
	2238	+ pwm3 {
	2239	+ pwm3_pin: pwm3-pin {
	2240	+ rockchip,pins =
	2241	+ <0 RK_PC0 1 &pcfg_pull_none>;
	2242	+ };
	2243	+
	2244	+ pwm3_pin_pull_down: pwm3-pin-pull-down {
	2245	+ rockchip,pins =
	2246	+ <0 RK_PC0 1 &pcfg_pull_down>;
	2247	+ };
	2248	+ };
	2249	+
	2250	+ pwm4 {
	2251	+ pwm4_pin: pwm4-pin {
	2252	+ rockchip,pins =
	2253	+ <0 RK_PA1 2 &pcfg_pull_none>;
	2254	+ };
	2255	+
	2256	+ pwm4_pin_pull_down: pwm4-pin-pull-down {
	2257	+ rockchip,pins =
	2258	+ <0 RK_PA1 2 &pcfg_pull_down>;
	2259	+ };
	2260	+ };
	2261	+
	2262	+ pwm5 {
	2263	+ pwm5_pin: pwm5-pin {
	2264	+ rockchip,pins =
	2265	+ <0 RK_PC1 2 &pcfg_pull_none>;
	2266	+ };
	2267	+
	2268	+ pwm5_pin_pull_down: pwm5-pin-pull-down {
	2269	+ rockchip,pins =
	2270	+ <0 RK_PC1 2 &pcfg_pull_down>;
	2271	+ };
	2272	+ };
	2273	+
	2274	+ pwm6 {
	2275	+ pwm6_pin: pwm6-pin {
	2276	+ rockchip,pins =
	2277	+ <0 RK_PC2 2 &pcfg_pull_none>;
	2278	+ };
	2279	+
	2280	+ pwm6_pin_pull_down: pwm6-pin-pull-down {
	2281	+ rockchip,pins =
	2282	+ <0 RK_PC2 2 &pcfg_pull_down>;
	2283	+ };
	2284	+ };
	2285	+
	2286	+ pwm7 {
	2287	+ pwm7_pin: pwm7-pin {
	2288	+ rockchip,pins =
	2289	+ <2 RK_PB0 2 &pcfg_pull_none>;
	2290	+ };
	2291	+
	2292	+ pwm7_pin_pull_down: pwm7-pin-pull-down {
	2293	+ rockchip,pins =
	2294	+ <2 RK_PB0 2 &pcfg_pull_down>;
	2295	+ };
	2296	+ };
	2297	+
	2298	+ pwm8 {
	2299	+ pwm8_pin: pwm8-pin {
	2300	+ rockchip,pins =
	2301	+ <2 RK_PB2 2 &pcfg_pull_none>;
	2302	+ };
	2303	+
	2304	+ pwm8_pin_pull_down: pwm8-pin-pull-down {
	2305	+ rockchip,pins =
	2306	+ <2 RK_PB2 2 &pcfg_pull_down>;
	2307	+ };
	2308	+ };
	2309	+
	2310	+ pwm9 {
	2311	+ pwm9_pin: pwm9-pin {
	2312	+ rockchip,pins =
	2313	+ <2 RK_PB3 2 &pcfg_pull_none>;
	2314	+ };
	2315	+
	2316	+ pwm9_pin_pull_down: pwm9-pin-pull-down {
	2317	+ rockchip,pins =
	2318	+ <2 RK_PB3 2 &pcfg_pull_down>;
	2319	+ };
	2320	+ };
	2321	+
	2322	+ pwm10 {
	2323	+ pwm10_pin: pwm10-pin {
	2324	+ rockchip,pins =
	2325	+ <2 RK_PB4 2 &pcfg_pull_none>;
	2326	+ };
	2327	+
	2328	+ pwm10_pin_pull_down: pwm10-pin-pull-down {
	2329	+ rockchip,pins =
	2330	+ <2 RK_PB4 2 &pcfg_pull_down>;
	2331	+ };
	2332	+ };
	2333	+
	2334	+ pwm11 {
	2335	+ pwm11_pin: pwm11-pin {
	2336	+ rockchip,pins =
	2337	+ <2 RK_PC0 4 &pcfg_pull_none>;
	2338	+ };
	2339	+
	2340	+ pwm11_pin_pull_down: pwm11-pin-pull-down {
	2341	+ rockchip,pins =
	2342	+ <2 RK_PC0 4 &pcfg_pull_down>;
	2343	+ };
	2344	+ };
	2345	+
	2346	+ rtc {
	2347	+ rtc_32k: rtc-32k {
	2348	+ rockchip,pins =
	2349	+ <0 RK_PC3 1 &pcfg_pull_none>;
	2350	+ };
	2351	+ };
	2352	+
	2353	+ sdmmc {
	2354	+ sdmmc_clk: sdmmc-clk {
	2355	+ rockchip,pins =
	2356	+ <4 RK_PD5 1 &pcfg_pull_none_4ma>;
	2357	+ };
	2358	+
	2359	+ sdmmc_cmd: sdmmc-cmd {
	2360	+ rockchip,pins =
	2361	+ <4 RK_PD4 1 &pcfg_pull_up_4ma>;
	2362	+ };
	2363	+
	2364	+ sdmmc_det: sdmmc-det {
	2365	+ rockchip,pins =
	2366	+ <0 RK_PA3 1 &pcfg_pull_up_4ma>;
	2367	+ };
	2368	+
	2369	+ sdmmc_pwren: sdmmc-pwren {
	2370	+ rockchip,pins =
	2371	+ <4 RK_PD6 1 &pcfg_pull_none_4ma>;
	2372	+ };
	2373	+
	2374	+ sdmmc_bus1: sdmmc-bus1 {
	2375	+ rockchip,pins =
	2376	+ <4 RK_PD0 1 &pcfg_pull_up_4ma>;
	2377	+ };
	2378	+
	2379	+ sdmmc_bus4: sdmmc-bus4 {
	2380	+ rockchip,pins =
	2381	+ <4 RK_PD0 1 &pcfg_pull_up_4ma>,
	2382	+ <4 RK_PD1 1 &pcfg_pull_up_4ma>,
	2383	+ <4 RK_PD2 1 &pcfg_pull_up_4ma>,
	2384	+ <4 RK_PD3 1 &pcfg_pull_up_4ma>;
	2385	+ };
	2386	+
	2387	+ sdmmc_gpio: sdmmc-gpio {
	2388	+ rockchip,pins =
	2389	+ <4 RK_PD0 RK_FUNC_GPIO &pcfg_pull_up_4ma>,
	2390	+ <4 RK_PD1 RK_FUNC_GPIO &pcfg_pull_up_4ma>,
	2391	+ <4 RK_PD2 RK_FUNC_GPIO &pcfg_pull_up_4ma>,
	2392	+ <4 RK_PD3 RK_FUNC_GPIO &pcfg_pull_up_4ma>,
	2393	+ <4 RK_PD4 RK_FUNC_GPIO &pcfg_pull_up_4ma>,
	2394	+ <4 RK_PD5 RK_FUNC_GPIO &pcfg_pull_up_4ma>,
	2395	+ <4 RK_PD6 RK_FUNC_GPIO &pcfg_pull_up_4ma>;
	2396	+ };
	2397	+ };
	2398	+
	2399	+ sdio {
	2400	+ sdio_clk: sdio-clk {
	2401	+ rockchip,pins =
	2402	+ <4 RK_PA5 1 &pcfg_pull_none_8ma>;
	2403	+ };
	2404	+
	2405	+ sdio_cmd: sdio-cmd {
	2406	+ rockchip,pins =
	2407	+ <4 RK_PA4 1 &pcfg_pull_up_8ma>;
	2408	+ };
	2409	+
	2410	+ sdio_pwren: sdio-pwren {
	2411	+ rockchip,pins =
	2412	+ <0 RK_PA2 1 &pcfg_pull_none_8ma>;
	2413	+ };
	2414	+
	2415	+ sdio_wrpt: sdio-wrpt {
	2416	+ rockchip,pins =
	2417	+ <0 RK_PA1 1 &pcfg_pull_none_8ma>;
	2418	+ };
	2419	+
	2420	+ sdio_intn: sdio-intn {
	2421	+ rockchip,pins =
	2422	+ <0 RK_PA0 1 &pcfg_pull_none_8ma>;
	2423	+ };
	2424	+
	2425	+ sdio_bus1: sdio-bus1 {
	2426	+ rockchip,pins =
	2427	+ <4 RK_PA0 1 &pcfg_pull_up_8ma>;
	2428	+ };
	2429	+
	2430	+ sdio_bus4: sdio-bus4 {
	2431	+ rockchip,pins =
	2432	+ <4 RK_PA0 1 &pcfg_pull_up_8ma>,
	2433	+ <4 RK_PA1 1 &pcfg_pull_up_8ma>,
	2434	+ <4 RK_PA2 1 &pcfg_pull_up_8ma>,
	2435	+ <4 RK_PA3 1 &pcfg_pull_up_8ma>;
	2436	+ };
	2437	+
	2438	+ sdio_gpio: sdio-gpio {
	2439	+ rockchip,pins =
	2440	+ <4 RK_PA0 RK_FUNC_GPIO &pcfg_pull_up_4ma>,
	2441	+ <4 RK_PA1 RK_FUNC_GPIO &pcfg_pull_up_4ma>,
	2442	+ <4 RK_PA2 RK_FUNC_GPIO &pcfg_pull_up_4ma>,
	2443	+ <4 RK_PA3 RK_FUNC_GPIO &pcfg_pull_up_4ma>,
	2444	+ <4 RK_PA4 RK_FUNC_GPIO &pcfg_pull_up_4ma>,
	2445	+ <4 RK_PA5 RK_FUNC_GPIO &pcfg_pull_up_4ma>;
	2446	+ };
	2447	+ };
	2448	+
1911	2449	spdif_in {
1912	2450	spdif_in: spdif-in {
1913	2451	rockchip,pins =
..	..	@@ -1919,116 +2457,6 @@
1919	2457	spdif_out: spdif-out {
1920	2458	rockchip,pins =
1921	2459	<0 RK_PC1 1 &pcfg_pull_none>;
1922		- };
1923		- };
1924		-
1925		- tsadc {
1926		- tsadc_otp_gpio: tsadc-otp-gpio {
1927		- rockchip,pins =
1928		- <0 RK_PB2 RK_FUNC_GPIO &pcfg_pull_none>;
1929		- };
1930		-
1931		- tsadc_otp_out: tsadc-otp-out {
1932		- rockchip,pins =
1933		- <0 RK_PB2 1 &pcfg_pull_none>;
1934		- };
1935		- };
1936		-
1937		- uart0 {
1938		- uart0_xfer: uart0-xfer {
1939		- rockchip,pins =
1940		- <2 RK_PA1 1 &pcfg_pull_up>,
1941		- <2 RK_PA0 1 &pcfg_pull_up>;
1942		- };
1943		-
1944		- uart0_cts: uart0-cts {
1945		- rockchip,pins =
1946		- <2 RK_PA2 1 &pcfg_pull_none>;
1947		- };
1948		-
1949		- uart0_rts: uart0-rts {
1950		- rockchip,pins =
1951		- <2 RK_PA3 1 &pcfg_pull_none>;
1952		- };
1953		-
1954		- uart0_rts_gpio: uart0-rts-gpio {
1955		- rockchip,pins =
1956		- <2 RK_PA3 RK_FUNC_GPIO &pcfg_pull_none>;
1957		- };
1958		- };
1959		-
1960		- uart1 {
1961		- uart1_xfer: uart1-xfer {
1962		- rockchip,pins =
1963		- <1 RK_PD1 1 &pcfg_pull_up>,
1964		- <1 RK_PD0 1 &pcfg_pull_up>;
1965		- };
1966		-
1967		- uart1_cts: uart1-cts {
1968		- rockchip,pins =
1969		- <1 RK_PC6 1 &pcfg_pull_none>;
1970		- };
1971		-
1972		- uart1_rts: uart1-rts {
1973		- rockchip,pins =
1974		- <1 RK_PC7 1 &pcfg_pull_none>;
1975		- };
1976		- };
1977		-
1978		- uart2-m0 {
1979		- uart2m0_xfer: uart2m0-xfer {
1980		- rockchip,pins =
1981		- <1 RK_PC7 2 &pcfg_pull_up>,
1982		- <1 RK_PC6 2 &pcfg_pull_up>;
1983		- };
1984		- };
1985		-
1986		- uart2-m1 {
1987		- uart2m1_xfer: uart2m1-xfer {
1988		- rockchip,pins =
1989		- <4 RK_PD3 2 &pcfg_pull_up>,
1990		- <4 RK_PD2 2 &pcfg_pull_up>;
1991		- };
1992		- };
1993		-
1994		- uart3 {
1995		- uart3_xfer: uart3-xfer {
1996		- rockchip,pins =
1997		- <3 RK_PB5 4 &pcfg_pull_up>,
1998		- <3 RK_PB4 4 &pcfg_pull_up>;
1999		- };
2000		- };
2001		-
2002		- uart3-m1 {
2003		- uart3m1_xfer: uart3m1-xfer {
2004		- rockchip,pins =
2005		- <0 RK_PC2 3 &pcfg_pull_up>,
2006		- <0 RK_PC1 3 &pcfg_pull_up>;
2007		- };
2008		- };
2009		-
2010		- uart4 {
2011		-
2012		- uart4_xfer: uart4-xfer {
2013		- rockchip,pins =
2014		- <4 RK_PB1 1 &pcfg_pull_up>,
2015		- <4 RK_PB0 1 &pcfg_pull_up>;
2016		- };
2017		-
2018		- uart4_cts: uart4-cts {
2019		- rockchip,pins =
2020		- <4 RK_PA6 1 &pcfg_pull_none>;
2021		-
2022		- };
2023		-
2024		- uart4_rts: uart4-rts {
2025		- rockchip,pins =
2026		- <4 RK_PA7 1 &pcfg_pull_none>;
2027		- };
2028		-
2029		- uart4_rts_gpio: uart4-rts-gpio {
2030		- rockchip,pins =
2031		- <4 RK_PA7 RK_FUNC_GPIO &pcfg_pull_none>;
2032	2460	};
2033	2461	};
2034	2462
..	..	@@ -2186,464 +2614,113 @@
2186	2614	};
2187	2615	};
2188	2616
2189		- sdmmc {
2190		- sdmmc_clk: sdmmc-clk {
	2617	+ tsadc {
	2618	+ tsadc_otp_pin: tsadc-otp-pin {
2191	2619	rockchip,pins =
2192		- <4 RK_PD5 1 &pcfg_pull_none_4ma>;
	2620	+ <0 RK_PB2 0 &pcfg_pull_none>;
2193	2621	};
2194	2622
2195		- sdmmc_cmd: sdmmc-cmd {
	2623	+ tsadc_otp_out: tsadc-otp-out {
2196	2624	rockchip,pins =
2197		- <4 RK_PD4 1 &pcfg_pull_up_4ma>;
2198		- };
2199		-
2200		- sdmmc_det: sdmmc-det {
2201		- rockchip,pins =
2202		- <0 RK_PA3 1 &pcfg_pull_up_4ma>;
2203		- };
2204		-
2205		- sdmmc_pwren: sdmmc-pwren {
2206		- rockchip,pins =
2207		- <4 RK_PD6 1 &pcfg_pull_none_4ma>;
2208		- };
2209		-
2210		- sdmmc_bus1: sdmmc-bus1 {
2211		- rockchip,pins =
2212		- <4 RK_PD0 1 &pcfg_pull_up_4ma>;
2213		- };
2214		-
2215		- sdmmc_bus4: sdmmc-bus4 {
2216		- rockchip,pins =
2217		- <4 RK_PD0 1 &pcfg_pull_up_4ma>,
2218		- <4 RK_PD1 1 &pcfg_pull_up_4ma>,
2219		- <4 RK_PD2 1 &pcfg_pull_up_4ma>,
2220		- <4 RK_PD3 1 &pcfg_pull_up_4ma>;
2221		- };
2222		-
2223		- sdmmc_gpio: sdmmc-gpio {
2224		- rockchip,pins =
2225		- <4 RK_PD0 RK_FUNC_GPIO &pcfg_pull_up_4ma>,
2226		- <4 RK_PD1 RK_FUNC_GPIO &pcfg_pull_up_4ma>,
2227		- <4 RK_PD2 RK_FUNC_GPIO &pcfg_pull_up_4ma>,
2228		- <4 RK_PD3 RK_FUNC_GPIO &pcfg_pull_up_4ma>,
2229		- <4 RK_PD4 RK_FUNC_GPIO &pcfg_pull_up_4ma>,
2230		- <4 RK_PD5 RK_FUNC_GPIO &pcfg_pull_up_4ma>,
2231		- <4 RK_PD6 RK_FUNC_GPIO &pcfg_pull_up_4ma>;
	2625	+ <0 RK_PB2 1 &pcfg_pull_none>;
2232	2626	};
2233	2627	};
2234	2628
2235		- sdio {
2236		- sdio_clk: sdio-clk {
	2629	+ uart0 {
	2630	+ uart0_xfer: uart0-xfer {
2237	2631	rockchip,pins =
2238		- <4 RK_PA5 1 &pcfg_pull_none_8ma>;
	2632	+ <2 RK_PA1 1 &pcfg_pull_up>,
	2633	+ <2 RK_PA0 1 &pcfg_pull_up>;
2239	2634	};
2240	2635
2241		- sdio_cmd: sdio-cmd {
	2636	+ uart0_cts: uart0-cts {
2242	2637	rockchip,pins =
2243		- <4 RK_PA4 1 &pcfg_pull_up_8ma>;
	2638	+ <2 RK_PA2 1 &pcfg_pull_none>;
2244	2639	};
2245	2640
2246		- sdio_pwren: sdio-pwren {
	2641	+ uart0_rts: uart0-rts {
2247	2642	rockchip,pins =
2248		- <0 RK_PA2 1 &pcfg_pull_none_8ma>;
	2643	+ <2 RK_PA3 1 &pcfg_pull_none>;
2249	2644	};
2250	2645
2251		- sdio_wrpt: sdio-wrpt {
	2646	+ uart0_rts_pin: uart0-rts-pin {
2252	2647	rockchip,pins =
2253		- <0 RK_PA1 1 &pcfg_pull_none_8ma>;
2254		- };
2255		-
2256		- sdio_intn: sdio-intn {
2257		- rockchip,pins =
2258		- <0 RK_PA0 1 &pcfg_pull_none_8ma>;
2259		- };
2260		-
2261		- sdio_bus1: sdio-bus1 {
2262		- rockchip,pins =
2263		- <4 RK_PA0 1 &pcfg_pull_up_8ma>;
2264		- };
2265		-
2266		- sdio_bus4: sdio-bus4 {
2267		- rockchip,pins =
2268		- <4 RK_PA0 1 &pcfg_pull_up_8ma>,
2269		- <4 RK_PA1 1 &pcfg_pull_up_8ma>,
2270		- <4 RK_PA2 1 &pcfg_pull_up_8ma>,
2271		- <4 RK_PA3 1 &pcfg_pull_up_8ma>;
2272		- };
2273		-
2274		- sdio_gpio: sdio-gpio {
2275		- rockchip,pins =
2276		- <4 RK_PA0 RK_FUNC_GPIO &pcfg_pull_up_4ma>,
2277		- <4 RK_PA1 RK_FUNC_GPIO &pcfg_pull_up_4ma>,
2278		- <4 RK_PA2 RK_FUNC_GPIO &pcfg_pull_up_4ma>,
2279		- <4 RK_PA3 RK_FUNC_GPIO &pcfg_pull_up_4ma>,
2280		- <4 RK_PA4 RK_FUNC_GPIO &pcfg_pull_up_4ma>,
2281		- <4 RK_PA5 RK_FUNC_GPIO &pcfg_pull_up_4ma>;
	2648	+ <2 RK_PA3 0 &pcfg_pull_none>;
2282	2649	};
2283	2650	};
2284	2651
2285		- emmc {
2286		- emmc_clk: emmc-clk {
	2652	+ uart1 {
	2653	+ uart1_xfer: uart1-xfer {
2287	2654	rockchip,pins =
2288		- <3 RK_PB1 2 &pcfg_pull_none_8ma>;
	2655	+ <1 RK_PD1 1 &pcfg_pull_up>,
	2656	+ <1 RK_PD0 1 &pcfg_pull_up>;
2289	2657	};
2290	2658
2291		- emmc_cmd: emmc-cmd {
	2659	+ uart1_cts: uart1-cts {
2292	2660	rockchip,pins =
2293		- <3 RK_PB0 2 &pcfg_pull_up_8ma>;
	2661	+ <1 RK_PC6 1 &pcfg_pull_none>;
2294	2662	};
2295	2663
2296		- emmc_pwren: emmc-pwren {
	2664	+ uart1_rts: uart1-rts {
2297	2665	rockchip,pins =
2298		- <3 RK_PB3 2 &pcfg_pull_none>;
2299		- };
2300		-
2301		- emmc_rstn: emmc-rstn {
2302		- rockchip,pins =
2303		- <3 RK_PB2 2 &pcfg_pull_none>;
2304		- };
2305		-
2306		- emmc_bus1: emmc-bus1 {
2307		- rockchip,pins =
2308		- <3 RK_PA0 2 &pcfg_pull_up_8ma>;
2309		- };
2310		-
2311		- emmc_bus4: emmc-bus4 {
2312		- rockchip,pins =
2313		- <3 RK_PA0 2 &pcfg_pull_up_8ma>,
2314		- <3 RK_PA1 2 &pcfg_pull_up_8ma>,
2315		- <3 RK_PA2 2 &pcfg_pull_up_8ma>,
2316		- <3 RK_PA3 2 &pcfg_pull_up_8ma>;
2317		- };
2318		-
2319		- emmc_bus8: emmc-bus8 {
2320		- rockchip,pins =
2321		- <3 RK_PA0 2 &pcfg_pull_up_8ma>,
2322		- <3 RK_PA1 2 &pcfg_pull_up_8ma>,
2323		- <3 RK_PA2 2 &pcfg_pull_up_8ma>,
2324		- <3 RK_PA3 2 &pcfg_pull_up_8ma>,
2325		- <3 RK_PA4 2 &pcfg_pull_up_8ma>,
2326		- <3 RK_PA5 2 &pcfg_pull_up_8ma>,
2327		- <3 RK_PA6 2 &pcfg_pull_up_8ma>,
2328		- <3 RK_PA7 2 &pcfg_pull_up_8ma>;
	2666	+ <1 RK_PC7 1 &pcfg_pull_none>;
2329	2667	};
2330	2668	};
2331	2669
2332		- flash {
2333		- flash_csn0: flash-csn0 {
	2670	+ uart2-m0 {
	2671	+ uart2m0_xfer: uart2m0-xfer {
2334	2672	rockchip,pins =
2335		- <3 RK_PB5 1 &pcfg_pull_none>;
2336		- };
2337		-
2338		- flash_rdy: flash-rdy {
2339		- rockchip,pins =
2340		- <3 RK_PB4 1 &pcfg_pull_none>;
2341		- };
2342		-
2343		- flash_ale: flash-ale {
2344		- rockchip,pins =
2345		- <3 RK_PB3 1 &pcfg_pull_none>;
2346		- };
2347		-
2348		- flash_cle: flash-cle {
2349		- rockchip,pins =
2350		- <3 RK_PB1 1 &pcfg_pull_none>;
2351		- };
2352		-
2353		- flash_wrn: flash-wrn {
2354		- rockchip,pins =
2355		- <3 RK_PB0 1 &pcfg_pull_none>;
2356		- };
2357		-
2358		- flash_rdn: flash-rdn {
2359		- rockchip,pins =
2360		- <3 RK_PB2 1 &pcfg_pull_none>;
2361		- };
2362		-
2363		- flash_bus8: flash-bus8 {
2364		- rockchip,pins =
2365		- <3 RK_PA0 1 &pcfg_pull_up_12ma>,
2366		- <3 RK_PA1 1 &pcfg_pull_up_12ma>,
2367		- <3 RK_PA2 1 &pcfg_pull_up_12ma>,
2368		- <3 RK_PA3 1 &pcfg_pull_up_12ma>,
2369		- <3 RK_PA4 1 &pcfg_pull_up_12ma>,
2370		- <3 RK_PA5 1 &pcfg_pull_up_12ma>,
2371		- <3 RK_PA6 1 &pcfg_pull_up_12ma>,
2372		- <3 RK_PA7 1 &pcfg_pull_up_12ma>;
	2673	+ <1 RK_PC7 2 &pcfg_pull_up>,
	2674	+ <1 RK_PC6 2 &pcfg_pull_up>;
2373	2675	};
2374	2676	};
2375	2677
2376		- pwm0 {
2377		- pwm0_pin: pwm0-pin {
	2678	+ uart2-m1 {
	2679	+ uart2m1_xfer: uart2m1-xfer {
2378	2680	rockchip,pins =
2379		- <0 RK_PB5 1 &pcfg_pull_none>;
2380		- };
2381		-
2382		- pwm0_pin_pull_down: pwm0-pin-pull-down {
2383		- rockchip,pins =
2384		- <0 RK_PB5 1 &pcfg_pull_down>;
	2681	+ <4 RK_PD3 2 &pcfg_pull_up>,
	2682	+ <4 RK_PD2 2 &pcfg_pull_up>;
2385	2683	};
2386	2684	};
2387	2685
2388		- pwm1 {
2389		- pwm1_pin: pwm1-pin {
	2686	+ uart3 {
	2687	+ uart3_xfer: uart3-xfer {
2390	2688	rockchip,pins =
2391		- <0 RK_PB6 1 &pcfg_pull_none>;
2392		- };
2393		-
2394		- pwm1_pin_pull_down: pwm1-pin-pull-down {
2395		- rockchip,pins =
2396		- <0 RK_PB6 1 &pcfg_pull_down>;
	2689	+ <3 RK_PB5 4 &pcfg_pull_up>,
	2690	+ <3 RK_PB4 4 &pcfg_pull_up>;
2397	2691	};
2398	2692	};
2399	2693
2400		- pwm2 {
2401		- pwm2_pin: pwm2-pin {
	2694	+ uart3-m1 {
	2695	+ uart3m1_xfer: uart3m1-xfer {
2402	2696	rockchip,pins =
2403		- <0 RK_PB7 1 &pcfg_pull_none>;
2404		- };
2405		-
2406		- pwm2_pin_pull_down: pwm2-pin-pull-down {
2407		- rockchip,pins =
2408		- <0 RK_PB7 1 &pcfg_pull_down>;
	2697	+ <0 RK_PC2 3 &pcfg_pull_up>,
	2698	+ <0 RK_PC1 3 &pcfg_pull_up>;
2409	2699	};
2410	2700	};
2411	2701
2412		- pwm3 {
2413		- pwm3_pin: pwm3-pin {
	2702	+ uart4 {
	2703	+ uart4_xfer: uart4-xfer {
2414	2704	rockchip,pins =
2415		- <0 RK_PC0 1 &pcfg_pull_none>;
	2705	+ <4 RK_PB1 1 &pcfg_pull_up>,
	2706	+ <4 RK_PB0 1 &pcfg_pull_up>;
2416	2707	};
2417	2708
2418		- pwm3_pin_pull_down: pwm3-pin-pull-down {
	2709	+ uart4_cts: uart4-cts {
2419	2710	rockchip,pins =
2420		- <0 RK_PC0 1 &pcfg_pull_down>;
2421		- };
2422		- };
2423		-
2424		- pwm4 {
2425		- pwm4_pin: pwm4-pin {
2426		- rockchip,pins =
2427		- <0 RK_PA1 2 &pcfg_pull_none>;
	2711	+ <4 RK_PA6 1 &pcfg_pull_none>;
2428	2712	};
2429	2713
2430		- pwm4_pin_pull_down: pwm4-pin-pull-down {
	2714	+ uart4_rts: uart4-rts {
2431	2715	rockchip,pins =
2432		- <0 RK_PA1 2 &pcfg_pull_down>;
2433		- };
2434		- };
2435		-
2436		- pwm5 {
2437		- pwm5_pin: pwm5-pin {
2438		- rockchip,pins =
2439		- <0 RK_PC1 2 &pcfg_pull_none>;
	2716	+ <4 RK_PA7 1 &pcfg_pull_none>;
2440	2717	};
2441	2718
2442		- pwm5_pin_pull_down: pwm5-pin-pull-down {
	2719	+ uart4_rts_pin: uart4-rts-pin {
2443	2720	rockchip,pins =
2444		- <0 RK_PC1 2 &pcfg_pull_down>;
2445		- };
2446		- };
2447		-
2448		- pwm6 {
2449		- pwm6_pin: pwm6-pin {
2450		- rockchip,pins =
2451		- <0 RK_PC2 2 &pcfg_pull_none>;
2452		- };
2453		-
2454		- pwm6_pin_pull_down: pwm6-pin-pull-down {
2455		- rockchip,pins =
2456		- <0 RK_PC2 2 &pcfg_pull_down>;
2457		- };
2458		- };
2459		-
2460		- pwm7 {
2461		- pwm7_pin: pwm7-pin {
2462		- rockchip,pins =
2463		- <2 RK_PB0 2 &pcfg_pull_none>;
2464		- };
2465		-
2466		- pwm7_pin_pull_down: pwm7-pin-pull-down {
2467		- rockchip,pins =
2468		- <2 RK_PB0 2 &pcfg_pull_down>;
2469		- };
2470		- };
2471		-
2472		- pwm8 {
2473		- pwm8_pin: pwm8-pin {
2474		- rockchip,pins =
2475		- <2 RK_PB2 2 &pcfg_pull_none>;
2476		- };
2477		-
2478		- pwm8_pin_pull_down: pwm8-pin-pull-down {
2479		- rockchip,pins =
2480		- <2 RK_PB2 2 &pcfg_pull_down>;
2481		- };
2482		- };
2483		-
2484		- pwm9 {
2485		- pwm9_pin: pwm9-pin {
2486		- rockchip,pins =
2487		- <2 RK_PB3 2 &pcfg_pull_none>;
2488		- };
2489		-
2490		- pwm9_pin_pull_down: pwm9-pin-pull-down {
2491		- rockchip,pins =
2492		- <2 RK_PB3 2 &pcfg_pull_down>;
2493		- };
2494		- };
2495		-
2496		- pwm10 {
2497		- pwm10_pin: pwm10-pin {
2498		- rockchip,pins =
2499		- <2 RK_PB4 2 &pcfg_pull_none>;
2500		- };
2501		-
2502		- pwm10_pin_pull_down: pwm10-pin-pull-down {
2503		- rockchip,pins =
2504		- <2 RK_PB4 2 &pcfg_pull_down>;
2505		- };
2506		- };
2507		-
2508		- pwm11 {
2509		- pwm11_pin: pwm11-pin {
2510		- rockchip,pins =
2511		- <2 RK_PC0 4 &pcfg_pull_none>;
2512		- };
2513		-
2514		- pwm11_pin_pull_down: pwm11-pin-pull-down {
2515		- rockchip,pins =
2516		- <2 RK_PC0 4 &pcfg_pull_down>;
2517		- };
2518		- };
2519		-
2520		- gmac {
2521		- rmii_pins: rmii-pins {
2522		- rockchip,pins =
2523		- /* mac_txen */
2524		- <1 RK_PC1 3 &pcfg_pull_none_12ma>,
2525		- /* mac_txd1 */
2526		- <1 RK_PC3 3 &pcfg_pull_none_12ma>,
2527		- /* mac_txd0 */
2528		- <1 RK_PC2 3 &pcfg_pull_none_12ma>,
2529		- /* mac_rxd0 */
2530		- <1 RK_PC4 3 &pcfg_pull_none>,
2531		- /* mac_rxd1 */
2532		- <1 RK_PC5 3 &pcfg_pull_none>,
2533		- /* mac_rxer */
2534		- <1 RK_PB7 3 &pcfg_pull_none>,
2535		- /* mac_rxdv */
2536		- <1 RK_PC0 3 &pcfg_pull_none>,
2537		- /* mac_mdio */
2538		- <1 RK_PB6 3 &pcfg_pull_none>,
2539		- /* mac_mdc */
2540		- <1 RK_PB5 3 &pcfg_pull_none>;
2541		- };
2542		-
2543		- mac_refclk_12ma: mac-refclk-12ma {
2544		- rockchip,pins =
2545		- <1 RK_PB4 3 &pcfg_pull_none_12ma>;
2546		- };
2547		-
2548		- mac_refclk: mac-refclk {
2549		- rockchip,pins =
2550		- <1 RK_PB4 3 &pcfg_pull_none>;
2551		- };
2552		- };
2553		-
2554		- gmac-m1 {
2555		- rmiim1_pins: rmiim1-pins {
2556		- rockchip,pins =
2557		- /* mac_txen */
2558		- <4 RK_PB7 2 &pcfg_pull_none_12ma>,
2559		- /* mac_txd1 */
2560		- <4 RK_PA5 2 &pcfg_pull_none_12ma>,
2561		- /* mac_txd0 */
2562		- <4 RK_PA4 2 &pcfg_pull_none_12ma>,
2563		- /* mac_rxd0 */
2564		- <4 RK_PA2 2 &pcfg_pull_none>,
2565		- /* mac_rxd1 */
2566		- <4 RK_PA3 2 &pcfg_pull_none>,
2567		- /* mac_rxer */
2568		- <4 RK_PA0 2 &pcfg_pull_none>,
2569		- /* mac_rxdv */
2570		- <4 RK_PA1 2 &pcfg_pull_none>,
2571		- /* mac_mdio */
2572		- <4 RK_PB6 2 &pcfg_pull_none>,
2573		- /* mac_mdc */
2574		- <4 RK_PB5 2 &pcfg_pull_none>;
2575		- };
2576		-
2577		- macm1_refclk_12ma: macm1-refclk-12ma {
2578		- rockchip,pins =
2579		- <4 RK_PB4 2 &pcfg_pull_none_12ma>;
2580		- };
2581		-
2582		- macm1_refclk: macm1-refclk {
2583		- rockchip,pins =
2584		- <4 RK_PB4 2 &pcfg_pull_none>;
2585		- };
2586		- };
2587		-
2588		- rtc {
2589		- rtc_32k: rtc-32k {
2590		- rockchip,pins =
2591		- <0 RK_PC3 1 &pcfg_pull_none>;
2592		- };
2593		- };
2594		-
2595		- can-m0 {
2596		- canm0_pins: canm0-pins {
2597		- rockchip,pins =
2598		- /* can_rxd_m0 */
2599		- <0 RK_PB3 2 &pcfg_pull_none>,
2600		- /* can_txd_m0 */
2601		- <0 RK_PB4 2 &pcfg_pull_none>;
2602		- };
2603		- };
2604		-
2605		- can-m1 {
2606		- canm1_pins: canm1-pins {
2607		- rockchip,pins =
2608		- /* can_rxd_m1 */
2609		- <1 RK_PC6 5 &pcfg_pull_none>,
2610		- /* can_txd_m1 */
2611		- <1 RK_PC7 5 &pcfg_pull_none>;
2612		- };
2613		- };
2614		-
2615		- can-m2 {
2616		- canm2_pins: canm2-pins {
2617		- rockchip,pins =
2618		- /* can_rxd_m2 */
2619		- <2 RK_PA2 4 &pcfg_pull_none>,
2620		- /* can_txd_m2 */
2621		- <2 RK_PA3 4 &pcfg_pull_none>;
2622		- };
2623		- };
2624		-
2625		- owire-m0 {
2626		- owirem0_pins: owirem0-pins {
2627		- rockchip,pins =
2628		- /* owire_m0 */
2629		- <0 RK_PB3 3 &pcfg_pull_none>;
2630		- };
2631		- };
2632		-
2633		- owire-m1 {
2634		- owirem1_pins: owirem1-pins {
2635		- rockchip,pins =
2636		- /* owire_m1 */
2637		- <1 RK_PC6 7 &pcfg_pull_none>;
2638		- };
2639		- };
2640		-
2641		- owire-m2 {
2642		- owirem2_pins: owirem2-pins {
2643		- rockchip,pins =
2644		- /* owire_m2 */
2645		- <2 RK_PA2 5 &pcfg_pull_none>;
	2721	+ <4 RK_PA7 0 &pcfg_pull_none>;
2646	2722	};
2647	2723	};
2648	2724	};
2649	2725	};
	2726	+#include "rk3308bs-pinctrl.dtsi"