forked from ~ljy/RK356X_SDK_RELEASE

hc
2024-01-05 071106ecf68c401173c58808b1cf5f68cc50d390
kernel/arch/arm64/boot/dts/renesas/r8a77970-v3msk.dts
....@@ -21,6 +21,41 @@
2121 stdout-path = "serial0:115200n8";
2222 };
2323
24
+ hdmi-out {
25
+ compatible = "hdmi-connector";
26
+ type = "a";
27
+
28
+ port {
29
+ hdmi_con: endpoint {
30
+ remote-endpoint = <&adv7511_out>;
31
+ };
32
+ };
33
+ };
34
+
35
+ lvds-decoder {
36
+ compatible = "thine,thc63lvd1024";
37
+ vcc-supply = <&vcc_d3_3v>;
38
+
39
+ ports {
40
+ #address-cells = <1>;
41
+ #size-cells = <0>;
42
+
43
+ port@0 {
44
+ reg = <0>;
45
+ thc63lvd1024_in: endpoint {
46
+ remote-endpoint = <&lvds0_out>;
47
+ };
48
+ };
49
+
50
+ port@2 {
51
+ reg = <2>;
52
+ thc63lvd1024_out: endpoint {
53
+ remote-endpoint = <&adv7511_in>;
54
+ };
55
+ };
56
+ };
57
+ };
58
+
2459 memory@48000000 {
2560 device_type = "memory";
2661 /* first 128MB is reserved for secure area. */
....@@ -51,39 +86,13 @@
5186 regulator-always-on;
5287 };
5388
54
- lvds-decoder {
55
- compatible = "thine,thc63lvd1024";
56
- vcc-supply = <&vcc_d3_3v>;
57
-
58
- ports {
59
- #address-cells = <1>;
60
- #size-cells = <0>;
61
-
62
- port@0 {
63
- reg = <0>;
64
- thc63lvd1024_in: endpoint {
65
- remote-endpoint = <&lvds0_out>;
66
- };
67
- };
68
-
69
- port@2 {
70
- reg = <2>;
71
- thc63lvd1024_out: endpoint {
72
- remote-endpoint = <&adv7511_in>;
73
- };
74
- };
75
- };
76
- };
77
-
78
- hdmi-out {
79
- compatible = "hdmi-connector";
80
- type = "a";
81
-
82
- port {
83
- hdmi_con: endpoint {
84
- remote-endpoint = <&adv7511_out>;
85
- };
86
- };
89
+ vcc_vddq_vin0: regulator-2 {
90
+ compatible = "regulator-fixed";
91
+ regulator-name = "VCC_VDDQ_VIN0";
92
+ regulator-min-microvolt = <3300000>;
93
+ regulator-max-microvolt = <3300000>;
94
+ regulator-boot-on;
95
+ regulator-always-on;
8796 };
8897 };
8998
....@@ -99,6 +108,8 @@
99108 phy0: ethernet-phy@0 {
100109 rxc-skew-ps = <1500>;
101110 reg = <0>;
111
+ interrupt-parent = <&gpio1>;
112
+ interrupts = <17 IRQ_TYPE_LEVEL_LOW>;
102113 };
103114 };
104115
....@@ -115,23 +126,6 @@
115126
116127 &extalr_clk {
117128 clock-frequency = <32768>;
118
-};
119
-
120
-&pfc {
121
- avb_pins: avb0 {
122
- groups = "avb0_mdio", "avb0_rgmii", "avb0_txcrefclk";
123
- function = "avb0";
124
- };
125
-
126
- i2c0_pins: i2c0 {
127
- groups = "i2c0";
128
- function = "i2c0";
129
- };
130
-
131
- scif0_pins: scif0 {
132
- groups = "scif0_data";
133
- function = "scif0";
134
- };
135129 };
136130
137131 &i2c0 {
....@@ -156,8 +150,6 @@
156150 adi,input-depth = <8>;
157151 adi,input-colorspace = "rgb";
158152 adi,input-clock = "1x";
159
- adi,input-style = <1>;
160
- adi,input-justification = "evenly";
161153
162154 ports {
163155 #address-cells = <1>;
....@@ -192,6 +184,107 @@
192184 };
193185 };
194186
187
+&mmc0 {
188
+ pinctrl-0 = <&mmc_pins>;
189
+ pinctrl-names = "default";
190
+
191
+ vmmc-supply = <&vcc_d3_3v>;
192
+ vqmmc-supply = <&vcc_vddq_vin0>;
193
+ bus-width = <8>;
194
+ non-removable;
195
+ status = "okay";
196
+};
197
+
198
+&pfc {
199
+ avb_pins: avb0 {
200
+ groups = "avb0_mdio", "avb0_rgmii", "avb0_txcrefclk";
201
+ function = "avb0";
202
+ };
203
+
204
+ i2c0_pins: i2c0 {
205
+ groups = "i2c0";
206
+ function = "i2c0";
207
+ };
208
+
209
+ mmc_pins: mmc_3_3v {
210
+ groups = "mmc_data8", "mmc_ctrl";
211
+ function = "mmc";
212
+ power-source = <3300>;
213
+ };
214
+
215
+ qspi0_pins: qspi0 {
216
+ groups = "qspi0_ctrl", "qspi0_data4";
217
+ function = "qspi0";
218
+ };
219
+
220
+ scif0_pins: scif0 {
221
+ groups = "scif0_data";
222
+ function = "scif0";
223
+ };
224
+};
225
+
226
+&rpc {
227
+ pinctrl-0 = <&qspi0_pins>;
228
+ pinctrl-names = "default";
229
+
230
+ status = "okay";
231
+
232
+ flash@0 {
233
+ compatible = "spansion,s25fs512s", "jedec,spi-nor";
234
+ reg = <0>;
235
+ spi-max-frequency = <50000000>;
236
+ spi-rx-bus-width = <4>;
237
+
238
+ partitions {
239
+ compatible = "fixed-partitions";
240
+ #address-cells = <1>;
241
+ #size-cells = <1>;
242
+
243
+ bootparam@0 {
244
+ reg = <0x00000000 0x040000>;
245
+ read-only;
246
+ };
247
+ cr7@40000 {
248
+ reg = <0x00040000 0x080000>;
249
+ read-only;
250
+ };
251
+ cert_header_sa3@c0000 {
252
+ reg = <0x000c0000 0x080000>;
253
+ read-only;
254
+ };
255
+ bl2@140000 {
256
+ reg = <0x00140000 0x040000>;
257
+ read-only;
258
+ };
259
+ cert_header_sa6@180000 {
260
+ reg = <0x00180000 0x040000>;
261
+ read-only;
262
+ };
263
+ bl31@1c0000 {
264
+ reg = <0x001c0000 0x460000>;
265
+ read-only;
266
+ };
267
+ uboot@640000 {
268
+ reg = <0x00640000 0x0c0000>;
269
+ read-only;
270
+ };
271
+ uboot-env@700000 {
272
+ reg = <0x00700000 0x040000>;
273
+ read-only;
274
+ };
275
+ dtb@740000 {
276
+ reg = <0x00740000 0x080000>;
277
+ };
278
+ kernel@7c0000 {
279
+ reg = <0x007c0000 0x1400000>;
280
+ };
281
+ user@1bc0000 {
282
+ reg = <0x01bc0000 0x2440000>;
283
+ };
284
+ };
285
+ };
286
+};
287
+
195288 &scif0 {
196289 pinctrl-0 = <&scif0_pins>;
197290 pinctrl-names = "default";