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2024-01-05 071106ecf68c401173c58808b1cf5f68cc50d390

 kernel/arch/arm/mm/proc-v7-bugs.c
..
..
@@ -6,7 +6,34 @@
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 #include <asm/cp15.h>
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 #include <asm/cputype.h>
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 #include <asm/proc-fns.h>
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+#include <asm/spectre.h>
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 #include <asm/system_misc.h>
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+
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+#ifdef CONFIG_ARM_PSCI
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+static int __maybe_unused spectre_v2_get_cpu_fw_mitigation_state(void)
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+{
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+	struct arm_smccc_res res;
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+
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+	arm_smccc_1_1_invoke(ARM_SMCCC_ARCH_FEATURES_FUNC_ID,
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+			     ARM_SMCCC_ARCH_WORKAROUND_1, &res);
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+
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+	switch ((int)res.a0) {
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+	case SMCCC_RET_SUCCESS:
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+		return SPECTRE_MITIGATED;
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+
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+	case SMCCC_ARCH_WORKAROUND_RET_UNAFFECTED:
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+		return SPECTRE_UNAFFECTED;
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+
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+	default:
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+		return SPECTRE_VULNERABLE;
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+	}
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+}
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+#else
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+static int __maybe_unused spectre_v2_get_cpu_fw_mitigation_state(void)
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+{
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+	return SPECTRE_VULNERABLE;
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+}
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+#endif
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37
 
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 #ifdef CONFIG_HARDEN_BRANCH_PREDICTOR
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 DEFINE_PER_CPU(harden_branch_predictor_fn_t, harden_branch_predictor_fn);
..
..
@@ -36,13 +63,60 @@
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 	arm_smccc_1_1_hvc(ARM_SMCCC_ARCH_WORKAROUND_1, NULL);
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64
 }
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-static void cpu_v7_spectre_init(void)
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+static unsigned int spectre_v2_install_workaround(unsigned int method)
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 {
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 	const char *spectre_v2_method = NULL;
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 	int cpu = smp_processor_id();
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 	if (per_cpu(harden_branch_predictor_fn, cpu))
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-		return;
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+		return SPECTRE_MITIGATED;
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+
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+	switch (method) {
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+	case SPECTRE_V2_METHOD_BPIALL:
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+		per_cpu(harden_branch_predictor_fn, cpu) =
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+			harden_branch_predictor_bpiall;
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+		spectre_v2_method = "BPIALL";
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+		break;
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+
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+	case SPECTRE_V2_METHOD_ICIALLU:
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+		per_cpu(harden_branch_predictor_fn, cpu) =
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+			harden_branch_predictor_iciallu;
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+		spectre_v2_method = "ICIALLU";
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+		break;
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+
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+	case SPECTRE_V2_METHOD_HVC:
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+		per_cpu(harden_branch_predictor_fn, cpu) =
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+			call_hvc_arch_workaround_1;
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+		cpu_do_switch_mm = cpu_v7_hvc_switch_mm;
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+		spectre_v2_method = "hypervisor";
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+		break;
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+
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+	case SPECTRE_V2_METHOD_SMC:
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+		per_cpu(harden_branch_predictor_fn, cpu) =
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+			call_smc_arch_workaround_1;
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+		cpu_do_switch_mm = cpu_v7_smc_switch_mm;
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+		spectre_v2_method = "firmware";
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+		break;
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+	}
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+
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+	if (spectre_v2_method)
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+		pr_info("CPU%u: Spectre v2: using %s workaround\n",
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+			smp_processor_id(), spectre_v2_method);
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+
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+	return SPECTRE_MITIGATED;
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+}
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+#else
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+static unsigned int spectre_v2_install_workaround(unsigned int method)
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+{
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+	pr_info_once("Spectre V2: workarounds disabled by configuration\n");
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+
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+	return SPECTRE_VULNERABLE;
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+}
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+#endif
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+
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+static void cpu_v7_spectre_v2_init(void)
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+{
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+	unsigned int state, method = 0;
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120
 
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 	switch (read_cpuid_part()) {
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 	case ARM_CPU_PART_CORTEX_A8:
..
..
@@ -51,71 +125,132 @@
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 	case ARM_CPU_PART_CORTEX_A17:
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126
 	case ARM_CPU_PART_CORTEX_A73:
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127
 	case ARM_CPU_PART_CORTEX_A75:
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-		per_cpu(harden_branch_predictor_fn, cpu) =
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-			harden_branch_predictor_bpiall;
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-		spectre_v2_method = "BPIALL";
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+		state = SPECTRE_MITIGATED;
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+		method = SPECTRE_V2_METHOD_BPIALL;
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130
 		break;
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131
 
59
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 	case ARM_CPU_PART_CORTEX_A15:
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133
 	case ARM_CPU_PART_BRAHMA_B15:
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-		per_cpu(harden_branch_predictor_fn, cpu) =
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-			harden_branch_predictor_iciallu;
63
-		spectre_v2_method = "ICIALLU";
134
+		state = SPECTRE_MITIGATED;
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+		method = SPECTRE_V2_METHOD_ICIALLU;
64
136
 		break;
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137
 
66
-#ifdef CONFIG_ARM_PSCI
67
138
 	case ARM_CPU_PART_BRAHMA_B53:
68
139
 		/* Requires no workaround */
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+		state = SPECTRE_UNAFFECTED;
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141
 		break;
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+
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143
 	default:
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 		/* Other ARM CPUs require no workaround */
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-		if (read_cpuid_implementor() == ARM_CPU_IMP_ARM)
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+		if (read_cpuid_implementor() == ARM_CPU_IMP_ARM) {
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+			state = SPECTRE_UNAFFECTED;
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147
 			break;
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-		/* fallthrough */
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-		/* Cortex A57/A72 require firmware workaround */
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+		}
149
+
150
+		fallthrough;
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+
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+	/* Cortex A57/A72 require firmware workaround */
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153
 	case ARM_CPU_PART_CORTEX_A57:
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-	case ARM_CPU_PART_CORTEX_A72: {
78
-		struct arm_smccc_res res;
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+	case ARM_CPU_PART_CORTEX_A72:
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+		state = spectre_v2_get_cpu_fw_mitigation_state();
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+		if (state != SPECTRE_MITIGATED)
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+			break;
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158
 
80
159
 		switch (arm_smccc_1_1_get_conduit()) {
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160
 		case SMCCC_CONDUIT_HVC:
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-			arm_smccc_1_1_hvc(ARM_SMCCC_ARCH_FEATURES_FUNC_ID,
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-					  ARM_SMCCC_ARCH_WORKAROUND_1, &res);
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-			if ((int)res.a0 != 0)
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-				break;
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-			per_cpu(harden_branch_predictor_fn, cpu) =
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-				call_hvc_arch_workaround_1;
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-			cpu_do_switch_mm = cpu_v7_hvc_switch_mm;
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-			spectre_v2_method = "hypervisor";
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+			method = SPECTRE_V2_METHOD_HVC;
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162
 			break;
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163
 
92
164
 		case SMCCC_CONDUIT_SMC:
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-			arm_smccc_1_1_smc(ARM_SMCCC_ARCH_FEATURES_FUNC_ID,
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-					  ARM_SMCCC_ARCH_WORKAROUND_1, &res);
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-			if ((int)res.a0 != 0)
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-				break;
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-			per_cpu(harden_branch_predictor_fn, cpu) =
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-				call_smc_arch_workaround_1;
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-			cpu_do_switch_mm = cpu_v7_smc_switch_mm;
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-			spectre_v2_method = "firmware";
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+			method = SPECTRE_V2_METHOD_SMC;
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166
 			break;
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167
 
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168
 		default:
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+			state = SPECTRE_VULNERABLE;
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170
 			break;
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171
 		}
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172
 	}
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-#endif
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+
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+	if (state == SPECTRE_MITIGATED)
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+		state = spectre_v2_install_workaround(method);
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+
177
+	spectre_v2_update_state(state, method);
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+}
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+
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+#ifdef CONFIG_HARDEN_BRANCH_HISTORY
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+static int spectre_bhb_method;
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+
183
+static const char *spectre_bhb_method_name(int method)
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+{
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+	switch (method) {
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+	case SPECTRE_V2_METHOD_LOOP8:
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+		return "loop";
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+
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+	case SPECTRE_V2_METHOD_BPIALL:
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+		return "BPIALL";
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+
192
+	default:
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+		return "unknown";
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+	}
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+}
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+
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+static int spectre_bhb_install_workaround(int method)
198
+{
199
+	if (spectre_bhb_method != method) {
200
+		if (spectre_bhb_method) {
201
+			pr_err("CPU%u: Spectre BHB: method disagreement, system vulnerable\n",
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+			       smp_processor_id());
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+
204
+			return SPECTRE_VULNERABLE;
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+		}
206
+
207
+		if (spectre_bhb_update_vectors(method) == SPECTRE_VULNERABLE)
208
+			return SPECTRE_VULNERABLE;
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+
210
+		spectre_bhb_method = method;
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+
212
+		pr_info("CPU%u: Spectre BHB: enabling %s workaround for all CPUs\n",
213
+			smp_processor_id(), spectre_bhb_method_name(method));
108
214
 	}
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215
 
110
-	if (spectre_v2_method)
111
-		pr_info("CPU%u: Spectre v2: using %s workaround\n",
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-			smp_processor_id(), spectre_v2_method);
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+	return SPECTRE_MITIGATED;
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217
 }
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218
 #else
115
-static void cpu_v7_spectre_init(void)
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+static int spectre_bhb_install_workaround(int method)
116
220
 {
221
+	return SPECTRE_VULNERABLE;
117
222
 }
118
223
 #endif
224
+
225
+static void cpu_v7_spectre_bhb_init(void)
226
+{
227
+	unsigned int state, method = 0;
228
+
229
+	switch (read_cpuid_part()) {
230
+	case ARM_CPU_PART_CORTEX_A15:
231
+	case ARM_CPU_PART_BRAHMA_B15:
232
+	case ARM_CPU_PART_CORTEX_A57:
233
+	case ARM_CPU_PART_CORTEX_A72:
234
+		state = SPECTRE_MITIGATED;
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+		method = SPECTRE_V2_METHOD_LOOP8;
236
+		break;
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+
238
+	case ARM_CPU_PART_CORTEX_A73:
239
+	case ARM_CPU_PART_CORTEX_A75:
240
+		state = SPECTRE_MITIGATED;
241
+		method = SPECTRE_V2_METHOD_BPIALL;
242
+		break;
243
+
244
+	default:
245
+		state = SPECTRE_UNAFFECTED;
246
+		break;
247
+	}
248
+
249
+	if (state == SPECTRE_MITIGATED)
250
+		state = spectre_bhb_install_workaround(method);
251
+
252
+	spectre_v2_update_state(state, method);
253
+}
119
254
 
120
255
 static __maybe_unused bool cpu_v7_check_auxcr_set(bool *warned,
121
256
 						  u32 mask, const char *msg)
..
..
@@ -145,16 +280,18 @@
145
280
 void cpu_v7_ca8_ibe(void)
146
281
 {
147
282
 	if (check_spectre_auxcr(this_cpu_ptr(&spectre_warned), BIT(6)))
148
-		cpu_v7_spectre_init();
283
+		cpu_v7_spectre_v2_init();
149
284
 }
150
285
 
151
286
 void cpu_v7_ca15_ibe(void)
152
287
 {
153
288
 	if (check_spectre_auxcr(this_cpu_ptr(&spectre_warned), BIT(0)))
154
-		cpu_v7_spectre_init();
289
+		cpu_v7_spectre_v2_init();
290
+	cpu_v7_spectre_bhb_init();
155
291
 }
156
292
 
157
293
 void cpu_v7_bugs_init(void)
158
294
 {
159
-	cpu_v7_spectre_init();
295
+	cpu_v7_spectre_v2_init();
296
+	cpu_v7_spectre_bhb_init();
160
297
 }