~hc/RK356X_SDK_RELEASE.git

..	..	@@ -16,10 +16,7 @@
16	16
17	17	#include <linux/types.h>
18	18
19		-#include <linux/platform_data/hsmmc-omap.h>
20	19	#include "omap_hwmod.h"
21		-#include "i2c.h"
22		-#include "wd_timer.h"
23	20	#include "cm33xx.h"
24	21	#include "prm33xx.h"
25	22	#include "omap_hwmod_33xx_43xx_common_data.h"
..	..	@@ -29,7 +26,6 @@
29	26	#define CLKCTRL(oh, clkctrl) ((oh).prcm.omap4.clkctrl_offs = (clkctrl))
30	27	#define RSTCTRL(oh, rstctrl) ((oh).prcm.omap4.rstctrl_offs = (rstctrl))
31	28	#define RSTST(oh, rstst) ((oh).prcm.omap4.rstst_offs = (rstst))
32		-#define PRCM_FLAGS(oh, flag) ((oh).prcm.omap4.flags = (flag))
33	29
34	30	/*
35	31	* 'l3' class
..	..	@@ -137,58 +133,6 @@
137	133	};
138	134
139	135	/*
140		- * 'pru-icss' class
141		- * Programmable Real-Time Unit and Industrial Communication Subsystem
142		- */
143		-static struct omap_hwmod_class am33xx_pruss_hwmod_class = {
144		- .name = "pruss",
145		-};
146		-
147		-static struct omap_hwmod_rst_info am33xx_pruss_resets[] = {
148		- { .name = "pruss", .rst_shift = 1 },
149		-};
150		-
151		-/* pru-icss */
152		-/* Pseudo hwmod for reset control purpose only */
153		-struct omap_hwmod am33xx_pruss_hwmod = {
154		- .name = "pruss",
155		- .class = &am33xx_pruss_hwmod_class,
156		- .clkdm_name = "pruss_ocp_clkdm",
157		- .main_clk = "pruss_ocp_gclk",
158		- .prcm = {
159		- .omap4 = {
160		- .modulemode = MODULEMODE_SWCTRL,
161		- },
162		- },
163		- .rst_lines = am33xx_pruss_resets,
164		- .rst_lines_cnt = ARRAY_SIZE(am33xx_pruss_resets),
165		-};
166		-
167		-/* gfx */
168		-/* Pseudo hwmod for reset control purpose only */
169		-static struct omap_hwmod_class am33xx_gfx_hwmod_class = {
170		- .name = "gfx",
171		-};
172		-
173		-static struct omap_hwmod_rst_info am33xx_gfx_resets[] = {
174		- { .name = "gfx", .rst_shift = 0, .st_shift = 0},
175		-};
176		-
177		-struct omap_hwmod am33xx_gfx_hwmod = {
178		- .name = "gfx",
179		- .class = &am33xx_gfx_hwmod_class,
180		- .clkdm_name = "gfx_l3_clkdm",
181		- .main_clk = "gfx_fck_div_ck",
182		- .prcm = {
183		- .omap4 = {
184		- .modulemode = MODULEMODE_SWCTRL,
185		- },
186		- },
187		- .rst_lines = am33xx_gfx_resets,
188		- .rst_lines_cnt = ARRAY_SIZE(am33xx_gfx_resets),
189		-};
190		-
191		-/*
192	136	* 'prcm' class
193	137	* power and reset manager (whole prcm infrastructure)
194	138	*/
..	..	@@ -216,84 +160,7 @@
216	160	.sysc = &am33xx_emif_sysc,
217	161	};
218	162
219		-/*
220		- * 'aes0' class
221		- */
222		-static struct omap_hwmod_class_sysconfig am33xx_aes0_sysc = {
223		- .rev_offs = 0x80,
224		- .sysc_offs = 0x84,
225		- .syss_offs = 0x88,
226		- .sysc_flags = SYSS_HAS_RESET_STATUS,
227		-};
228	163
229		-static struct omap_hwmod_class am33xx_aes0_hwmod_class = {
230		- .name = "aes0",
231		- .sysc = &am33xx_aes0_sysc,
232		-};
233		-
234		-struct omap_hwmod am33xx_aes0_hwmod = {
235		- .name = "aes",
236		- .class = &am33xx_aes0_hwmod_class,
237		- .clkdm_name = "l3_clkdm",
238		- .main_clk = "aes0_fck",
239		- .prcm = {
240		- .omap4 = {
241		- .modulemode = MODULEMODE_SWCTRL,
242		- },
243		- },
244		-};
245		-
246		-/* sha0 HIB2 (the 'P' (public) device) */
247		-static struct omap_hwmod_class_sysconfig am33xx_sha0_sysc = {
248		- .rev_offs = 0x100,
249		- .sysc_offs = 0x110,
250		- .syss_offs = 0x114,
251		- .sysc_flags = SYSS_HAS_RESET_STATUS,
252		-};
253		-
254		-static struct omap_hwmod_class am33xx_sha0_hwmod_class = {
255		- .name = "sha0",
256		- .sysc = &am33xx_sha0_sysc,
257		-};
258		-
259		-struct omap_hwmod am33xx_sha0_hwmod = {
260		- .name = "sham",
261		- .class = &am33xx_sha0_hwmod_class,
262		- .clkdm_name = "l3_clkdm",
263		- .main_clk = "l3_gclk",
264		- .prcm = {
265		- .omap4 = {
266		- .modulemode = MODULEMODE_SWCTRL,
267		- },
268		- },
269		-};
270		-
271		-/* rng */
272		-static struct omap_hwmod_class_sysconfig am33xx_rng_sysc = {
273		- .rev_offs = 0x1fe0,
274		- .sysc_offs = 0x1fe4,
275		- .sysc_flags = SYSC_HAS_AUTOIDLE \| SYSC_HAS_SIDLEMODE,
276		- .idlemodes = SIDLE_FORCE \| SIDLE_NO,
277		- .sysc_fields = &omap_hwmod_sysc_type1,
278		-};
279		-
280		-static struct omap_hwmod_class am33xx_rng_hwmod_class = {
281		- .name = "rng",
282		- .sysc = &am33xx_rng_sysc,
283		-};
284		-
285		-struct omap_hwmod am33xx_rng_hwmod = {
286		- .name = "rng",
287		- .class = &am33xx_rng_hwmod_class,
288		- .clkdm_name = "l4ls_clkdm",
289		- .flags = HWMOD_SWSUP_SIDLE,
290		- .main_clk = "rng_fck",
291		- .prcm = {
292		- .omap4 = {
293		- .modulemode = MODULEMODE_SWCTRL,
294		- },
295		- },
296		-};
297	164
298	165	/* ocmcram */
299	166	static struct omap_hwmod_class am33xx_ocmcram_hwmod_class = {
..	..	@@ -351,251 +218,6 @@
351	218	.name = "control",
352	219	};
353	220
354		-/*
355		- * 'cpgmac' class
356		- * cpsw/cpgmac sub system
357		- */
358		-static struct omap_hwmod_class_sysconfig am33xx_cpgmac_sysc = {
359		- .rev_offs = 0x0,
360		- .sysc_offs = 0x8,
361		- .syss_offs = 0x4,
362		- .sysc_flags = (SYSC_HAS_SIDLEMODE \| SYSC_HAS_MIDLEMODE \|
363		- SYSS_HAS_RESET_STATUS),
364		- .idlemodes = (SIDLE_FORCE \| SIDLE_NO \| MSTANDBY_FORCE \|
365		- MSTANDBY_NO),
366		- .sysc_fields = &omap_hwmod_sysc_type3,
367		-};
368		-
369		-static struct omap_hwmod_class am33xx_cpgmac0_hwmod_class = {
370		- .name = "cpgmac0",
371		- .sysc = &am33xx_cpgmac_sysc,
372		-};
373		-
374		-struct omap_hwmod am33xx_cpgmac0_hwmod = {
375		- .name = "cpgmac0",
376		- .class = &am33xx_cpgmac0_hwmod_class,
377		- .clkdm_name = "cpsw_125mhz_clkdm",
378		- .flags = (HWMOD_SWSUP_SIDLE \| HWMOD_SWSUP_MSTANDBY),
379		- .main_clk = "cpsw_125mhz_gclk",
380		- .mpu_rt_idx = 1,
381		- .prcm = {
382		- .omap4 = {
383		- .modulemode = MODULEMODE_SWCTRL,
384		- },
385		- },
386		-};
387		-
388		-/*
389		- * mdio class
390		- */
391		-static struct omap_hwmod_class am33xx_mdio_hwmod_class = {
392		- .name = "davinci_mdio",
393		-};
394		-
395		-struct omap_hwmod am33xx_mdio_hwmod = {
396		- .name = "davinci_mdio",
397		- .class = &am33xx_mdio_hwmod_class,
398		- .clkdm_name = "cpsw_125mhz_clkdm",
399		- .main_clk = "cpsw_125mhz_gclk",
400		-};
401		-
402		-/*
403		- * dcan class
404		- */
405		-static struct omap_hwmod_class am33xx_dcan_hwmod_class = {
406		- .name = "d_can",
407		-};
408		-
409		-/* dcan0 */
410		-struct omap_hwmod am33xx_dcan0_hwmod = {
411		- .name = "d_can0",
412		- .class = &am33xx_dcan_hwmod_class,
413		- .clkdm_name = "l4ls_clkdm",
414		- .main_clk = "dcan0_fck",
415		- .prcm = {
416		- .omap4 = {
417		- .modulemode = MODULEMODE_SWCTRL,
418		- },
419		- },
420		-};
421		-
422		-/* dcan1 */
423		-struct omap_hwmod am33xx_dcan1_hwmod = {
424		- .name = "d_can1",
425		- .class = &am33xx_dcan_hwmod_class,
426		- .clkdm_name = "l4ls_clkdm",
427		- .main_clk = "dcan1_fck",
428		- .prcm = {
429		- .omap4 = {
430		- .modulemode = MODULEMODE_SWCTRL,
431		- },
432		- },
433		-};
434		-
435		-/* elm */
436		-static struct omap_hwmod_class_sysconfig am33xx_elm_sysc = {
437		- .rev_offs = 0x0000,
438		- .sysc_offs = 0x0010,
439		- .syss_offs = 0x0014,
440		- .sysc_flags = (SYSC_HAS_CLOCKACTIVITY \| SYSC_HAS_SIDLEMODE \|
441		- SYSC_HAS_SOFTRESET \| SYSC_HAS_AUTOIDLE \|
442		- SYSS_HAS_RESET_STATUS),
443		- .idlemodes = (SIDLE_FORCE \| SIDLE_NO \| SIDLE_SMART),
444		- .sysc_fields = &omap_hwmod_sysc_type1,
445		-};
446		-
447		-static struct omap_hwmod_class am33xx_elm_hwmod_class = {
448		- .name = "elm",
449		- .sysc = &am33xx_elm_sysc,
450		-};
451		-
452		-struct omap_hwmod am33xx_elm_hwmod = {
453		- .name = "elm",
454		- .class = &am33xx_elm_hwmod_class,
455		- .clkdm_name = "l4ls_clkdm",
456		- .main_clk = "l4ls_gclk",
457		- .prcm = {
458		- .omap4 = {
459		- .modulemode = MODULEMODE_SWCTRL,
460		- },
461		- },
462		-};
463		-
464		-/* pwmss */
465		-static struct omap_hwmod_class_sysconfig am33xx_epwmss_sysc = {
466		- .rev_offs = 0x0,
467		- .sysc_offs = 0x4,
468		- .sysc_flags = (SYSC_HAS_SIDLEMODE \| SYSC_HAS_MIDLEMODE),
469		- .idlemodes = (SIDLE_FORCE \| SIDLE_NO \| SIDLE_SMART \|
470		- SIDLE_SMART_WKUP \| MSTANDBY_FORCE \| MSTANDBY_NO \|
471		- MSTANDBY_SMART \| MSTANDBY_SMART_WKUP),
472		- .sysc_fields = &omap_hwmod_sysc_type2,
473		-};
474		-
475		-struct omap_hwmod_class am33xx_epwmss_hwmod_class = {
476		- .name = "epwmss",
477		- .sysc = &am33xx_epwmss_sysc,
478		-};
479		-
480		-/* epwmss0 */
481		-struct omap_hwmod am33xx_epwmss0_hwmod = {
482		- .name = "epwmss0",
483		- .class = &am33xx_epwmss_hwmod_class,
484		- .clkdm_name = "l4ls_clkdm",
485		- .main_clk = "l4ls_gclk",
486		- .prcm = {
487		- .omap4 = {
488		- .modulemode = MODULEMODE_SWCTRL,
489		- },
490		- },
491		-};
492		-
493		-/* epwmss1 */
494		-struct omap_hwmod am33xx_epwmss1_hwmod = {
495		- .name = "epwmss1",
496		- .class = &am33xx_epwmss_hwmod_class,
497		- .clkdm_name = "l4ls_clkdm",
498		- .main_clk = "l4ls_gclk",
499		- .prcm = {
500		- .omap4 = {
501		- .modulemode = MODULEMODE_SWCTRL,
502		- },
503		- },
504		-};
505		-
506		-/* epwmss2 */
507		-struct omap_hwmod am33xx_epwmss2_hwmod = {
508		- .name = "epwmss2",
509		- .class = &am33xx_epwmss_hwmod_class,
510		- .clkdm_name = "l4ls_clkdm",
511		- .main_clk = "l4ls_gclk",
512		- .prcm = {
513		- .omap4 = {
514		- .modulemode = MODULEMODE_SWCTRL,
515		- },
516		- },
517		-};
518		-
519		-/*
520		- * 'gpio' class: for gpio 0,1,2,3
521		- */
522		-static struct omap_hwmod_class_sysconfig am33xx_gpio_sysc = {
523		- .rev_offs = 0x0000,
524		- .sysc_offs = 0x0010,
525		- .syss_offs = 0x0114,
526		- .sysc_flags = (SYSC_HAS_AUTOIDLE \| SYSC_HAS_ENAWAKEUP \|
527		- SYSC_HAS_SIDLEMODE \| SYSC_HAS_SOFTRESET \|
528		- SYSS_HAS_RESET_STATUS),
529		- .idlemodes = (SIDLE_FORCE \| SIDLE_NO \| SIDLE_SMART \|
530		- SIDLE_SMART_WKUP),
531		- .sysc_fields = &omap_hwmod_sysc_type1,
532		-};
533		-
534		-struct omap_hwmod_class am33xx_gpio_hwmod_class = {
535		- .name = "gpio",
536		- .sysc = &am33xx_gpio_sysc,
537		- .rev = 2,
538		-};
539		-
540		-/* gpio1 */
541		-static struct omap_hwmod_opt_clk gpio1_opt_clks[] = {
542		- { .role = "dbclk", .clk = "gpio1_dbclk" },
543		-};
544		-
545		-struct omap_hwmod am33xx_gpio1_hwmod = {
546		- .name = "gpio2",
547		- .class = &am33xx_gpio_hwmod_class,
548		- .clkdm_name = "l4ls_clkdm",
549		- .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
550		- .main_clk = "l4ls_gclk",
551		- .prcm = {
552		- .omap4 = {
553		- .modulemode = MODULEMODE_SWCTRL,
554		- },
555		- },
556		- .opt_clks = gpio1_opt_clks,
557		- .opt_clks_cnt = ARRAY_SIZE(gpio1_opt_clks),
558		-};
559		-
560		-/* gpio2 */
561		-static struct omap_hwmod_opt_clk gpio2_opt_clks[] = {
562		- { .role = "dbclk", .clk = "gpio2_dbclk" },
563		-};
564		-
565		-struct omap_hwmod am33xx_gpio2_hwmod = {
566		- .name = "gpio3",
567		- .class = &am33xx_gpio_hwmod_class,
568		- .clkdm_name = "l4ls_clkdm",
569		- .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
570		- .main_clk = "l4ls_gclk",
571		- .prcm = {
572		- .omap4 = {
573		- .modulemode = MODULEMODE_SWCTRL,
574		- },
575		- },
576		- .opt_clks = gpio2_opt_clks,
577		- .opt_clks_cnt = ARRAY_SIZE(gpio2_opt_clks),
578		-};
579		-
580		-/* gpio3 */
581		-static struct omap_hwmod_opt_clk gpio3_opt_clks[] = {
582		- { .role = "dbclk", .clk = "gpio3_dbclk" },
583		-};
584		-
585		-struct omap_hwmod am33xx_gpio3_hwmod = {
586		- .name = "gpio4",
587		- .class = &am33xx_gpio_hwmod_class,
588		- .clkdm_name = "l4ls_clkdm",
589		- .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
590		- .main_clk = "l4ls_gclk",
591		- .prcm = {
592		- .omap4 = {
593		- .modulemode = MODULEMODE_SWCTRL,
594		- },
595		- },
596		- .opt_clks = gpio3_opt_clks,
597		- .opt_clks_cnt = ARRAY_SIZE(gpio3_opt_clks),
598		-};
599	221
600	222	/* gpmc */
601	223	static struct omap_hwmod_class_sysconfig gpmc_sysc = {
..	..	@@ -627,789 +249,42 @@
627	249	},
628	250	};
629	251
630		-/* 'i2c' class */
631		-static struct omap_hwmod_class_sysconfig am33xx_i2c_sysc = {
632		- .rev_offs = 0,
633		- .sysc_offs = 0x0010,
634		- .syss_offs = 0x0090,
635		- .sysc_flags = (SYSC_HAS_AUTOIDLE \| SYSC_HAS_CLOCKACTIVITY \|
636		- SYSC_HAS_ENAWAKEUP \| SYSC_HAS_SIDLEMODE \|
637		- SYSC_HAS_SOFTRESET \| SYSS_HAS_RESET_STATUS),
638		- .idlemodes = (SIDLE_FORCE \| SIDLE_NO \| SIDLE_SMART \|
639		- SIDLE_SMART_WKUP),
640		- .sysc_fields = &omap_hwmod_sysc_type1,
641		-};
642		-
643		-static struct omap_hwmod_class i2c_class = {
644		- .name = "i2c",
645		- .sysc = &am33xx_i2c_sysc,
646		- .rev = OMAP_I2C_IP_VERSION_2,
647		- .reset = &omap_i2c_reset,
648		-};
649		-
650		-/* i2c1 */
651		-struct omap_hwmod am33xx_i2c1_hwmod = {
652		- .name = "i2c1",
653		- .class = &i2c_class,
654		- .clkdm_name = "l4_wkup_clkdm",
655		- .flags = HWMOD_16BIT_REG \| HWMOD_SET_DEFAULT_CLOCKACT,
656		- .main_clk = "dpll_per_m2_div4_wkupdm_ck",
657		- .prcm = {
658		- .omap4 = {
659		- .modulemode = MODULEMODE_SWCTRL,
660		- },
661		- },
662		-};
663		-
664		-/* i2c1 */
665		-struct omap_hwmod am33xx_i2c2_hwmod = {
666		- .name = "i2c2",
667		- .class = &i2c_class,
668		- .clkdm_name = "l4ls_clkdm",
669		- .flags = HWMOD_16BIT_REG \| HWMOD_SET_DEFAULT_CLOCKACT,
670		- .main_clk = "dpll_per_m2_div4_ck",
671		- .prcm = {
672		- .omap4 = {
673		- .modulemode = MODULEMODE_SWCTRL,
674		- },
675		- },
676		-};
677		-
678		-/* i2c3 */
679		-struct omap_hwmod am33xx_i2c3_hwmod = {
680		- .name = "i2c3",
681		- .class = &i2c_class,
682		- .clkdm_name = "l4ls_clkdm",
683		- .flags = HWMOD_16BIT_REG \| HWMOD_SET_DEFAULT_CLOCKACT,
684		- .main_clk = "dpll_per_m2_div4_ck",
685		- .prcm = {
686		- .omap4 = {
687		- .modulemode = MODULEMODE_SWCTRL,
688		- },
689		- },
690		-};
691		-
692		-/*
693		- * 'mailbox' class
694		- * mailbox module allowing communication between the on-chip processors using a
695		- * queued mailbox-interrupt mechanism.
696		- */
697		-static struct omap_hwmod_class_sysconfig am33xx_mailbox_sysc = {
698		- .rev_offs = 0x0000,
699		- .sysc_offs = 0x0010,
700		- .sysc_flags = (SYSC_HAS_RESET_STATUS \| SYSC_HAS_SIDLEMODE \|
701		- SYSC_HAS_SOFTRESET),
702		- .idlemodes = (SIDLE_FORCE \| SIDLE_NO \| SIDLE_SMART),
703		- .sysc_fields = &omap_hwmod_sysc_type2,
704		-};
705		-
706		-static struct omap_hwmod_class am33xx_mailbox_hwmod_class = {
707		- .name = "mailbox",
708		- .sysc = &am33xx_mailbox_sysc,
709		-};
710		-
711		-struct omap_hwmod am33xx_mailbox_hwmod = {
712		- .name = "mailbox",
713		- .class = &am33xx_mailbox_hwmod_class,
714		- .clkdm_name = "l4ls_clkdm",
715		- .main_clk = "l4ls_gclk",
716		- .prcm = {
717		- .omap4 = {
718		- .modulemode = MODULEMODE_SWCTRL,
719		- },
720		- },
721		-};
722		-
723		-/*
724		- * 'mcasp' class
725		- */
726		-static struct omap_hwmod_class_sysconfig am33xx_mcasp_sysc = {
727		- .rev_offs = 0x0,
728		- .sysc_offs = 0x4,
729		- .sysc_flags = SYSC_HAS_SIDLEMODE,
730		- .idlemodes = (SIDLE_FORCE \| SIDLE_NO \| SIDLE_SMART),
731		- .sysc_fields = &omap_hwmod_sysc_type3,
732		-};
733		-
734		-static struct omap_hwmod_class am33xx_mcasp_hwmod_class = {
735		- .name = "mcasp",
736		- .sysc = &am33xx_mcasp_sysc,
737		-};
738		-
739		-/* mcasp0 */
740		-struct omap_hwmod am33xx_mcasp0_hwmod = {
741		- .name = "mcasp0",
742		- .class = &am33xx_mcasp_hwmod_class,
743		- .clkdm_name = "l3s_clkdm",
744		- .main_clk = "mcasp0_fck",
745		- .prcm = {
746		- .omap4 = {
747		- .modulemode = MODULEMODE_SWCTRL,
748		- },
749		- },
750		-};
751		-
752		-/* mcasp1 */
753		-struct omap_hwmod am33xx_mcasp1_hwmod = {
754		- .name = "mcasp1",
755		- .class = &am33xx_mcasp_hwmod_class,
756		- .clkdm_name = "l3s_clkdm",
757		- .main_clk = "mcasp1_fck",
758		- .prcm = {
759		- .omap4 = {
760		- .modulemode = MODULEMODE_SWCTRL,
761		- },
762		- },
763		-};
764		-
765		-/* 'mmc' class */
766		-static struct omap_hwmod_class_sysconfig am33xx_mmc_sysc = {
767		- .rev_offs = 0x2fc,
768		- .sysc_offs = 0x110,
769		- .syss_offs = 0x114,
770		- .sysc_flags = (SYSC_HAS_CLOCKACTIVITY \| SYSC_HAS_SIDLEMODE \|
771		- SYSC_HAS_ENAWAKEUP \| SYSC_HAS_SOFTRESET \|
772		- SYSC_HAS_AUTOIDLE \| SYSS_HAS_RESET_STATUS),
773		- .idlemodes = (SIDLE_FORCE \| SIDLE_NO \| SIDLE_SMART),
774		- .sysc_fields = &omap_hwmod_sysc_type1,
775		-};
776		-
777		-static struct omap_hwmod_class am33xx_mmc_hwmod_class = {
778		- .name = "mmc",
779		- .sysc = &am33xx_mmc_sysc,
780		-};
781		-
782		-/* mmc0 */
783		-static struct omap_hsmmc_dev_attr am33xx_mmc0_dev_attr = {
784		- .flags = OMAP_HSMMC_SUPPORTS_DUAL_VOLT,
785		-};
786		-
787		-struct omap_hwmod am33xx_mmc0_hwmod = {
788		- .name = "mmc1",
789		- .class = &am33xx_mmc_hwmod_class,
790		- .clkdm_name = "l4ls_clkdm",
791		- .main_clk = "mmc_clk",
792		- .prcm = {
793		- .omap4 = {
794		- .modulemode = MODULEMODE_SWCTRL,
795		- },
796		- },
797		- .dev_attr = &am33xx_mmc0_dev_attr,
798		-};
799		-
800		-/* mmc1 */
801		-static struct omap_hsmmc_dev_attr am33xx_mmc1_dev_attr = {
802		- .flags = OMAP_HSMMC_SUPPORTS_DUAL_VOLT,
803		-};
804		-
805		-struct omap_hwmod am33xx_mmc1_hwmod = {
806		- .name = "mmc2",
807		- .class = &am33xx_mmc_hwmod_class,
808		- .clkdm_name = "l4ls_clkdm",
809		- .main_clk = "mmc_clk",
810		- .prcm = {
811		- .omap4 = {
812		- .modulemode = MODULEMODE_SWCTRL,
813		- },
814		- },
815		- .dev_attr = &am33xx_mmc1_dev_attr,
816		-};
817		-
818		-/* mmc2 */
819		-static struct omap_hsmmc_dev_attr am33xx_mmc2_dev_attr = {
820		- .flags = OMAP_HSMMC_SUPPORTS_DUAL_VOLT,
821		-};
822		-struct omap_hwmod am33xx_mmc2_hwmod = {
823		- .name = "mmc3",
824		- .class = &am33xx_mmc_hwmod_class,
825		- .clkdm_name = "l3s_clkdm",
826		- .main_clk = "mmc_clk",
827		- .prcm = {
828		- .omap4 = {
829		- .modulemode = MODULEMODE_SWCTRL,
830		- },
831		- },
832		- .dev_attr = &am33xx_mmc2_dev_attr,
833		-};
834		-
835		-/*
836		- * 'rtc' class
837		- * rtc subsystem
838		- */
839		-static struct omap_hwmod_class_sysconfig am33xx_rtc_sysc = {
840		- .rev_offs = 0x0074,
841		- .sysc_offs = 0x0078,
842		- .sysc_flags = SYSC_HAS_SIDLEMODE,
843		- .idlemodes = (SIDLE_FORCE \| SIDLE_NO \|
844		- SIDLE_SMART \| SIDLE_SMART_WKUP),
845		- .sysc_fields = &omap_hwmod_sysc_type3,
846		-};
847		-
848		-static struct omap_hwmod_class am33xx_rtc_hwmod_class = {
849		- .name = "rtc",
850		- .sysc = &am33xx_rtc_sysc,
851		- .unlock = &omap_hwmod_rtc_unlock,
852		- .lock = &omap_hwmod_rtc_lock,
853		-};
854		-
855		-struct omap_hwmod am33xx_rtc_hwmod = {
856		- .name = "rtc",
857		- .class = &am33xx_rtc_hwmod_class,
858		- .clkdm_name = "l4_rtc_clkdm",
859		- .main_clk = "clk_32768_ck",
860		- .prcm = {
861		- .omap4 = {
862		- .modulemode = MODULEMODE_SWCTRL,
863		- },
864		- },
865		-};
866		-
867		-/* 'spi' class */
868		-static struct omap_hwmod_class_sysconfig am33xx_mcspi_sysc = {
869		- .rev_offs = 0x0000,
870		- .sysc_offs = 0x0110,
871		- .syss_offs = 0x0114,
872		- .sysc_flags = (SYSC_HAS_CLOCKACTIVITY \| SYSC_HAS_SIDLEMODE \|
873		- SYSC_HAS_SOFTRESET \| SYSC_HAS_AUTOIDLE \|
874		- SYSS_HAS_RESET_STATUS),
875		- .idlemodes = (SIDLE_FORCE \| SIDLE_NO \| SIDLE_SMART),
876		- .sysc_fields = &omap_hwmod_sysc_type1,
877		-};
878		-
879		-struct omap_hwmod_class am33xx_spi_hwmod_class = {
880		- .name = "mcspi",
881		- .sysc = &am33xx_mcspi_sysc,
882		-};
883		-
884		-/* spi0 */
885		-struct omap_hwmod am33xx_spi0_hwmod = {
886		- .name = "spi0",
887		- .class = &am33xx_spi_hwmod_class,
888		- .clkdm_name = "l4ls_clkdm",
889		- .main_clk = "dpll_per_m2_div4_ck",
890		- .prcm = {
891		- .omap4 = {
892		- .modulemode = MODULEMODE_SWCTRL,
893		- },
894		- },
895		-};
896		-
897		-/* spi1 */
898		-struct omap_hwmod am33xx_spi1_hwmod = {
899		- .name = "spi1",
900		- .class = &am33xx_spi_hwmod_class,
901		- .clkdm_name = "l4ls_clkdm",
902		- .main_clk = "dpll_per_m2_div4_ck",
903		- .prcm = {
904		- .omap4 = {
905		- .modulemode = MODULEMODE_SWCTRL,
906		- },
907		- },
908		-};
909		-
910		-/*
911		- * 'spinlock' class
912		- * spinlock provides hardware assistance for synchronizing the
913		- * processes running on multiple processors
914		- */
915		-
916		-static struct omap_hwmod_class_sysconfig am33xx_spinlock_sysc = {
917		- .rev_offs = 0x0000,
918		- .sysc_offs = 0x0010,
919		- .syss_offs = 0x0014,
920		- .sysc_flags = (SYSC_HAS_AUTOIDLE \| SYSC_HAS_CLOCKACTIVITY \|
921		- SYSC_HAS_ENAWAKEUP \| SYSC_HAS_SIDLEMODE \|
922		- SYSC_HAS_SOFTRESET \| SYSS_HAS_RESET_STATUS),
923		- .idlemodes = (SIDLE_FORCE \| SIDLE_NO \| SIDLE_SMART),
924		- .sysc_fields = &omap_hwmod_sysc_type1,
925		-};
926		-
927		-static struct omap_hwmod_class am33xx_spinlock_hwmod_class = {
928		- .name = "spinlock",
929		- .sysc = &am33xx_spinlock_sysc,
930		-};
931		-
932		-struct omap_hwmod am33xx_spinlock_hwmod = {
933		- .name = "spinlock",
934		- .class = &am33xx_spinlock_hwmod_class,
935		- .clkdm_name = "l4ls_clkdm",
936		- .main_clk = "l4ls_gclk",
937		- .prcm = {
938		- .omap4 = {
939		- .modulemode = MODULEMODE_SWCTRL,
940		- },
941		- },
942		-};
943		-
944		-/* 'timer 2-7' class */
945		-static struct omap_hwmod_class_sysconfig am33xx_timer_sysc = {
946		- .rev_offs = 0x0000,
947		- .sysc_offs = 0x0010,
948		- .syss_offs = 0x0014,
949		- .sysc_flags = SYSC_HAS_SIDLEMODE \| SYSC_HAS_SOFTRESET \|
950		- SYSC_HAS_RESET_STATUS,
951		- .idlemodes = (SIDLE_FORCE \| SIDLE_NO \| SIDLE_SMART \|
952		- SIDLE_SMART_WKUP),
953		- .sysc_fields = &omap_hwmod_sysc_type2,
954		-};
955		-
956		-struct omap_hwmod_class am33xx_timer_hwmod_class = {
957		- .name = "timer",
958		- .sysc = &am33xx_timer_sysc,
959		-};
960		-
961		-/* timer1 1ms */
962		-static struct omap_hwmod_class_sysconfig am33xx_timer1ms_sysc = {
963		- .rev_offs = 0x0000,
964		- .sysc_offs = 0x0010,
965		- .syss_offs = 0x0014,
966		- .sysc_flags = (SYSC_HAS_CLOCKACTIVITY \| SYSC_HAS_SIDLEMODE \|
967		- SYSC_HAS_SOFTRESET \| SYSC_HAS_AUTOIDLE \|
968		- SYSS_HAS_RESET_STATUS),
969		- .idlemodes = (SIDLE_FORCE \| SIDLE_NO \| SIDLE_SMART),
970		- .sysc_fields = &omap_hwmod_sysc_type1,
971		-};
972		-
973		-static struct omap_hwmod_class am33xx_timer1ms_hwmod_class = {
974		- .name = "timer",
975		- .sysc = &am33xx_timer1ms_sysc,
976		-};
977		-
978		-struct omap_hwmod am33xx_timer1_hwmod = {
979		- .name = "timer1",
980		- .class = &am33xx_timer1ms_hwmod_class,
981		- .clkdm_name = "l4_wkup_clkdm",
982		- .main_clk = "timer1_fck",
983		- .prcm = {
984		- .omap4 = {
985		- .modulemode = MODULEMODE_SWCTRL,
986		- },
987		- },
988		-};
989		-
990		-struct omap_hwmod am33xx_timer2_hwmod = {
991		- .name = "timer2",
992		- .class = &am33xx_timer_hwmod_class,
993		- .clkdm_name = "l4ls_clkdm",
994		- .main_clk = "timer2_fck",
995		- .prcm = {
996		- .omap4 = {
997		- .modulemode = MODULEMODE_SWCTRL,
998		- },
999		- },
1000		-};
1001		-
1002		-struct omap_hwmod am33xx_timer3_hwmod = {
1003		- .name = "timer3",
1004		- .class = &am33xx_timer_hwmod_class,
1005		- .clkdm_name = "l4ls_clkdm",
1006		- .main_clk = "timer3_fck",
1007		- .prcm = {
1008		- .omap4 = {
1009		- .modulemode = MODULEMODE_SWCTRL,
1010		- },
1011		- },
1012		-};
1013		-
1014		-struct omap_hwmod am33xx_timer4_hwmod = {
1015		- .name = "timer4",
1016		- .class = &am33xx_timer_hwmod_class,
1017		- .clkdm_name = "l4ls_clkdm",
1018		- .main_clk = "timer4_fck",
1019		- .prcm = {
1020		- .omap4 = {
1021		- .modulemode = MODULEMODE_SWCTRL,
1022		- },
1023		- },
1024		-};
1025		-
1026		-struct omap_hwmod am33xx_timer5_hwmod = {
1027		- .name = "timer5",
1028		- .class = &am33xx_timer_hwmod_class,
1029		- .clkdm_name = "l4ls_clkdm",
1030		- .main_clk = "timer5_fck",
1031		- .prcm = {
1032		- .omap4 = {
1033		- .modulemode = MODULEMODE_SWCTRL,
1034		- },
1035		- },
1036		-};
1037		-
1038		-struct omap_hwmod am33xx_timer6_hwmod = {
1039		- .name = "timer6",
1040		- .class = &am33xx_timer_hwmod_class,
1041		- .clkdm_name = "l4ls_clkdm",
1042		- .main_clk = "timer6_fck",
1043		- .prcm = {
1044		- .omap4 = {
1045		- .modulemode = MODULEMODE_SWCTRL,
1046		- },
1047		- },
1048		-};
1049		-
1050		-struct omap_hwmod am33xx_timer7_hwmod = {
1051		- .name = "timer7",
1052		- .class = &am33xx_timer_hwmod_class,
1053		- .clkdm_name = "l4ls_clkdm",
1054		- .main_clk = "timer7_fck",
1055		- .prcm = {
1056		- .omap4 = {
1057		- .modulemode = MODULEMODE_SWCTRL,
1058		- },
1059		- },
1060		-};
1061		-
1062		-/* tpcc */
1063		-static struct omap_hwmod_class am33xx_tpcc_hwmod_class = {
1064		- .name = "tpcc",
1065		-};
1066		-
1067		-struct omap_hwmod am33xx_tpcc_hwmod = {
1068		- .name = "tpcc",
1069		- .class = &am33xx_tpcc_hwmod_class,
1070		- .clkdm_name = "l3_clkdm",
1071		- .main_clk = "l3_gclk",
1072		- .prcm = {
1073		- .omap4 = {
1074		- .modulemode = MODULEMODE_SWCTRL,
1075		- },
1076		- },
1077		-};
1078		-
1079		-static struct omap_hwmod_class_sysconfig am33xx_tptc_sysc = {
1080		- .rev_offs = 0x0,
1081		- .sysc_offs = 0x10,
1082		- .sysc_flags = (SYSC_HAS_SIDLEMODE \| SYSC_HAS_SOFTRESET \|
1083		- SYSC_HAS_MIDLEMODE),
1084		- .idlemodes = (SIDLE_FORCE \| SIDLE_SMART \| MSTANDBY_FORCE),
1085		- .sysc_fields = &omap_hwmod_sysc_type2,
1086		-};
1087		-
1088		-/* 'tptc' class */
1089		-static struct omap_hwmod_class am33xx_tptc_hwmod_class = {
1090		- .name = "tptc",
1091		- .sysc = &am33xx_tptc_sysc,
1092		-};
1093		-
1094		-/* tptc0 */
1095		-struct omap_hwmod am33xx_tptc0_hwmod = {
1096		- .name = "tptc0",
1097		- .class = &am33xx_tptc_hwmod_class,
1098		- .clkdm_name = "l3_clkdm",
1099		- .flags = HWMOD_SWSUP_SIDLE \| HWMOD_SWSUP_MSTANDBY,
1100		- .main_clk = "l3_gclk",
1101		- .prcm = {
1102		- .omap4 = {
1103		- .modulemode = MODULEMODE_SWCTRL,
1104		- },
1105		- },
1106		-};
1107		-
1108		-/* tptc1 */
1109		-struct omap_hwmod am33xx_tptc1_hwmod = {
1110		- .name = "tptc1",
1111		- .class = &am33xx_tptc_hwmod_class,
1112		- .clkdm_name = "l3_clkdm",
1113		- .flags = (HWMOD_SWSUP_SIDLE \| HWMOD_SWSUP_MSTANDBY),
1114		- .main_clk = "l3_gclk",
1115		- .prcm = {
1116		- .omap4 = {
1117		- .modulemode = MODULEMODE_SWCTRL,
1118		- },
1119		- },
1120		-};
1121		-
1122		-/* tptc2 */
1123		-struct omap_hwmod am33xx_tptc2_hwmod = {
1124		- .name = "tptc2",
1125		- .class = &am33xx_tptc_hwmod_class,
1126		- .clkdm_name = "l3_clkdm",
1127		- .flags = (HWMOD_SWSUP_SIDLE \| HWMOD_SWSUP_MSTANDBY),
1128		- .main_clk = "l3_gclk",
1129		- .prcm = {
1130		- .omap4 = {
1131		- .modulemode = MODULEMODE_SWCTRL,
1132		- },
1133		- },
1134		-};
1135		-
1136		-/* 'uart' class */
1137		-static struct omap_hwmod_class_sysconfig uart_sysc = {
1138		- .rev_offs = 0x50,
1139		- .sysc_offs = 0x54,
1140		- .syss_offs = 0x58,
1141		- .sysc_flags = (SYSC_HAS_SIDLEMODE \| SYSC_HAS_ENAWAKEUP \|
1142		- SYSC_HAS_SOFTRESET \| SYSC_HAS_AUTOIDLE),
1143		- .idlemodes = (SIDLE_FORCE \| SIDLE_NO \| SIDLE_SMART \|
1144		- SIDLE_SMART_WKUP),
1145		- .sysc_fields = &omap_hwmod_sysc_type1,
1146		-};
1147		-
1148		-static struct omap_hwmod_class uart_class = {
1149		- .name = "uart",
1150		- .sysc = &uart_sysc,
1151		-};
1152		-
1153		-struct omap_hwmod am33xx_uart1_hwmod = {
1154		- .name = "uart1",
1155		- .class = &uart_class,
1156		- .clkdm_name = "l4_wkup_clkdm",
1157		- .flags = DEBUG_AM33XXUART1_FLAGS \| HWMOD_SWSUP_SIDLE_ACT,
1158		- .main_clk = "dpll_per_m2_div4_wkupdm_ck",
1159		- .prcm = {
1160		- .omap4 = {
1161		- .modulemode = MODULEMODE_SWCTRL,
1162		- },
1163		- },
1164		-};
1165		-
1166		-struct omap_hwmod am33xx_uart2_hwmod = {
1167		- .name = "uart2",
1168		- .class = &uart_class,
1169		- .clkdm_name = "l4ls_clkdm",
1170		- .flags = HWMOD_SWSUP_SIDLE_ACT,
1171		- .main_clk = "dpll_per_m2_div4_ck",
1172		- .prcm = {
1173		- .omap4 = {
1174		- .modulemode = MODULEMODE_SWCTRL,
1175		- },
1176		- },
1177		-};
1178		-
1179		-/* uart3 */
1180		-struct omap_hwmod am33xx_uart3_hwmod = {
1181		- .name = "uart3",
1182		- .class = &uart_class,
1183		- .clkdm_name = "l4ls_clkdm",
1184		- .flags = HWMOD_SWSUP_SIDLE_ACT,
1185		- .main_clk = "dpll_per_m2_div4_ck",
1186		- .prcm = {
1187		- .omap4 = {
1188		- .modulemode = MODULEMODE_SWCTRL,
1189		- },
1190		- },
1191		-};
1192		-
1193		-struct omap_hwmod am33xx_uart4_hwmod = {
1194		- .name = "uart4",
1195		- .class = &uart_class,
1196		- .clkdm_name = "l4ls_clkdm",
1197		- .flags = HWMOD_SWSUP_SIDLE_ACT,
1198		- .main_clk = "dpll_per_m2_div4_ck",
1199		- .prcm = {
1200		- .omap4 = {
1201		- .modulemode = MODULEMODE_SWCTRL,
1202		- },
1203		- },
1204		-};
1205		-
1206		-struct omap_hwmod am33xx_uart5_hwmod = {
1207		- .name = "uart5",
1208		- .class = &uart_class,
1209		- .clkdm_name = "l4ls_clkdm",
1210		- .flags = HWMOD_SWSUP_SIDLE_ACT,
1211		- .main_clk = "dpll_per_m2_div4_ck",
1212		- .prcm = {
1213		- .omap4 = {
1214		- .modulemode = MODULEMODE_SWCTRL,
1215		- },
1216		- },
1217		-};
1218		-
1219		-struct omap_hwmod am33xx_uart6_hwmod = {
1220		- .name = "uart6",
1221		- .class = &uart_class,
1222		- .clkdm_name = "l4ls_clkdm",
1223		- .flags = HWMOD_SWSUP_SIDLE_ACT,
1224		- .main_clk = "dpll_per_m2_div4_ck",
1225		- .prcm = {
1226		- .omap4 = {
1227		- .modulemode = MODULEMODE_SWCTRL,
1228		- },
1229		- },
1230		-};
1231		-
1232		-/* 'wd_timer' class */
1233		-static struct omap_hwmod_class_sysconfig wdt_sysc = {
1234		- .rev_offs = 0x0,
1235		- .sysc_offs = 0x10,
1236		- .syss_offs = 0x14,
1237		- .sysc_flags = (SYSC_HAS_EMUFREE \| SYSC_HAS_SIDLEMODE \|
1238		- SYSC_HAS_SOFTRESET \| SYSS_HAS_RESET_STATUS),
1239		- .idlemodes = (SIDLE_FORCE \| SIDLE_NO \| SIDLE_SMART \|
1240		- SIDLE_SMART_WKUP),
1241		- .sysc_fields = &omap_hwmod_sysc_type1,
1242		-};
1243		-
1244		-static struct omap_hwmod_class am33xx_wd_timer_hwmod_class = {
1245		- .name = "wd_timer",
1246		- .sysc = &wdt_sysc,
1247		- .pre_shutdown = &omap2_wd_timer_disable,
1248		-};
1249		-
1250		-/*
1251		- * XXX: device.c file uses hardcoded name for watchdog timer
1252		- * driver "wd_timer2, so we are also using same name as of now...
1253		- */
1254		-struct omap_hwmod am33xx_wd_timer1_hwmod = {
1255		- .name = "wd_timer2",
1256		- .class = &am33xx_wd_timer_hwmod_class,
1257		- .clkdm_name = "l4_wkup_clkdm",
1258		- .flags = HWMOD_SWSUP_SIDLE,
1259		- .main_clk = "wdt1_fck",
1260		- .prcm = {
1261		- .omap4 = {
1262		- .modulemode = MODULEMODE_SWCTRL,
1263		- },
1264		- },
1265		-};
1266		-
1267	252	static void omap_hwmod_am33xx_clkctrl(void)
1268	253	{
1269		- CLKCTRL(am33xx_uart2_hwmod, AM33XX_CM_PER_UART1_CLKCTRL_OFFSET);
1270		- CLKCTRL(am33xx_uart3_hwmod, AM33XX_CM_PER_UART2_CLKCTRL_OFFSET);
1271		- CLKCTRL(am33xx_uart4_hwmod, AM33XX_CM_PER_UART3_CLKCTRL_OFFSET);
1272		- CLKCTRL(am33xx_uart5_hwmod, AM33XX_CM_PER_UART4_CLKCTRL_OFFSET);
1273		- CLKCTRL(am33xx_uart6_hwmod, AM33XX_CM_PER_UART5_CLKCTRL_OFFSET);
1274		- CLKCTRL(am33xx_dcan0_hwmod, AM33XX_CM_PER_DCAN0_CLKCTRL_OFFSET);
1275		- CLKCTRL(am33xx_dcan1_hwmod, AM33XX_CM_PER_DCAN1_CLKCTRL_OFFSET);
1276		- CLKCTRL(am33xx_elm_hwmod, AM33XX_CM_PER_ELM_CLKCTRL_OFFSET);
1277		- CLKCTRL(am33xx_epwmss0_hwmod, AM33XX_CM_PER_EPWMSS0_CLKCTRL_OFFSET);
1278		- CLKCTRL(am33xx_epwmss1_hwmod, AM33XX_CM_PER_EPWMSS1_CLKCTRL_OFFSET);
1279		- CLKCTRL(am33xx_epwmss2_hwmod, AM33XX_CM_PER_EPWMSS2_CLKCTRL_OFFSET);
1280		- CLKCTRL(am33xx_gpio1_hwmod, AM33XX_CM_PER_GPIO1_CLKCTRL_OFFSET);
1281		- CLKCTRL(am33xx_gpio2_hwmod, AM33XX_CM_PER_GPIO2_CLKCTRL_OFFSET);
1282		- CLKCTRL(am33xx_gpio3_hwmod, AM33XX_CM_PER_GPIO3_CLKCTRL_OFFSET);
1283		- CLKCTRL(am33xx_i2c2_hwmod, AM33XX_CM_PER_I2C1_CLKCTRL_OFFSET);
1284		- CLKCTRL(am33xx_i2c3_hwmod, AM33XX_CM_PER_I2C2_CLKCTRL_OFFSET);
1285		- CLKCTRL(am33xx_mailbox_hwmod, AM33XX_CM_PER_MAILBOX0_CLKCTRL_OFFSET);
1286		- CLKCTRL(am33xx_mcasp0_hwmod, AM33XX_CM_PER_MCASP0_CLKCTRL_OFFSET);
1287		- CLKCTRL(am33xx_mcasp1_hwmod, AM33XX_CM_PER_MCASP1_CLKCTRL_OFFSET);
1288		- CLKCTRL(am33xx_mmc0_hwmod, AM33XX_CM_PER_MMC0_CLKCTRL_OFFSET);
1289		- CLKCTRL(am33xx_mmc1_hwmod, AM33XX_CM_PER_MMC1_CLKCTRL_OFFSET);
1290		- CLKCTRL(am33xx_spi0_hwmod, AM33XX_CM_PER_SPI0_CLKCTRL_OFFSET);
1291		- CLKCTRL(am33xx_spi1_hwmod, AM33XX_CM_PER_SPI1_CLKCTRL_OFFSET);
1292		- CLKCTRL(am33xx_spinlock_hwmod, AM33XX_CM_PER_SPINLOCK_CLKCTRL_OFFSET);
1293		- CLKCTRL(am33xx_timer2_hwmod, AM33XX_CM_PER_TIMER2_CLKCTRL_OFFSET);
1294		- CLKCTRL(am33xx_timer3_hwmod, AM33XX_CM_PER_TIMER3_CLKCTRL_OFFSET);
1295		- CLKCTRL(am33xx_timer4_hwmod, AM33XX_CM_PER_TIMER4_CLKCTRL_OFFSET);
1296		- CLKCTRL(am33xx_timer5_hwmod, AM33XX_CM_PER_TIMER5_CLKCTRL_OFFSET);
1297		- CLKCTRL(am33xx_timer6_hwmod, AM33XX_CM_PER_TIMER6_CLKCTRL_OFFSET);
1298		- CLKCTRL(am33xx_timer7_hwmod, AM33XX_CM_PER_TIMER7_CLKCTRL_OFFSET);
1299	254	CLKCTRL(am33xx_smartreflex0_hwmod,
1300	255	AM33XX_CM_WKUP_SMARTREFLEX0_CLKCTRL_OFFSET);
1301	256	CLKCTRL(am33xx_smartreflex1_hwmod,
1302	257	AM33XX_CM_WKUP_SMARTREFLEX1_CLKCTRL_OFFSET);
1303		- CLKCTRL(am33xx_uart1_hwmod, AM33XX_CM_WKUP_UART0_CLKCTRL_OFFSET);
1304		- CLKCTRL(am33xx_timer1_hwmod, AM33XX_CM_WKUP_TIMER1_CLKCTRL_OFFSET);
1305		- CLKCTRL(am33xx_i2c1_hwmod, AM33XX_CM_WKUP_I2C0_CLKCTRL_OFFSET);
1306		- CLKCTRL(am33xx_wd_timer1_hwmod, AM33XX_CM_WKUP_WDT1_CLKCTRL_OFFSET);
1307		- CLKCTRL(am33xx_rtc_hwmod, AM33XX_CM_RTC_RTC_CLKCTRL_OFFSET);
1308		- PRCM_FLAGS(am33xx_rtc_hwmod, HWMOD_OMAP4_ZERO_CLKCTRL_OFFSET);
1309		- CLKCTRL(am33xx_mmc2_hwmod, AM33XX_CM_PER_MMC2_CLKCTRL_OFFSET);
1310	258	CLKCTRL(am33xx_gpmc_hwmod, AM33XX_CM_PER_GPMC_CLKCTRL_OFFSET);
1311	259	CLKCTRL(am33xx_l4_ls_hwmod, AM33XX_CM_PER_L4LS_CLKCTRL_OFFSET);
1312	260	CLKCTRL(am33xx_l4_wkup_hwmod, AM33XX_CM_WKUP_L4WKUP_CLKCTRL_OFFSET);
1313	261	CLKCTRL(am33xx_l3_main_hwmod, AM33XX_CM_PER_L3_CLKCTRL_OFFSET);
1314		- CLKCTRL(am33xx_tpcc_hwmod, AM33XX_CM_PER_TPCC_CLKCTRL_OFFSET);
1315		- CLKCTRL(am33xx_tptc0_hwmod, AM33XX_CM_PER_TPTC0_CLKCTRL_OFFSET);
1316		- CLKCTRL(am33xx_tptc1_hwmod, AM33XX_CM_PER_TPTC1_CLKCTRL_OFFSET);
1317		- CLKCTRL(am33xx_tptc2_hwmod, AM33XX_CM_PER_TPTC2_CLKCTRL_OFFSET);
1318		- CLKCTRL(am33xx_gfx_hwmod, AM33XX_CM_GFX_GFX_CLKCTRL_OFFSET);
1319		- CLKCTRL(am33xx_cpgmac0_hwmod, AM33XX_CM_PER_CPGMAC0_CLKCTRL_OFFSET);
1320		- CLKCTRL(am33xx_pruss_hwmod, AM33XX_CM_PER_PRUSS_CLKCTRL_OFFSET);
1321	262	CLKCTRL(am33xx_mpu_hwmod , AM33XX_CM_MPU_MPU_CLKCTRL_OFFSET);
1322	263	CLKCTRL(am33xx_l3_instr_hwmod , AM33XX_CM_PER_L3_INSTR_CLKCTRL_OFFSET);
1323	264	CLKCTRL(am33xx_ocmcram_hwmod , AM33XX_CM_PER_OCMCRAM_CLKCTRL_OFFSET);
1324		- CLKCTRL(am33xx_sha0_hwmod , AM33XX_CM_PER_SHA0_CLKCTRL_OFFSET);
1325		- CLKCTRL(am33xx_aes0_hwmod , AM33XX_CM_PER_AES0_CLKCTRL_OFFSET);
1326		- CLKCTRL(am33xx_rng_hwmod, AM33XX_CM_PER_RNG_CLKCTRL_OFFSET);
1327		-}
1328		-
1329		-static void omap_hwmod_am33xx_rst(void)
1330		-{
1331		- RSTCTRL(am33xx_pruss_hwmod, AM33XX_RM_PER_RSTCTRL_OFFSET);
1332		- RSTCTRL(am33xx_gfx_hwmod, AM33XX_RM_GFX_RSTCTRL_OFFSET);
1333		- RSTST(am33xx_gfx_hwmod, AM33XX_RM_GFX_RSTST_OFFSET);
1334	265	}
1335	266
1336	267	void omap_hwmod_am33xx_reg(void)
1337	268	{
1338	269	omap_hwmod_am33xx_clkctrl();
1339		- omap_hwmod_am33xx_rst();
1340	270	}
1341	271
1342	272	static void omap_hwmod_am43xx_clkctrl(void)
1343	273	{
1344		- CLKCTRL(am33xx_uart2_hwmod, AM43XX_CM_PER_UART1_CLKCTRL_OFFSET);
1345		- CLKCTRL(am33xx_uart3_hwmod, AM43XX_CM_PER_UART2_CLKCTRL_OFFSET);
1346		- CLKCTRL(am33xx_uart4_hwmod, AM43XX_CM_PER_UART3_CLKCTRL_OFFSET);
1347		- CLKCTRL(am33xx_uart5_hwmod, AM43XX_CM_PER_UART4_CLKCTRL_OFFSET);
1348		- CLKCTRL(am33xx_uart6_hwmod, AM43XX_CM_PER_UART5_CLKCTRL_OFFSET);
1349		- CLKCTRL(am33xx_dcan0_hwmod, AM43XX_CM_PER_DCAN0_CLKCTRL_OFFSET);
1350		- CLKCTRL(am33xx_dcan1_hwmod, AM43XX_CM_PER_DCAN1_CLKCTRL_OFFSET);
1351		- CLKCTRL(am33xx_elm_hwmod, AM43XX_CM_PER_ELM_CLKCTRL_OFFSET);
1352		- CLKCTRL(am33xx_epwmss0_hwmod, AM43XX_CM_PER_EPWMSS0_CLKCTRL_OFFSET);
1353		- CLKCTRL(am33xx_epwmss1_hwmod, AM43XX_CM_PER_EPWMSS1_CLKCTRL_OFFSET);
1354		- CLKCTRL(am33xx_epwmss2_hwmod, AM43XX_CM_PER_EPWMSS2_CLKCTRL_OFFSET);
1355		- CLKCTRL(am33xx_gpio1_hwmod, AM43XX_CM_PER_GPIO1_CLKCTRL_OFFSET);
1356		- CLKCTRL(am33xx_gpio2_hwmod, AM43XX_CM_PER_GPIO2_CLKCTRL_OFFSET);
1357		- CLKCTRL(am33xx_gpio3_hwmod, AM43XX_CM_PER_GPIO3_CLKCTRL_OFFSET);
1358		- CLKCTRL(am33xx_i2c2_hwmod, AM43XX_CM_PER_I2C1_CLKCTRL_OFFSET);
1359		- CLKCTRL(am33xx_i2c3_hwmod, AM43XX_CM_PER_I2C2_CLKCTRL_OFFSET);
1360		- CLKCTRL(am33xx_mailbox_hwmod, AM43XX_CM_PER_MAILBOX0_CLKCTRL_OFFSET);
1361		- CLKCTRL(am33xx_mcasp0_hwmod, AM43XX_CM_PER_MCASP0_CLKCTRL_OFFSET);
1362		- CLKCTRL(am33xx_mcasp1_hwmod, AM43XX_CM_PER_MCASP1_CLKCTRL_OFFSET);
1363		- CLKCTRL(am33xx_mmc0_hwmod, AM43XX_CM_PER_MMC0_CLKCTRL_OFFSET);
1364		- CLKCTRL(am33xx_mmc1_hwmod, AM43XX_CM_PER_MMC1_CLKCTRL_OFFSET);
1365		- CLKCTRL(am33xx_spi0_hwmod, AM43XX_CM_PER_SPI0_CLKCTRL_OFFSET);
1366		- CLKCTRL(am33xx_spi1_hwmod, AM43XX_CM_PER_SPI1_CLKCTRL_OFFSET);
1367		- CLKCTRL(am33xx_spinlock_hwmod, AM43XX_CM_PER_SPINLOCK_CLKCTRL_OFFSET);
1368		- CLKCTRL(am33xx_timer2_hwmod, AM43XX_CM_PER_TIMER2_CLKCTRL_OFFSET);
1369		- CLKCTRL(am33xx_timer3_hwmod, AM43XX_CM_PER_TIMER3_CLKCTRL_OFFSET);
1370		- CLKCTRL(am33xx_timer4_hwmod, AM43XX_CM_PER_TIMER4_CLKCTRL_OFFSET);
1371		- CLKCTRL(am33xx_timer5_hwmod, AM43XX_CM_PER_TIMER5_CLKCTRL_OFFSET);
1372		- CLKCTRL(am33xx_timer6_hwmod, AM43XX_CM_PER_TIMER6_CLKCTRL_OFFSET);
1373		- CLKCTRL(am33xx_timer7_hwmod, AM43XX_CM_PER_TIMER7_CLKCTRL_OFFSET);
1374	274	CLKCTRL(am33xx_smartreflex0_hwmod,
1375	275	AM43XX_CM_WKUP_SMARTREFLEX0_CLKCTRL_OFFSET);
1376	276	CLKCTRL(am33xx_smartreflex1_hwmod,
1377	277	AM43XX_CM_WKUP_SMARTREFLEX1_CLKCTRL_OFFSET);
1378		- CLKCTRL(am33xx_uart1_hwmod, AM43XX_CM_WKUP_UART0_CLKCTRL_OFFSET);
1379		- CLKCTRL(am33xx_timer1_hwmod, AM43XX_CM_WKUP_TIMER1_CLKCTRL_OFFSET);
1380		- CLKCTRL(am33xx_i2c1_hwmod, AM43XX_CM_WKUP_I2C0_CLKCTRL_OFFSET);
1381		- CLKCTRL(am33xx_wd_timer1_hwmod, AM43XX_CM_WKUP_WDT1_CLKCTRL_OFFSET);
1382		- CLKCTRL(am33xx_rtc_hwmod, AM43XX_CM_RTC_RTC_CLKCTRL_OFFSET);
1383		- CLKCTRL(am33xx_mmc2_hwmod, AM43XX_CM_PER_MMC2_CLKCTRL_OFFSET);
1384	278	CLKCTRL(am33xx_gpmc_hwmod, AM43XX_CM_PER_GPMC_CLKCTRL_OFFSET);
1385	279	CLKCTRL(am33xx_l4_ls_hwmod, AM43XX_CM_PER_L4LS_CLKCTRL_OFFSET);
1386	280	CLKCTRL(am33xx_l4_wkup_hwmod, AM43XX_CM_WKUP_L4WKUP_CLKCTRL_OFFSET);
1387	281	CLKCTRL(am33xx_l3_main_hwmod, AM43XX_CM_PER_L3_CLKCTRL_OFFSET);
1388		- CLKCTRL(am33xx_tpcc_hwmod, AM43XX_CM_PER_TPCC_CLKCTRL_OFFSET);
1389		- CLKCTRL(am33xx_tptc0_hwmod, AM43XX_CM_PER_TPTC0_CLKCTRL_OFFSET);
1390		- CLKCTRL(am33xx_tptc1_hwmod, AM43XX_CM_PER_TPTC1_CLKCTRL_OFFSET);
1391		- CLKCTRL(am33xx_tptc2_hwmod, AM43XX_CM_PER_TPTC2_CLKCTRL_OFFSET);
1392		- CLKCTRL(am33xx_gfx_hwmod, AM43XX_CM_GFX_GFX_CLKCTRL_OFFSET);
1393		- CLKCTRL(am33xx_cpgmac0_hwmod, AM43XX_CM_PER_CPGMAC0_CLKCTRL_OFFSET);
1394		- CLKCTRL(am33xx_pruss_hwmod, AM43XX_CM_PER_PRUSS_CLKCTRL_OFFSET);
1395	282	CLKCTRL(am33xx_mpu_hwmod , AM43XX_CM_MPU_MPU_CLKCTRL_OFFSET);
1396	283	CLKCTRL(am33xx_l3_instr_hwmod , AM43XX_CM_PER_L3_INSTR_CLKCTRL_OFFSET);
1397	284	CLKCTRL(am33xx_ocmcram_hwmod , AM43XX_CM_PER_OCMCRAM_CLKCTRL_OFFSET);
1398		- CLKCTRL(am33xx_sha0_hwmod , AM43XX_CM_PER_SHA0_CLKCTRL_OFFSET);
1399		- CLKCTRL(am33xx_aes0_hwmod , AM43XX_CM_PER_AES0_CLKCTRL_OFFSET);
1400		- CLKCTRL(am33xx_rng_hwmod, AM43XX_CM_PER_RNG_CLKCTRL_OFFSET);
1401		-}
1402		-
1403		-static void omap_hwmod_am43xx_rst(void)
1404		-{
1405		- RSTCTRL(am33xx_pruss_hwmod, AM43XX_RM_PER_RSTCTRL_OFFSET);
1406		- RSTCTRL(am33xx_gfx_hwmod, AM43XX_RM_GFX_RSTCTRL_OFFSET);
1407		- RSTST(am33xx_pruss_hwmod, AM43XX_RM_PER_RSTST_OFFSET);
1408		- RSTST(am33xx_gfx_hwmod, AM43XX_RM_GFX_RSTST_OFFSET);
1409	285	}
1410	286
1411	287	void omap_hwmod_am43xx_reg(void)
1412	288	{
1413	289	omap_hwmod_am43xx_clkctrl();
1414		- omap_hwmod_am43xx_rst();
1415	290	}