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| 1 | +/* SPDX-License-Identifier: GPL-2.0-only */ |
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| 1 | 2 | /* |
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| 2 | 3 | * Copyright (C) 2004, 2007-2010, 2011-2012 Synopsys, Inc. (www.synopsys.com) |
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| 3 | | - * |
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| 4 | | - * This program is free software; you can redistribute it and/or modify |
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| 5 | | - * it under the terms of the GNU General Public License version 2 as |
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| 6 | | - * published by the Free Software Foundation. |
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| 7 | 4 | */ |
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| 8 | 5 | |
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| 9 | 6 | #ifndef __ASM_ARC_CMPXCHG_H |
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| .. | .. |
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| 23 | 20 | |
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| 24 | 21 | /* |
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| 25 | 22 | * Explicit full memory barrier needed before/after as |
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| 26 | | - * LLOCK/SCOND thmeselves don't provide any such semantics |
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| 23 | + * LLOCK/SCOND themselves don't provide any such semantics |
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| 27 | 24 | */ |
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| 28 | 25 | smp_mb(); |
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| 29 | 26 | |
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| .. | .. |
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| 44 | 41 | return prev; |
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| 45 | 42 | } |
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| 46 | 43 | |
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| 47 | | -#elif !defined(CONFIG_ARC_PLAT_EZNPS) |
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| 44 | +#else /* !CONFIG_ARC_HAS_LLSC */ |
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| 48 | 45 | |
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| 49 | 46 | static inline unsigned long |
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| 50 | 47 | __cmpxchg(volatile void *ptr, unsigned long expected, unsigned long new) |
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| .. | .. |
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| 64 | 61 | return prev; |
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| 65 | 62 | } |
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| 66 | 63 | |
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| 67 | | -#else /* CONFIG_ARC_PLAT_EZNPS */ |
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| 68 | | - |
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| 69 | | -static inline unsigned long |
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| 70 | | -__cmpxchg(volatile void *ptr, unsigned long expected, unsigned long new) |
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| 71 | | -{ |
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| 72 | | - /* |
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| 73 | | - * Explicit full memory barrier needed before/after |
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| 74 | | - */ |
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| 75 | | - smp_mb(); |
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| 76 | | - |
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| 77 | | - write_aux_reg(CTOP_AUX_GPA1, expected); |
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| 78 | | - |
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| 79 | | - __asm__ __volatile__( |
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| 80 | | - " mov r2, %0\n" |
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| 81 | | - " mov r3, %1\n" |
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| 82 | | - " .word %2\n" |
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| 83 | | - " mov %0, r2" |
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| 84 | | - : "+r"(new) |
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| 85 | | - : "r"(ptr), "i"(CTOP_INST_EXC_DI_R2_R2_R3) |
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| 86 | | - : "r2", "r3", "memory"); |
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| 87 | | - |
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| 88 | | - smp_mb(); |
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| 89 | | - |
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| 90 | | - return new; |
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| 91 | | -} |
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| 92 | | - |
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| 93 | | -#endif /* CONFIG_ARC_HAS_LLSC */ |
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| 64 | +#endif |
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| 94 | 65 | |
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| 95 | 66 | #define cmpxchg(ptr, o, n) ({ \ |
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| 96 | 67 | (typeof(*(ptr)))__cmpxchg((ptr), \ |
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| .. | .. |
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| 106 | 77 | */ |
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| 107 | 78 | #define atomic_cmpxchg(v, o, n) ((int)cmpxchg(&((v)->counter), (o), (n))) |
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| 108 | 79 | |
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| 109 | | - |
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| 110 | | -#ifndef CONFIG_ARC_PLAT_EZNPS |
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| 111 | 80 | |
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| 112 | 81 | /* |
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| 113 | 82 | * xchg (reg with memory) based on "Native atomic" EX insn |
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| .. | .. |
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| 170 | 139 | #define xchg(ptr, with) _xchg(ptr, with) |
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| 171 | 140 | |
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| 172 | 141 | #endif |
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| 173 | | - |
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| 174 | | -#else /* CONFIG_ARC_PLAT_EZNPS */ |
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| 175 | | - |
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| 176 | | -static inline unsigned long __xchg(unsigned long val, volatile void *ptr, |
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| 177 | | - int size) |
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| 178 | | -{ |
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| 179 | | - extern unsigned long __xchg_bad_pointer(void); |
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| 180 | | - |
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| 181 | | - switch (size) { |
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| 182 | | - case 4: |
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| 183 | | - /* |
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| 184 | | - * Explicit full memory barrier needed before/after |
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| 185 | | - */ |
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| 186 | | - smp_mb(); |
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| 187 | | - |
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| 188 | | - __asm__ __volatile__( |
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| 189 | | - " mov r2, %0\n" |
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| 190 | | - " mov r3, %1\n" |
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| 191 | | - " .word %2\n" |
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| 192 | | - " mov %0, r2\n" |
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| 193 | | - : "+r"(val) |
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| 194 | | - : "r"(ptr), "i"(CTOP_INST_XEX_DI_R2_R2_R3) |
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| 195 | | - : "r2", "r3", "memory"); |
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| 196 | | - |
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| 197 | | - smp_mb(); |
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| 198 | | - |
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| 199 | | - return val; |
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| 200 | | - } |
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| 201 | | - return __xchg_bad_pointer(); |
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| 202 | | -} |
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| 203 | | - |
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| 204 | | -#define xchg(ptr, with) ({ \ |
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| 205 | | - (typeof(*(ptr)))__xchg((unsigned long)(with), \ |
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| 206 | | - (ptr), \ |
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| 207 | | - sizeof(*(ptr))); \ |
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| 208 | | -}) |
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| 209 | | - |
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| 210 | | -#endif /* CONFIG_ARC_PLAT_EZNPS */ |
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| 211 | 142 | |
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| 212 | 143 | /* |
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| 213 | 144 | * "atomic" variant of xchg() |
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