change wifi driver to cypress

hc

2024-01-05 071106ecf68c401173c58808b1cf5f68cc50d390

 kernel/arch/arc/include/asm/bitops.h
..
..
@@ -1,9 +1,6 @@
1
+/* SPDX-License-Identifier: GPL-2.0-only */
1
2
 /*
2
3
  * Copyright (C) 2004, 2007-2010, 2011-2012 Synopsys, Inc. (www.synopsys.com)
3
- *
4
- * This program is free software; you can redistribute it and/or modify
5
- * it under the terms of the GNU General Public License version 2 as
6
- * published by the Free Software Foundation.
7
4
  */
8
5
 
9
6
 #ifndef _ASM_BITOPS_H
..
..
@@ -88,7 +85,7 @@
88
85
 	return (old & (1 << nr)) != 0;					\
89
86
 }
90
87
 
91
-#elif !defined(CONFIG_ARC_PLAT_EZNPS)
88
+#else /* !CONFIG_ARC_HAS_LLSC */
92
89
 
93
90
 /*
94
91
  * Non hardware assisted Atomic-R-M-W
..
..
@@ -139,55 +136,7 @@
139
136
 	return (old & (1UL << (nr & 0x1f))) != 0;			\
140
137
 }
141
138
 
142
-#else /* CONFIG_ARC_PLAT_EZNPS */
143
-
144
-#define BIT_OP(op, c_op, asm_op)					\
145
-static inline void op##_bit(unsigned long nr, volatile unsigned long *m)\
146
-{									\
147
-	m += nr >> 5;							\
148
-									\
149
-	nr = (1UL << (nr & 0x1f));					\
150
-	if (asm_op == CTOP_INST_AAND_DI_R2_R2_R3)			\
151
-		nr = ~nr;						\
152
-									\
153
-	__asm__ __volatile__(						\
154
-	"	mov r2, %0\n"						\
155
-	"	mov r3, %1\n"						\
156
-	"	.word %2\n"						\
157
-	:								\
158
-	: "r"(nr), "r"(m), "i"(asm_op)					\
159
-	: "r2", "r3", "memory");					\
160
-}
161
-
162
-#define TEST_N_BIT_OP(op, c_op, asm_op)					\
163
-static inline int test_and_##op##_bit(unsigned long nr, volatile unsigned long *m)\
164
-{									\
165
-	unsigned long old;						\
166
-									\
167
-	m += nr >> 5;							\
168
-									\
169
-	nr = old = (1UL << (nr & 0x1f));				\
170
-	if (asm_op == CTOP_INST_AAND_DI_R2_R2_R3)			\
171
-		old = ~old;						\
172
-									\
173
-	/* Explicit full memory barrier needed before/after */		\
174
-	smp_mb();							\
175
-									\
176
-	__asm__ __volatile__(						\
177
-	"	mov r2, %0\n"						\
178
-	"	mov r3, %1\n"						\
179
-	"       .word %2\n"						\
180
-	"	mov %0, r2"						\
181
-	: "+r"(old)							\
182
-	: "r"(m), "i"(asm_op)						\
183
-	: "r2", "r3", "memory");					\
184
-									\
185
-	smp_mb();							\
186
-									\
187
-	return (old & nr) != 0;					\
188
-}
189
-
190
-#endif /* CONFIG_ARC_PLAT_EZNPS */
139
+#endif
191
140
 
192
141
 /***************************************
193
142
  * Non atomic variants
..
..
@@ -229,15 +178,9 @@
229
178
 	/* __test_and_set_bit(), __test_and_clear_bit(), __test_and_change_bit() */\
230
179
 	__TEST_N_BIT_OP(op, c_op, asm_op)
231
180
 
232
-#ifndef CONFIG_ARC_PLAT_EZNPS
233
181
 BIT_OPS(set, |, bset)
234
182
 BIT_OPS(clear, & ~, bclr)
235
183
 BIT_OPS(change, ^, bxor)
236
-#else
237
-BIT_OPS(set, |, CTOP_INST_AOR_DI_R2_R2_R3)
238
-BIT_OPS(clear, & ~, CTOP_INST_AAND_DI_R2_R2_R3)
239
-BIT_OPS(change, ^, CTOP_INST_AXOR_DI_R2_R2_R3)
240
-#endif
241
184
 
242
185
 /*
243
186
  * This routine doesn't need to be atomic.
..
..
@@ -278,7 +221,7 @@
278
221
 	return res;
279
222
 }
280
223
 
281
-static inline int constant_fls(int x)
224
+static inline int constant_fls(unsigned int x)
282
225
 {
283
226
 	int r = 32;
284
227
 
..
..
@@ -300,10 +243,8 @@
300
243
 		x <<= 2;
301
244
 		r -= 2;
302
245
 	}
303
-	if (!(x & 0x80000000u)) {
304
-		x <<= 1;
246
+	if (!(x & 0x80000000u))
305
247
 		r -= 1;
306
-	}
307
248
 	return r;
308
249
 }
309
250
 
..
..
@@ -312,7 +253,7 @@
312
253
  * @result: [1-32]
313
254
  * fls(1) = 1, fls(0x80000000) = 32, fls(0) = 0
314
255
  */
315
-static inline __attribute__ ((const)) int fls(unsigned long x)
256
+static inline __attribute__ ((const)) int fls(unsigned int x)
316
257
 {
317
258
 	if (__builtin_constant_p(x))
318
259
 	       return constant_fls(x);